CY7C194B-15VC

CY7C194B CY7C195B 256 Kb (64K x 4) Static RAM Features • Fast access time: 12 ns, 15 ns, and 25 ns • Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) • CMOS for optimum speed/power • TTL-compatible inputs and outputs • Available in 24 DIP, 24 SOJ, 28 DIP, and 28 SOJ General Description1 The CY7C194B-CY7C195B is a high-performance CMOS Asynchronous SRAM organized as 64K × 4 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected. Output enable (OE) is supported only in CY7C195B.2 See the Truth Table in this data sheet for a complete description of read and write modes. The CY7C194B-CY7C195B is available in 24 DIP, 24 SOJ, 28 DIP, and 28 SOJ package(s). Logic Block Diagram Input Buffer Row Decoder RAM Array Sense Amps I/Ox CE Column Decoder Power Down Circuit WE OE (7C195 only) X A X Product Portfolio 12 ns Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Notes: 1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. All OE-specific descriptions and parameters in this datasheet pertain to CY7C195 only. 15 ns 15 80 10 25 ns 25 80 10 Unit ns mA mA 12 90 10 Cypress Semiconductor Corporation Document #: 38-05409 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 17, 2003 CY7C194B CY7C195B Pin Layout and Specifications CY7C195B 28 DIP (6.9 × 35.6 × 3.5 mm) – P21 NC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 NC NC I/O3 I/O2 I/O1 I/O0 WE CY7C195B 28 SOJ (8 × 18 × 3.5 mm) – V21 NC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 NC NC I/O3 I/O2 I/O1 I/O0 WE Document #: 38-05409 Rev. *A Page 2 of 13 CY7C194B CY7C195B Pin Layout and Specifications (continued) CY7C194B 24 SOJ (8 × 15 × 3.5 mm) – V13 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE CY7C194B 24 DIP (6.6 × 31.8 × 3.5 mm) – P13 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE Document #: 38-05409 Rev. *A Page 3 of 13 CY7C194B CY7C195B Pin Description Pin AX Type Input Address Inputs. Description 28 DIP 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 22, 23, 24, 25, 26, 27 12 16, 17, 18, 19 1, 20, 21 13 28 15 24 DIP 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 11 14, 15, 16, 17 – – 24 13 24 SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 11 14, 15, 16, 17 – – 24 13 28 SOJ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 22, 23, 24, 25, 26, 27 12 16, 17, 18, 19 1, 20, 21 13 28 15 CE I/OX NC OE VCC WE Control Input or Output – Control Supply Control Chip Enable. Data Input/Outputs. No Connect. Pins are not internally connected to the die. Output Enable (CY7C195 only). Power (5.0V). Write Enable. CY7C195B Truth Table CE H L L L OE X L X H WE X H L H I/Ox High Z Data Out Data In High Z Mode Deselect / Power-Down Read Write Selected, outputs disabled Power Standby (ISB) Active (ICC ) Active (ICC ) Active (ICC ) CY7C194B Truth Table CE H L L WE X H L Input/Output High Z Data Out Data In Mode Power-Down Read W rite Power Standby (I SB ) Active (I CC ) Active (I CC ) Document #: 38-05409 Rev. *A Page 4 of 13 CY7C194B CY7C195B Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Parameter TSTG TAMB VCC VCC IOUT VESD ILU Storage Temperature Ambient Temperature with Power Applied (i.e. case temperature) Core Supply Voltage Relative to VSS DC Voltage Applied to any Pin Relative to VSS Output Short-Circuit Current Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-up Current Description Value –65 to +150 –55 to +125 –0.5 to +7.0 –0.5 to VCC + null 20 > 2001 > 200 Unit °C °C V V mA V mA Operating Range Range Commercial Ambient Temperature (TA) 0°C to 70°C Voltage Range (VCC) 5.0V ± 10% DC Electrical Characteristics3 12 ns Parameter VIH VIL VOH VOL ICC ISB1 ISB2 IOZ IIX Description Input HIGH Voltage Input LOW Voltage Output HIGH Volt- VCC = Min., loh = -4.0 ma age Output LOW Volt- VCC = Min., lol = 8.0 ma age VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = FMAX = 1 / tRC Condition Min 2.2 –0.3 2.4 – – – Max VCC + 0.3 0.8 – 0.4 90 30 2.2 –0.3 2.4 – – – 15 ns Min Max VCC + 0.3 0.8 – 0.4 80 30 2.2 –0.5 2.4 – – – 25 ns Min Max VCC + 0.3 0.8 – 0.4 80 30 Unit V V V V mA mA Automatic CE VCC = Max., CE ≥ VIH, VIN ≥ VIH Power-down Cur- or VIN ≤ VIL, f = FMAX rent TTL Inputs Automatic CE VCC = Max., CE ≥ VCC - 0.3v, Power-down Cur- VIN > VCC - 0.3v or VIN ≤ 0.3,f rent CMOS Inputs = 0 Commercial Output Leakage Current Input Load Current GND ≤ Vi ≤ VCC, Output Disabled GND ≤ Vi ≤ VCC – 10 – 10 – 10 mA –5 –5 +5 +5 –5 –5 +5 +5 –5 –5 +5 +5 uA uA Capacitance4 Max Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25C, f = 1 MHz, VCC = 5.0V ALL - PACKAGES 7 10 Unit pF Notes: 3. VIL (min) = –2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05409 Rev. *A Page 5 of 13 CY7C194B CY7C195B AC Test Loads Output Loads R1 VCC VCC Output C1 R2 Output Loads for tHZOE, tHZCE & tHZWE R3 C2 R4 (A)* (B)* All Input Pulses 90% 90% Thevenin Equivalent VCC Output Rth VT VSS 10% 10% Rise Time 1 V/ns Fall Time 1 V/ns * including scope and jig capacitance AC Test Conditions Parameter C1 C2 R1 R2 R3 R4 RTH VTH Description Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Nom. 30 5 480 255 480 255 167 1.73 V Ω Unit pF Thermal Resistance5 Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Conditions Still Air, soldered on a 3 x 4.5 square inches, two-layer printed circuit board 28 SOJ 69 24 SOJ TBD 28 DIP TBD 24 DIP TBD Unit °C/W 29.84 TBD TBD TBD Notes: 5. Test Conditions assume a transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V Document #: 38-05409 Rev. *A Page 6 of 13 CY7C194B CY7C195B AC Electrical Characteristics2 6 Parameter tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid OE to Data Valid OE to Low Z OE to High Z CE to Low Z CE to High Z CE to Power-up CE to Power-down Write Cycle Time CE to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z 78 12 ns Min 12 – 3 – – 0 – 3 – 0 – 12 9 9 0 0 8 7 0 – 3 Max – 12 – 12 6 – 5 – 5 – 12 – – – – – – – – 6 – Min 15 – 3 – – 0 – 3 – 0 – 15 10 10 0 0 9 8 0 – 3 15 ns Max – 15 – 15 7 – 7 – 7 – 15 – – – – – – – – 7 – Min 25 – 3 – – 0 – 3 – 0 – 25 18 20 0 0 18 10 0 3 25 ns Max – 25 – 25 10 – 10 – 10 – 25 – – – – – – – – 10 – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage Document #: 38-05409 Rev. *A Page 7 of 13 CY7C194B CY7C195B Timing Waveforms Read Cycle No. 1 9 10 tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Read Cycle No. 2 2 11 12 tRC Address CE tACE OE tDOE tLZOE Data Out ICC ISB High Z tLZCE tPU 50% Data Valid tPD 50% High Z tHZOE tHZCE VCC Current Notes: 9. Device is continuously selected. OE = VIL = CE. 10. WE is HIGH for Read Cycle. 11. This cycle is OE Controlled and WE is HIGH read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document #: 38-05409 Rev. *A Page 8 of 13 CY7C194B CY7C195B Write Cycle No. 1 (WE Controlled) 2 13 14 15 tWC Address tSCE CE tAW tSA WE tPWE tHA OE tHZOE tSD tHD Data In/Out Undefined see footnotes Data-In Valid Write Cycle No. 2 (CE Controlled)16 17 18 tWC Address tSCE CE tSA tHA tAW WE tSD Data In/Out High Z Data-In Valid tHD High Z Notes: 13. This cycle is WE controlled, OE is HIGH during write. 14. Data In/Out is high impedance if OE = VIH. 15. During this period the I/Os are in output state and input signals should not be applied. 16. This cycle is CE controlled. 17. Data In/Out is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05409 Rev. *A Page 9 of 13 CY7C194B CY7C195B Write Cycle No. 3 (WE Controlled, OE Low) 2 19 t WC Address tSCE CE tAW tSA WE tSD Data In/Out Undefined see footnotes tHA tPWE tHD Undefined See Footnotes Data-In Valid tHZWE tLZWE Ordering Information Speed 12 ns 15 ns 15 ns 15 ns 25 ns 25 ns Ordering Code CY7C195B-12VC CY7C194B-15PC CY7C194B-15VC CY7C195B-15VC CY7C194B-25VC CY7C195B-25PC Package Name V21 P13 V13 V21 V13 P21 Package Type 28 SOJ (8 x 18 x 3.5 mm) 24 DIP (6.6 x 31.8 x 3.5 mm) 24 SOJ (8 x 15 x 3.5 mm) 28 SOJ (8 x 18 x 3.5 mm) 24 SOJ (8 x 15 x 3.5 mm) 28 DIP (6.9 x 35.6 x 3.5 mm) Power Option Standard Standard Standard Standard Standard Standard Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Notes: 19. The cycle is WE controlled, OE low. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 38-05409 Rev. *A Page 10 of 13 CY7C194B CY7C195B Package Diagram 24-Lead (300-Mil) Molded SOJ V13 51-85030-A 28-Lead (300-Mil) Molded SOJ V21 DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID DETAIL A EXTERNAL LEAD DESIGN 14 1 0.291 0.300 0.330 0.350 0.026 0.032 0.014 0.020 OPTION 2 15 28 0.013 0.019 OPTION 1 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE A 0.025 MIN. 0.004 0.007 0.013 0.262 0.272 51-85031-*B Document #: 38-05409 Rev. *A Page 11 of 13 CY7C194B CY7C195B Package Diagram (continued) 24-Lead (300-Mil) PDIP P13 51-85013-*B 28-Lead (300-Mil) Molded DIP P21 51-85014-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05409 Rev. *A Page 12 of 13 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C194B CY7C195B Document History Page Document Title: CY7C194B-CY7C195B 256 Kb (64K x 4) Static RAM Document Number: 38-05409 REV. ** *A ECN No. 129234 129786 Issue Date 09/16/03 09/18/03 Orig. of Change HGK AJU New Data Sheet Found typos in AC Electrical Characteristics table. Modified the following: tSCE from 10, 12 and 20 to 9, 10 and 18; tAW from 10, 12 and 20 to 9, 10 and 20; tPWE from 10, 12 and 20 to 8, 9 and 18. Description of Change Document #: 38-05409 Rev. *A Page 13 of 13