CY7C195-35PC

96 CY7C194 CY7C195 CY7C196 64K x 4 Static RAM Features • High speed — 12 ns • Output enable (OE) feature (7C195 and 7C196) • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs • Automatic power-down when deselected able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and Write Enable (WE) inputs are both LOW. Data on the four input pins (I/O0 through I/O3) is written into the memory location, specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) LOW, while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. A die coat is used to ensure alpha immunity. Functional Description The CY7C194, CY7C195, and CY7C196 are high-performance CMOS static RAMs organized as 65,536 by 4 bits. Easy memory expansion is provided by active LOW Chip En- Logic Block Diagram Pin Configurations DIP/SOJ Top View A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 I/O3 SENSE AMPS I/O2 I/O1 I/O0 CE GND 1 2 3 4 5 6 7C194 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE NC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE1 OE GND DIP/SOJ Top View 1 2 3 4 5 6 7C195 7 7C196 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 NC I/O3 I/O2 I/O1 I/O0 WE C194-3 INPUT BUFFER CE2 (7C196) NC (7C195) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 ROW DECODER 1024 x 64 x 4 ARRAY C194-2 COLUMN DECODER POWER DOWN CE2 (7C196 only) CE1 WE (OE) (7C195 and 7C196 ONLY) C194-1 A0 A11 A12 A13 A14 Selection Guide 7C194-12 7C195-12 7C196-12 12 155 30 7C194-15 7C195-15 7C196-15 15 145 30 7C194-20 7C195-20 7C196-20 20 135 30 7C194-25 7C195-25 7C196-25 25 115 30 7C194-35 7C195-35 7C196-35 35 115 30 7C194-45 7C196-45 45 30 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Cypress Semiconductor Corporation Document #: 38-05162 Rev. ** A15 • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 18, 2001 CY7C194 CY7C195 CY7C196 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V ] Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range 7C194-12 7C195-12 7C196-12 Parameter VOH VOL VIH VIL[1] IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs[4] Automatic CE Power-Down Current —CMOS Inputs[4] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC =Max., IOUT =0 mA, f=fMAX =1/tRC Max. VCC, CE1,2 > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1,2 > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA 2.2 −0.5 −5 −5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 −300 155 30 2.2 −0.5 −5 −5 Max. 7C194-15 7C195-15 7C196-15 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 −300 145 30 Max. Unit V V V V µA µA mA mA mA ISB2 10 10 mA Notes: 1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. Document #: 38-05162 Rev. ** Page 2 of 12 CY7C194 CY7C195 CY7C196 ) Electrical Characteristics Over the Operating Range (continued) 7C194-20 7C195-20 7C196-20 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs[4] Automatic CE Power-Down Current —CMOS Inputs[4] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC=Max., IOUT=0 mA, f=fMAX=1/tRC Max. VCC, CE1,2 > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1,2 > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 –300 135 30 2.2 –0.5 –5 –5 Max. 7C194-25, 35, 45 7C195-25, 35 7C196-25, 35, 45 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 –300 115 30 Max. Unit V V V V µA µA mA mA mA ISB2 15 15 mA Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 10 Unit pF pF AC Test Loads and Waveforms[6] 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255Ω R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255Ω C194-4 R1 481Ω ALL INPUT PULSES 3.0V GND 10% < tr 90% 90% 10% < tr C194-5 Equivalent to: THEVENIN EQUIVALENT É 167Ω OUTPUT 1.73V Notes: 5. Tested initially and after any design or process changes that may affect these parameters. 6. tr = < 3 ns for the -12 and -15 speeds. T.r = < 5 ns for the -20 and slower speeds. Document #: 38-05162 Rev. ** Page 3 of 12 CY7C194 CY7C195 CY7C196 : Switching Characteristics Over the Operating Range[7] 7C194-12 7C195-12 7C196-12 Parameter READ CYCLE tRC tAA tOHA tACE1, tACE2 tDOE tLZOE tHZOE tLZCE1, tLZCE2 tHZCE1, tHZCE2 tPU tPD Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[8] CE LOW to Low Z[8] CE HIGH to High Z[8,8] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[8, 9] 12 9 9 0 0 8 8 0 3 7 0 12 7C195, 7C196 7C195, 7C196 7C195, 7C196 3 5 0 15 0 5 3 7 0 20 3 12 5 0 7 3 9 0 25 12 12 3 15 7 0 9 3 11 0 35 15 15 3 20 9 3 11 3 15 0 45 20 20 3 25 10 3 15 3 15 25 25 3 35 16 3 15 35 35 3 45 16 45 45 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C194-15 7C195-15 7C196-15 7C194-20 7C195-20 7C196-20 7C194-25 7C195-25 7C196-25 7C194-35 7C195-35 7C196-35 7C194-45 7C196-45 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE[10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE 15 10 10 0 0 9 9 0 3 7 20 15 15 0 0 15 10 0 3 10 25 18 20 0 0 18 10 0 3 0 13 35 22 25 0 0 22 15 0 3 0 15 45 22 35 0 0 22 15 0 3 0 20 ns ns ns ns ns ns ns ns ns ns Notes: 7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, and WE LOW. All signals must be LOW to initiate a write and any signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05162 Rev. ** Page 4 of 12 CY7C194 CY7C195 CY7C196 Switching Waveforms Read Cycle No. 1 [11, 12] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C194-8 Read Cycle No. 2 CE1, CE2 [11, 13] t RC tACE OE (7C195 and 7C196) tDOE t LZOE HIGH IMPEDANCE t LZCE t HZOE t HZCE DATA VALID tPD HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT t PU 50% ICC 50% ISB C194-6 Write Cycle No. 1 (CE Controlled) [10, 14, 15] tWC ADDRESS CE1 CE2 (7C196) tSCE tSA tAW tHA WE tSD DATA I/O DATA VALID C194-7 tHD Notes: 11. WE is HIGH for read cycle. 12. Device is continuously selected: CE1 = VIL, CE2 = VIL (7C196), and OE = VIL (7C195 and 7C196). 13. Address valid prior to or coincident with CE1 and CE2 transition LOW. 14. Data I/O will be high impedance if OE = VIH (7C195 and 7C196). 15. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05162 Rev. ** Page 5 of 12 CY7C194 CY7C195 CY7C196 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write for 7C195 and 7C196only) tWC ADDRESS CE1 CE2 (7C196) tAW WE tSA tPWE tHA [10, 14, 15] OE tSD DATA I/O tHZOE DATA VALID C194-8 tHD Write Cycle No. 3 (WE Controlled, OE LOW) [15, 16] tWC ADDRESS CE1 CE2 (7C196) tAW WE tSA tHA tSD DATA I/O tHZWE Note: 16. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. tHD DATA VALID tLZWE C194-9 Document #: 38-05162 Rev. ** Page 6 of 12 CY7C194 CY7C195 CY7C196 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 SB OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25°C ICC ICC 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −55 ISB 25 125 VCC =5.0V VIN =5.0V NORMALIZED I, I CC NORMALIZED I, I CC SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25°C 1.6 1.4 1.2 1.0 AMBIENT TEMPERATURE(°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C VCC =5.0V 0.8 0.6 −55 25 125 OUTPUT SINK CURRENT (mA) SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO DELTA tAA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC NORMALIZED I CC vs.CYCLE TIME 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 VCC =4.5V TA =25°C 1.00 VCC =5.0V TA =25°C VIN =0.5V 0.75 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05162 Rev. ** Page 7 of 12 CY7C194 CY7C195 CY7C196 7C194 Truth Table CE H L L WE X H L High Z Data Out Data In Data I/O Read Write Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) 7C195 Truth Table CE1 H L L L WE X H L H OE X L X H High Z Data Out Data In High Z Data I/O Read Write Deselect Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) 7C196 Truth Table CE1 H X L L L CE2 X H L L L WE X X H L H OE X X L X H Data Out Data In High Z Read Write Deselect Active (ICC) Active (ICC) Active (ICC) High Z Data I/O Mode Deselect/Power-Down Power Standby (ISB) Document #: 38-05162 Rev. ** Page 8 of 12 CY7C194 CY7C195 CY7C196 Ordering Information Speed (ns) 12 15 20 25 35 45 Ordering Code CY7C194-12PC CY7C194-12VC CY7C194-15PC CY7C194-15VC CY7C194-20PC CY7C194-20VC CY7C194-25PC CY7C194-25VC CY7C194-35PC CY7C194-35VC CY7C194-45PC CY7C194-45VC Package Name P13 V13 P13 V13 P13 V13 P13 V13 P13 V13 P13 V13 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ Commercial Commercial Commercial Commercial Commercial Operating Range Commercial Speed (ns) 12 15 20 25 35 45 Ordering Code CY7C195-12PC CY7C195-12VC CY7C195-15PC CY7C195-15VC CY7C195-20PC CY7C195-20VC CY7C195-25PC CY7C195-25VC CY7C195-35PC CY7C195-35VC CY7C195-45PC CY7C195-45VC Package Name P21 V21 P21 V21 P21 V21 P21 V21 P21 V21 P21 V21 Package Name P21 V21 P21 V21 P21 V21 P21 V21 P21 V21 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ Operating Range Commercial Commercial Commercial Commercial Commercial Commercial ) Speed (ns) 12 15 20 25 35 Ordering Code CY7C196-12PC CY7C196-12VC CY7C196-15PC CY7C196-15VC CY7C196-20PC CY7C196-20VC CY7C196-25PC CY7C196-25VC CY7C196-35PC CY7C196-35VC Operating Range Commercial Commercial Commercial Commercial Commercial Document #: 38-05162 Rev. ** Page 9 of 12 CY7C194 CY7C195 CY7C196 Package Diagrams 24-Lead (300-Mil) Molded DIP P13/P13A 51-85013-A 28-Lead (300-Mil) Molded DIP P21 51-85014-B Document #: 38-05162 Rev. ** Page 10 of 12 CY7C194 CY7C195 CY7C196 Package Diagrams (continued) 24-Lead (300-Mil) Molded SOJ V13 51-85030-A 28-Lead (300-Mil) Molded SOJ V21 51-85031-B Document #: 38-05162 Rev. ** Page 11 of 12 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C194 CY7C195 CY7C196 Document Title: CY7C194/CY7C195/CY7C196 64K x 4 Static RAM Document Number: 38-05162 REV. ** ECN NO. 110172 Issue Date 09/29/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00081 to 38-05162 Document #: 38-05162 Rev. ** Page 12 of 12