CY7C197-45VC

97 CY7C197 256Kx1 Static RAM Features • High speed — 12 ns • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs • Automatic power-down when deselected vided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C197 has an automatic power-down feature, reducing the power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking chip enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data output (DOUT) pin. The output pin stays in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C197 utilizes a die coat to insure alpha immunity. Functional Description The CY7C197 is a high-performance CMOS static RAM organized as 256K words by 1 bit. Easy memory expansion is pro- Logic Block Diagram DI Pin Configurations DIP/SOJ Top View INPUT BUFFER A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A0 A1 A2 A3 A4 A5 A6 A7 A8 DOUT WE GND 1 24 2 23 3 22 4 21 5 20 7C197 19 6 18 7 8 17 9 16 10 15 14 11 12 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 DIN CE C197-2 CE LCC Top View A2 A1 A0 V CC A 17 NC A3 A4 A5 A6 A7 A8 DOUT NC 3 2 1 28 27 4 26 NC 5 25 A16 6 24 A15 7 23 A14 8 7C197 22 A13 9 21 A12 10 20 A11 11 19 A10 12 18 NC 1314151617 WE GND CE DIN A9 C197-3 ROW DECODER 1024 x 256 ARRAY SENSE AMPS DO COLUMN DECODER POWER DOWN A5 A6 A7 A8 A9 A10 A11 A12 WE C197-1 Selection Guide 7C197-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 12 150 30 7C197-15 15 140 30 7C197-20 20 135 30 7C197-25 25 95 30 7C197-35 35 95 30 30 7C197-45 45 Cypress Semiconductor Corporation Document #: 38-05049 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C197 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................−65°C to +150°C Ambient Temperature with Power Applied ..................................................−55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................... −0.5V to VCC + 0.5V DC Input Voltage[1].................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range 7C197-12 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[2] VCC Operating Supply Current Automatic CE Power-Down Current—TTL Inputs[3] Automatic CE Power-Down Current—CMOS Inputs[3] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min. IOL =12.0 mA 2.2 −0.5 −5 −5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 −300 150 30 10 2.2 −0.5 −5 −5 Max. 7C197-15 Min. 2.4 0.4 VCC +0.3V 0.8 +5 +5 −300 140 30 10 Max. Unit V V V V µA µA mA mA mA mA Notes: 1. V(min.) = −2.0V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. Document #: 38-05049 Rev. ** Page 2 of 10 CY7C197 Electrical Characteristics Over the Operating Range (continued) 7C197-20 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[2] VCC Operating Supply Current Automatic CE Power Down Current—TTL Inputs[3] Automatic CE Power-Down Current—CMOS Inputs[3] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min. IOL =12.0mA 2.2 −0.5 −5 −5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 −300 135 30 15 2.2 −0.5 −5 −5 Max. 7C197-25, 35, 45 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 −300 95 30 15 Max. Unit V V V V µA µA mA mA mA mA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 10 Unit pF pF AC Test Loads and Waveforms[5] R1 329 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: 5V OUTPUT R2 5 pF 202Ω (255Ω MIL) INCLUDING JIG AND SCOPE R2 255Ω (255Ω MIL) 3.0V 10% GND < tr < tr C197-5 R1 329 Ω ALL INPUT PULSES 90% 90% 10% (a) (b) C197-4 THÉVENIN EQUIVALENT 125Ω OUTPUT 1.90V Commercial Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. tr = < 3 ns for the -12 and -15 speeds. tr = < 5 ns for the -20 and slower speeds. Document #: 38-05049 Rev. ** Page 3 of 10 CY7C197 Switching Characteristics Over the Operating Range[6] 7C197-12 Parameter READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid CE LOW to Low Z[7] CE HIGH to High Z[7, 8] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[7,8] 12 9 9 0 0 8 8 0 2 7 0 12 3 5 0 15 3 12 3 7 12 12 3 15 3 0 0 20 9 15 15 3 20 3 0 0 20 11 20 20 3 25 3 0 0 25 15 25 25 3 35 3 0 0 30 15 35 35 3 45 45 45 ns ns ns ns ns ns ns ns Description Min. Max. 7C197-15 Min. Max. 7C197-20 Min. Max. 7C197-25 Min. Max. 7C197-35 Min. Max. 7C197-45 Min. Max. Unit WRITE CYCLE[9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE 15 10 10 0 0 9 9 0 2 7 20 15 15 0 0 15 10 0 3 0 10 25 20 20 0 0 20 15 0 3 0 11 35 30 30 0 0 25 17 0 3 0 15 45 40 40 0 0 30 20 0 3 0 15 ns ns ns ns ns ns ns ns ns ns Notes: 6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05049 Rev. ** Page 4 of 10 CY7C197 Switching Waveforms Read Cycle No. 1 [10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID C197-6 Read Cycle No. 2 [10] CE tACE tLZCE DATA OUT HIGH IMPEDANCE DATA VALID tPD ICC 50% 50% ISB tHZCE HIGH IMPEDANCE tRC VCC SUPPLY CURRENT tPU C197-7 Write Cycle No.1 (WE Controlled) [9] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE C197-8 tAW tPWE tHA tHD Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE = VIL. Document #: 38-05049 Rev. ** Page 5 of 10 CY7C197 Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA OUT DATA VALID HIGH IMPEDANCE C197-9 [9, 12] tWC tSCE tHA tHD Note: 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05049 Rev. ** Page 6 of 10 CY7C197 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE SB 1.4 NORMALIZED I, I SB CC 1.2 1.0 0.8 0.6 0.4 0.2 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 ICC 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 AMBIENT TEMPERATURE(°C) VCC =5.0V VIN =5.0V OUTPUT SOURCE CURRENT (mA) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) VCC =5.0V TA =25°C VIN =5.0V TA =25°C ISB 4.5 5.0 5.5 6.0 0.0 4.0 SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25°C 1.6 1.4 1.2 1.0 NORMALIZED I,CC I ICC OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 140 120 100 80 60 40 20 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE VCC =5.0V 0.8 0.6 −55 25 125 VCC =5.0V TA =25°C 0 0.0 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 (ns) NORMALIZED I PO 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED I CC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 VCC =4.5V TA =25°C NORMALIZED I CC vs. CYCLE TIME 1.25 VCC =5.0V TA =25°C VIN =0.5V DELTA tAA 1.00 0.75 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05049 Rev. ** Page 7 of 10 CY7C197 CY7C197 Truth Table CE H L L WE X H L High Z Data Out Data In Input/Output Deselect/Power-Down Read Write Mode Ordering Information Speed (ns) 12 15 20 25 35 45 Ordering Code CY7C197-12PC CY7C197-12VC CY7C197-15PC CY7C197-15VC CY7C197-20PC CY7C197-20VC CY7C197-25PC CY7C197-25VC CY7C197-35PC CY7C197-35VC CY7C197-45PC CY7C197-45VC Package Name P13 V13 P13 V13 P13 V13 P13 V13 P13 V13 P13 V13 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ Commercial Commercial Commercial Commercial Commercial Operating Range Commercial Document #: 38-05049 Rev. ** Page 8 of 10 CY7C197 Package Diagrams 24-Lead (300-Mil) Molded DIP P13/P13A 51-85013-A 24-Lead (300-Mil) Molded SOJ V13 51-85030-A Document #: 38-05049 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C197 Document Title: CY7C197 256K x 1 Static RAM Document Number: 38-05049 REV. ** ECN NO. 107151 Issue Date 09/10/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00078 to 38-05049 Document #: 38-05049 Rev. ** Page 10 of 10