CY7C197B-25PC

CY7C197B 256 Kb (256K x 1) Static RAM Features • Fast access time: 12 ns and 25 ns • Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) • CMOS for optimum speed/power • TTL-compatible Inputs and Outputs • Available in 24 DIP and 24 SOJ General Description1 The CY7C197B is a high-performance CMOS Asynchronous SRAM organized as 256K × 1 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected. See the Truth Table in this data sheet for a complete description of read and write modes. The CY7C197B is available in 24 DIP and 24 SOJ package(s). Logic Block Diagram Din Input Buffer Row Decoder RAM Array Sense Amps Dout CE Column Decoder Power Down Circuit WE x Ax Product Portfolio 12 ns Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 12 150 10 25 ns 25 95 10 Unit ns mA mA Notes: 1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05410 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 15, 2003 CY7C197B Pin Layout and Specifications 24 DIP (6.6 × 31.8 × 3.5 mm) – P13 A0 A1 A2 A3 A4 A5 A6 A7 A8 Dout WE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 Din CE 24 SOJ (8 × 15 × 3.5 mm) – V13 A0 A1 A2 A3 A4 A5 A6 A7 A8 Dout WE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 Din CE Document #: 38-05410 Rev. ** Page 2 of 10 CY7C197B Pin Description Pin AX Type Input Address Inputs. Description DIP SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 18, 19, 20, 21, 22, 23 23 13 14 10 24 11 13 14 10 24 11 CE Din Dout VCC WE Control Input Output Supply Control Chip Enable. Data Input Pins. Data Output Pins. Power (5.0V). Write Enable. Truth Table CE H L L WE X H L Input/Output High Z Data Out Data In Mode Deselect/Power-Down Read Write Power Standby (ISB) Active (ICC) Active (ICC ) Document #: 38-05410 Rev. ** Page 3 of 10 CY7C197B Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Parameter TSTG TAMB VCC VIN, VOUT IOUT VESD ILU Storage Temperature Ambient Temperature with Power Applied (i.e., case temperature) Core Supply Voltage Relative to VSS DC Voltage Applied to any Pin Relative to VSS Output Short-Circuit Current Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-up Current Description Value –65 to +150 –55 to +125 –0.5 to +7.0 –0.5 to VCC + 0.5 20 > 2001 > 200 Unit °C °C V V mA V mA Operating Range Range Commercial Ambient Temperature (TA) 0°C to 70°C Voltage Range (VCC) 5.0V ± 10% DC Electrical Characteristics2 12 ns Parameter VIH VIL VOH VOL ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage VCC Operating Supply Current Automatic CE Power-down Current TTL Inputs Automatic CE Power-down Current CMOS Inputs Input Load Current VCC = Min., IOH = –4.0 mA VCC = Min., lol = 8.0 mA VCC = Max., IOUT = 0 mA, f = FMAX = 1/tRC VCC = Max., CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = FMAX VCC = Max., CE ≥ VCC – 0.3v, VIN ≥ VCC – 0.3v or VIN < 0.3v, f = 0 – Condition Min 2.2 –0.3 2.4 – – – Max VCC+0.3 0.8 – 0.4 150 30 Min 2.2 –0.3 2.4 – – – 25 ns Max VCC+0.3 0.8 – 0.4 95 30 Unit V V V V mA mA ISB2 – 10 – 10 mA IOZ IIX Output Leakage Current GND ≤ Vi ≤ VCC, Output Disabled GND ≤ Vi ≤ VCC –5 –5 +5 +5 –5 –5 +5 +5 uA uA Capacitance3 Max Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25C, f = 1 MHz, VCC = 5.0V ALL – PACKAGES 8 10 Unit pF Notes: 2. VIL (min) = –2.0V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05410 Rev. ** Page 4 of 10 CY7C197B AC Test Loads Output Loads R1 VCC VCC Output C1 R2 Output Loads for tHZOE, tHZCE & tHZWE R3 C2 R4 (A)* (B)* Thevenin Equivalent All Input Pulses VCC 90% 90% Output Rth VT VSS 10% 10% Rise Time 1 V/ns Fall Time 1 V/ns * including scope and jig capacitance AC Test Conditions Parameter C1 C2 R1 R2 R3 R4 RTH VTH Description Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Nom. 30 5 480 255 480 255 167 1.73 V Ω Unit pF Thermal Resistance4 Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Conditions Still Air, soldered on a 3 × 4.5 square inches, two-layer printed circuit board All – Packages TBD TBD Unit °C/W Notes: 4. Test conditions assume a transition time of 3 ns or less for –12 speed and 5 ns or less for –25 speed, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. Document #: 38-05410 Rev. ** Page 5 of 10 CY7C197B AC Electrical Characteristics5 6 7 12 ns Parameter Description Min Max Min 25 ns Max Unit tRC tAA tOHA tACE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid CE to Low Z CE to High Z CE to Power-up CE to Power-down Write Cycle Time CE to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z 12 – 3 – 3 – 0 – 12 9 9 0 0 8 8 0 – 2 – 12 – 12 – 5 – 12 – – – – – – – – 7 – 25 – 3 – 3 – 0 – 25 20 20 0 0 20 15 0 – 3 – 25 – 25 – 11 – 20 – – – – – – – – 11 – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZCE and tLZCE are specified with CL = 5 pF as in part (B) in AC Test Loads and Waveforms. Transition is measured +/-500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05410 Rev. ** Page 6 of 10 CY7C197B Timing Waveforms Read Cycle No. 1 8 9 tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Read Cycle No. 2 8 tRC Address CE tACE tLZCE tHZCE High Z Data Out tPU Data Valid High Z ICC Vcc Supply Current ISB tPD 50% 50% Notes: 8. WE is HIGH for ready cycle. 9. Device is continuously selected, CE = VIL. Document #: 38-05410 Rev. ** Page 7 of 10 CY7C197B Write Cycle No. 1 (WE Controlled)7 tWC Address tSCE CE tAW tSA WE tSD Data Valid tHZWE Data Out Data Undefined tLZWE High Impedance tHD tPWE tHA Data In Write Cycle No. 2 (CE Controlled)7 10 tWC Address tSA CE tHA tAW tPWE WE tSD Data In Data Valid High Z tHD tSCE Data Out Notes: Notes: 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. Document #: 38-05410 Rev. ** Page 8 of 10 CY7C197B Ordering Information Speed Ordering Code Package Name Package Type Power Option Operating Range 12 ns 25 ns CY7C197B-12VC CY7C197B-25PC V13 P13 24 SOJ (8 x 15 x 3.5 mm) 24 DIP (6.6 x 31.8 x 3.5 mm) Standard Standard Commercial Commercial Package Diagram 24-Lead (300-Mil) Molded SOJ V13 51-85030-*A 24-Lead (300-Mil) PDIP P13 51-85013-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05410 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C197B Document History Page Document Title: CY7C197B 256 Kb (256K x 1) Static RAM Document Number: 38-05410 REV. ECN No. Issue Date Orig. of Change Description of Change ** 129235 09/16/03 HGK New Data Sheet Document #: 38-05410 Rev. ** Page 10 of 10