CY7C197D-12PXI

PRELIMINARY CY7C197D 256K (256K x 1) Static RAM Features • Pin- and function-compatible with CY7C197B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — ICC = 60 mA @ 10 ns • Low CMOS standby power — ISB2 = 3 mA • TTL-compatible inputs and outputs • Data retention at 2.0V • Automatic power-down when deselected • Available in Pb-Free Packages Functional Description[1] The CY7C197D is a high-performance CMOS static RAM organized as 256K words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C197D has an automatic power-down feature, reducing the power consumption when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking chip enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data output (DOUT) pin. The output pin stays in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C197D is available in standard 24-Lead DIP and SOJ Pb-Free Packages. Logic Block Diagram DI Pin Configurations DIP/SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 1 24 2 23 22 3 4 21 5 20 6 7C197D 19 18 7 8 17 9 16 10 15 14 11 12 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 DIN CE INPUT BUFFER A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 ROW DECODER 1024 x 256 ARRAY SENSE AMPS DO COLUMN DECODER POWER DOWN CE DOUT WE GND A5 A6 A7 A8 A9 A10 A11 A12 WE Selection Guide CY7C197D-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 10 60 3 CY7C197D-12 12 50 3 CY7C197D-15 15 40 3 Note: 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05458 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 11, 2005 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................−65°C to +150°C Ambient Temperature with Power Applied ..................................................−55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[2] ....................................... −0.5V to VCC + 0.5V CY7C197D DC Input Voltage[2].................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C −40°C to +85°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range 7C197D-10 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND < VI < VCC GND < VO < VCC, Output Disabled Input Load Current Output Leakage Current Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA 2.0 −0.5 −1 −1 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 −300 60 10 3 2.0 −0.5 −1 −1 Max. 7C197D-12 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +1 −300 50 10 3 7C197D-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current Output Short Circuit Current Automatic CE Power Down Current—TTL Inputs Automatic CE Power-Down Current—CMOS Inputs [3] Max. Unit V V V V µA µA mA mA mA mA Output Short Circuit Current[3] VCC = Max., VOUT = GND VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Power-down Current—TTL Inputs Automatic CE Power-down Current—CMOS Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 Max. 0.4 Unit V V V V µA µA mA mA mA mA 2.0 −0.5 GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V −1 −1 VCC + 0.3V 0.8 +1 +1 −300 40 10 3 VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 10 Unit pF pF Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05458 Rev. *C Page 2 of 8 PRELIMINARY Thermal Resistance[4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient)[4] Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board CY7C197D All-Packages TBD TBD Unit °C/W °C/W AC Test Loads and Waveforms[5] 10-ns Device OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 12, 15 -ns Devices Z = 50Ω ALL INPUT PULSES 3.0V 10% < tr R1 480 Ω High-Z characteristics: R1 480 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255Ω 5 pF INCLUDING JIG AND SCOPE R2 255Ω 90% 90% 10% < tr 30 pF* GND (a) Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V 5V OUTPUT (b) (c) Switching Characteristics Over the Operating Range[6] 7C197D-10 Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tLZCE tHZCE tPU tPD tSCE tHA tSA Write Cycle tWC tAW VCC(typical) to the first access Read Cycle Time Address to Data Valid Output Hold from Address Change CE LOW to Data Valid CE LOW to Low Z[8] CE HIGH to High Z[8, 9] 0 10 8 0 0 10 7 9 0 0 12 9 CE LOW to Power-Up CE HIGH to Power-Down CE LOW to Write End Address Hold from Write End Address Set-Up to Write Start [10] 7C197D-12 Min. 100 12 Max. 7C197D-15 Min. 100 15 Max. Unit µs ns 15 3 15 3 7 0 15 10 0 0 15 10 ns ns ns ns ns ns ns ns ns ns ns ns Description Min. 100 10 Max. 10 3 10 3 5 0 3 3 12 12 5 12 Write Cycle Time Address Set-Up to Write End Notes: 5. tr = < 3 ns for all speeds. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 9. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±200 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05458 Rev. *C Page 3 of 8 PRELIMINARY Switching Characteristics Over the Operating Range[6] 7C197D-10 Parameter tPWE tSD tHD tLZWE tHZWE Description WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[8,9] Min. 7 6 0 3 6 Max. 7C197D-12 Min. 8 8 0 3 7 Max. CY7C197D 7C197D-15 Min. 9 9 0 3 7 Max. Unit ns ns ns ns ns Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[4] tR[11] Description VCC for Data Retention Data Retention Current Non-L, Com’l / Ind’l L-Version Only Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Conditions Min. 2.0 3 1.2 0 tRC Max. Unit V mA mA ns ns Data Retention Waveform VCC 4.5V tCDR CE DATA RETENTION MODE VDR > 2V 4.5V tR Switching Waveforms Read Cycle No. 1[12, 13] tRC Address tAA t OHA Data Out Previous Data Valid Data Valid Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 12. WE is HIGH for read cycle. 13. Device is continuously selected, CE = VIL. Document #: 38-05458 Rev. *C Page 4 of 8 PRELIMINARY Switching Waveforms (continued) Read Cycle No. 2[12] t RC Address CY7C197D CE t ACE t LZ CE t HZCE High Z Data O ut tP U Data Valid tPD 50% 50% High Z I CC Vcc Supply Current I SB Write Cycle No. 1 (WE Controlled)[10] tW C Address t SC E CE t AW tSA WE t SD Data In t H ZW E Data O ut Data Undefined Data Valid tLZW E High Im pedance tH D t PW E tH A Document #: 38-05458 Rev. *C Page 5 of 8 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[10,14] tW C A ddress tS A CE tH A tP W E WE tS D D ata In D ata V alid H igh Z tH D tS C E CY7C197D tA W D ata O ut Truth Table CE H L L WE X H L High Z Data Out Data In Input/Output Deselect/Power-Down Read Write Mode Ordering Information Speed (ns) 10 Ordering Code CY7C197D-10PXC CY7C197D-10VXC CY7C197D-10PXI CY7C197D-10VXI 12 CY7C197D-12PXC CY7C197D-12VXC CY7C197D-12PXI CY7C197D-12VXI 15 CY7C197D-15PXC CY7C197D-15VXC CY7C197D-15PXI CY7C197D-15VXI Package Name P13 V13 P13 V13 P13 V13 P13 V13 P13 V13 P13 V13 Package Type 24-Lead (300-Mil) Molded DIP (Pb-Free) 24-Lead Molded SOJ (Pb-Free) 24-Lead (300-Mil) Molded DIP (Pb-Free) 24-Lead Molded SOJ (Pb-Free) 24-Lead (300-Mil) Molded DIP (Pb-Free) 24-Lead Molded SOJ (Pb-Free) 24-Lead (300-Mil) Molded DIP (Pb-Free) 24-Lead Molded SOJ (Pb-Free) 24-Lead (300-Mil) Molded DIP (Pb-Free) 24-Lead Molded SOJ (Pb-Free) 24-Lead (300-Mil) Molded DIP (Pb-Free) 24-Lead Molded SOJ (Pb-Free) Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Note: 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05458 Rev. *C Page 6 of 8 PRELIMINARY Package Diagram 24-Lead (300-Mil) PDIP P13 CY7C197D 51-85013-*B PIN 1 ID 24-lead (300-mil) SOJ V13 12 1 DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088 0.330[8.38] 0.350[8.89] MIN. MAX. 0.291[7.39] 0.300[7.62] PACKAGE WEIGHT 0.75gms PART # 13 24 V24.3 VZ24.3 STANDARD PKG. LEAD FREE PKG. 0.597[15.16] 0.613[15.57] SEATING PLANE 0.120[3.05] 0.140[3.55] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.013[0.33] 0.019[0.48] 0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91] 51-85030-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05458 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY7C197D 256K (256K x 1) Static RAM (Preliminary) Document Number: 38-05458 REV. ** *A *B ECN NO. 201560 233693 263769 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Datasheet for C9 IPP CY7C197D DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information 1) Reduced Speed bins to -10, -12 and -15 ns 2) Added ‘Industrial’ grade parts to the Ordering Info on Page #6 *C 307593 See ECN RKF Document #: 38-05458 Rev. *C Page 8 of 8