CY7C199-20PXC

CY7C199 32K x 8 Static RAM Features • High speed — 12 ns • Fast tDOE • CMOS for optimum speed/power • Low active power — 495 mW (Max, “L” version) • Low standby power — 0.275 mW (Max, “L” version) • 2V data retention (“L” version only) • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • Available in pb-free 28-pin TSOP I and 28-pin (300-Mil) Molded DIP Functional Description The CY7C199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199 is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity. Pin Configurations DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Logic Block Diagram I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE I/O1 ROW DECODER I/O2 SENSE AMPS 32K x 8 ARRAY I/O3 I/O4 I/O5 COLUMN DECODER POWER DOWN I/O6 I/O7 A 10 A 12 A 13 A 11 Selection Guide Maximum Access Time Maximum Operating Current L Maximum CMOS Standby Current L 10 –12 12 160 –15 15 155 90 10 0.05 –20 20 150 10 Unit ns mA mA A 14 OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) A0 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 14 A 13 A 12 Cypress Semiconductor Corporation Document #: 38-05160 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 CY7C199 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range [3] -12 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current Automatic CE Power-down Current— TTL Inputs Automatic CE Power-down Current— CMOS Inputs VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com’l L 30 Test Conditions VCC = Min., IOH=–4.0 mA VCC = Min., IOL=8.0 mA 2.2 –0.5 –5 –5 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 160 2.2 –0.5 –5 –5 Max. Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 155 90 30 5 10 10 0.05 10 30 2.2 –0.5 –5 –5 -15 Max. Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 150 -20 Max. Unit V V V V µA µA mA mA mA mA mA mA ISB1 Max. VCC, CE > VIH, Com’l VIN > VIH or L VIN < VIL, f = fMAX Max. VCC, Com’l CE > VCC – 0.3V L VIN > VCC – 0.3V or VIN < 0.3V, f = 0 ISB2 Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. Document #: 38-05160 Rev. *B Page 2 of 11 CY7C199 Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF AC Test Loads and Waveforms[5] R1 481 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 255 Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω 3.0V 10% GND ≤ tr R1 481 Ω ALL INPUT PULSES 90% 90% 10% ≤ tr (a) (b) THÉVENIN EQUIVALENT 167 Ω 1.73V OUTPUT Data Retention Characteristics Over the Operating Range (L-version only) Parameter VDR ICCDR tCDR[4] tR [5] Description VCC for Data Retention Data Retention Current Conditions[6] Min. 2.0 Max. Unit V VCC = VDR = 2.0V, CE > VCC – 0.3V, Chip Deselect to Data Retention Time V > V – 0.3V or V < 0.3V IN CC IN Operation Recovery Time 10 0 200 µA ns µs Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. tR< 3 ns for the -12 and the -15 speeds. tR< 5 ns for the -20 and slower speeds. 6. No input may exceed VCC + 0.5V. VDR > 2V 3.0V tR Document #: 38-05160 Rev. *B Page 3 of 11 CY7C199 Switching Characteristics Over the Operating Range [3,7] -12 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[10, 11] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[9] WE HIGH to Low-Z[8] 3 12 9 9 0 0 8 8 0 7 3 15 10 10 0 0 9 9 0 7 3 20 15 15 0 0 15 10 0 10 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z CE LOW to Low-Z CE HIGH to [8] -15 Max. Min. 15 12 15 3 12 5 15 7 0 5 7 3 5 7 0 12 15 0 3 0 3 Max. Min. 20 -20 Max. Unit ns 20 20 9 9 9 20 ns ns ns ns ns ns ns ns ns ns Description Min. 12 3 0 3 0 OE HIGH to High-Z[8, 9] [8] High-Z[8, 9] CE LOW to Power-up CE HIGH to Power-down Notes: 7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05160 Rev. *B Page 4 of 11 CY7C199 Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 [13, 14] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tRC tHZOE tHZCE DATA VALID tPD HIGH IMPEDANCE DATA OUT ICC 50% ISB Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05160 Rev. *B Page 5 of 11 CY7C199 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[10, 15, 16] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O tHZOE DATAIN VALID tHD Write Cycle No. 2 (CE Controlled)[10, 15, 16] tWC ADDRESS CE tSA tAW tHA tSCE WE tSD DATA I/O Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. tHD DATA IN VALID Document #: 38-05160 Rev. *B Page 6 of 11 CY7C199 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled OE LOW)[11, 16] tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O tHZWE DATAIN VALID tHD tLZWE Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC,I SB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25°C ICC NORMALIZED ICC,I SB 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 125 AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 NORMALIZED t AA 1.4 1.2 1.0 VCC =5.0V 0.8 0.6 –55 VCC =5.0V VIN =5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.3 NORMALIZED t AA 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25°C OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25°C 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT SINK CURRENT (mA) OUTPUT VOLTAGE (V) Document #: 38-05160 Rev. *B Page 7 of 11 CY7C199 Typical DC and AC Characteristics (continued) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO DELTA t AA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 NORMALIZED I CC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 0.50 10 20 30 40 VCC =4.5V TA =25°C TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 VCC =5.0V TA =25°C VIN =0.5V NORMALIZED I CC vs. CYCLE TIME 1.00 0.75 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 15 20 Ordering Code CY7C199-12ZXC CY7C199-15ZXC CY7C199L-15ZXC CY7C199-20PXC Package Diagram 51-85071 51-85071 51-85014 Package Type 28-pin TSOP I (Pb-free) 28-pin TSOP I (Pb-free) 28-pin (300-Mil) Molded DIP (Pb-free) Operating Range Commercial Commercial Commercial Document #: 38-05160 Rev. *B Page 8 of 11 CY7C199 Package Diagrams 28-pin (300-Mil) PDIP (51-85014) SEE LEAD END OPTION 14 1 DIMENSIONS IN INCHES [MM] MIN. MAX. 0.260[6.60] 0.295[7.49] REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 15 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 3° MIN. 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] 0.310[7.87] 0.385[9.78] SEE LEAD END OPTION LEAD END OPTION (LEAD #1, 14, 15 & 28) 51-85014-*D Document #: 38-05160 Rev. *B Page 9 of 11 CY7C199 Package Diagrams (continued) 28-pin TSOP Type 1 (8x13.4 mm) (51-85071) 51-85071-*G All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05160 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C199 Document History Page Document Title: CY7C199 32K x 8 Static RAM Document Number: 38-05160 REV. ** *A *B ECN NO. 109971 121730 492500 Issue Date 10/28/01 01/09/02 See ECN Orig. of Change SZV DFP NXR Description of Change Change from Spec number: 38-00239 to 38-05160 Updated Product Offering table Removed 8 ns, 10 ns, 25 ns , 35 ns, 45 ns speed bins Removed 28-Lead (300-Mil) CerDIP, 28-Pin Rectangular Leadless Chip Carrier, 28-Lead Molded SOIC, 28-Lead Molded SOJ packages from product offering Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics Table Updated Ordering Information Table Document #: 38-05160 Rev. *B Page 11 of 11