CY7C199C-20VC

CY7C199C 32K x 8 Static RAM Features • Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns • Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) • CMOS for optimum speed/power • TTL–compatible Inputs and Outputs • Available in 28 DIP, 28 SOJ, and 28 TSOP I. • 2.0V Data Retention • Low CMOS standby power • Automated Power–down when deselected General Description1 The CY7C199C is a high–performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power–down feature that significantly reduces power consumption when deselected. See the Truth Table in this datasheet for a complete description of read and write modes. The CY7C199C is available in 28 DIP, 28 SOJ, and 28 TSOP I package(s). Logic Block Diagram Input Buffer Row Decoder RAM Array Sense Amps I/Ox CE Column Decoder Power Down Circuit WE OE A X X Product Portfolio 12 ns Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current (low power) 12 85 500 15 ns 15 80 500 20 ns 20 75 500 25 ns 25 75 500 Unit ns mA uA Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05408 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 11, 2003 CY7C199C Pin Layout and Specifications 28 DIP (6.9 x 35.6 x 3.5 mm) – P21 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 TSOP I (8 x 13.4 x 1.2 mm) – Z28 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A14 A13 A12 Document #: 38-05408 Rev. *A Page 2 of 12 CY7C199C Pin Layout and Specifications (continued) 28 SOJ (8 x 18 x 3.5 mm) – V21 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 Pin Description Pin AX Type Input Address Inputs. Description DIP 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 TSOP I 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 28 27 18, 19, 20, 22, 23, 24, 25, 26 1 7 21 6 CE I/OX OE VCC VSS WE Control Input or Output Control Supply Supply Control Chip Enable. Data Input/Outputs. Output Enable. Power (5.0V). Ground. Write Enable. Truth Table CE H L L L OE X L X H WE X H L H I/Ox High Z Data Out Data In High Z Mode Deselect / Power-Down Read Write Selected, outputs disabled Power Standby (ISB) Active (ICC ) Active (ICC ) Active (ICC ) Document #: 38-05408 Rev. *A Page 3 of 12 CY7C199C Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Parameter TSTG TAMB VCC VIN, VOUT IOUT VESD ILU Storage Temperature Ambient Temperature with Power Applied (i.e. case temperature) Core Supply Voltage Relative to VSS DC Voltage Applied to any Pin Relative to VSS Output Short–Circuit Current Static Discharge Voltage (per MIL–STD–883, Method 3015) Latch–up Current Description Value –65 to +150 –55 to +125 –0.5 to +7.0 –0.5 to VCC + 0.5 20 > 2001 > 200 Unit °C °C V V mA V mA Operating Range Range Commercial Industrial Ambient Temperature (TA) 0°C to 70°C –40°C to 85°C Voltage Range (VCC) 5.0V ± 10% 5.0V ± 10% DC Electrical Characteristics Over the Operating Range (–12, –15)2 12 ns Parameter VIH VIL VOH VOL ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage VCC Operating Supply Current Automatic CE Power–down Current TTL Inputs Automatic CE Power–down Current CMOS Inputs Output Leakage Current Input Load Current VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA VCC = Max., IOUT = 0 mA, f = FMAX = 1/tRC Max. VCC, CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = FMAX Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 GND ≤ Vi ≤ VCC, Output Disabled GND ≤ Vi ≤ VCC Condition Power – – – – – – L – L – – Min. 2.2 –0.5 2.4 – – – – – – –5 –5 Max. VCC + 0.3 0.8 – 0.4 85 30 10 10 500 +5 +5 15 ns Min. 2.2 –0.5 2.4 – – – – – – –5 –5 Max. VCC + 0.3 0.8 – 0.4 80 30 10 10 500 +5 +5 Unit V V V V mA mA mA mA uA uA uA ISB2 IOZ IIX DC Electrical Characteristics Over the Operating Range (–20, –25)3 20 ns Parameter VIH Description Input HIGH Voltage Condition Power – Min 2.2 Max VCC + 0.3 0.8 – 0.4 25 ns Min 2.2 Max VCC + 0.3 0.8 – 0.4 Unit V VIL VOH VOL Input LOW Voltage Output HIGH Voltage Output LOW Voltage VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA – – – –0.5 2.4 – –0.5 2.4 – V V V Notes: 2. VIL (min) = –2.0V for pulse durations of less than 20 ns. 3.VIL (min) = –2.0V for pulse durations of less than 20 ns. Document #: 38-05408 Rev. *A Page 4 of 12 CY7C199C 20 ns Parameter ICC ISB1 Description VCC Operating Supply Current Automatic CE Power–down Current TTL Inputs Automatic CE Power–down Current CMOS Inputs Output Leakage Current Input Load Current Condition VCC = Max., IOUT = 0 mA, f = FMAX = 1/tRC Max. VCC, CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = FMAX Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 GND ≤ Vi ≤ VCC, Output Disabled GND ≤ Vi ≤ VCC Power – – L – L – – Min – – – – – –5 –5 Max 75 30 10 10 500 +5 +5 25 ns Min – – – – – –5 –5 Max 75 30 10 10 500 +5 +5 Unit mA mA mA mA uA uA uA ISB2 IOZ IIX Capacitance4 Max Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25C, f = 1 MHz, VCC = 5.0V ALL – PACKAGES 8 8 Unit pF AC Test Loads Output Loads R1 VCC VCC Output C1 R2 Output Loads for tHZOE, tHZCE & tHZWE R3 C2 R4 (A)* (B)* Thevenin Equivalent All Input Pulses VCC 90% 90% Output Rth VT VSS 10% 10% Rise Time 1 V/ns Fall Time 1 V/ns * including scope and jig capacitance Notes: 4. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05408 Rev. *A Page 5 of 12 CY7C199C AC Test Conditions Parameter Description Nom. Unit C1 C2 R1 R2 R3 R4 RTH VTH Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin 30 5 480 255 480 255 167 1.73 pF Ω V Thermal Resistance5 Parameter ΘJA ΘJC Description Conditions TSOP I SOJ DIP Unit Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Still Air, soldered on a 3 × 4.5 square inch, two–layer printed circuit board 88.6 79 TBD °C/W 21.94 41.42 TBD AC Electrical Characteristics6 7 8 12 ns Parameter Description Min Max 15 ns Min Max 20 ns Min Max 25 ns Min Max Unit tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid OE to Data Valid OE to Low Z OE to High Z CE to Low Z CE to High Z CE to Power–Up CE to Power–Down Write Cycle Time CE to Write End Address Set–Up to Write End Address Hold from Write End 12 – 3 – – 0 – 3 – 0 – 12 9 9 0 – 12 – 12 5 – 5 – 5 – 12 – – – – 15 – 3 – – 0 – 3 – 0 – 15 10 10 0 – 15 – 15 7 – 7 – 7 – 15 – – – – 20 – 3 – – 0 – 3 – 0 – 20 15 15 0 – 20 – 20 9 – 9 – 9 – 20 – – – – 25 – 3 – – 0 – 3 – 0 – 25 15 15 0 – 25 – 25 9 – 9 – 9 – 20 – – – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 5. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage. Document #: 38-05408 Rev. *A Page 6 of 12 CY7C199C 12 ns Parameter Description Min Max 15 ns Min Max 20 ns Min Max 25 ns Min Max Unit tSA tPWE tSD tHD tHZWE tLZWE Address Set–Up to Write Start WE Pulse Width Data Set–Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z 0 8 8 0 – 3 – – – – 7 – 0 9 9 0 – 3 – – – – 7 – 0 15 10 0 – 3 – – – – 10 – 0 15 10 0 – 3 – – – – 10 – ns ns ns ns ns ns Data Retention Characteristics9 ALL Parameter Description Condition Min Max Unit VDR ICCDR tCDR tR VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR=2.0V, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V 2.0 – 0 200 – 150 – – V uA ns us Timing Waveforms Data Retention Waveform VCC DATA RETENTION MODE tCDR CE tR Read Cycle No. 1 10 11 tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Notes: 9. L–version only. 10. Device is continuously selected. OE = VIL = CE. 11. WE is HIGH for Read Cycle. Document #: 38-05408 Rev. *A Page 7 of 12 CY7C199C Read Cycle No. 2 12 13 tRC Address CE tACE OE tDOE tLZOE High Z Data Out ICC ISB tLZCE tPU 50% Data Valid tPD 50% High Z tHZOE tHZCE VCC Current Write Cycle No. 1 (WE Controlled)14 15 16 tWC Address tSCE CE tAW tSA WE tPWE tHA OE tHZOE tSD tHD Data In/Out Undefined see footnotes Data-In Valid Notes: 12. This cycle is OE Controlled and WE is HIGH read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. This cycle is WE controlled, OE is HIGH during write. 15. Data In/Out is high impedance if OE = VIH. 16. During this period the I/Os are in output state and input signals should not be applied. Document #: 38-05408 Rev. *A Page 8 of 12 CY7C199C Write Cycle No. 2 (CE Controlled)17 18 19 tWC Address tSCE CE tSA tAW tHA WE tSD Data In/Out High Z Data-In Valid tHD High Z Write Cycle No. 3 (WE Controlled, OE Low)20 t WC Address tSCE CE tAW tSA WE tSD Data In/Out Undefined see footnotes tHA tPWE tHD Undefined See Footnotes Data-In Valid tHZWE tLZWE Notes: 17. This cycle is CE controlled. 18. Data In/Out is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high–impedance state. 20. The cycle is WE controlled, OE low. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 38-05408 Rev. *A Page 9 of 12 CY7C199C Ordering Information Speed Ordering Code Package Name Package Type Power Option Operating Range 12 ns 12 ns 12 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 20 ns 20 ns 25 ns CY7C199C–12VC CY7C199C–12ZC CY7C199C–12VI CY7C199C–15PC CY7C199C–15VC CY7C199C–15ZC CY7C199C–15VI CY7C199CL–15VC CY7C199CL–15ZC CY7C199CL–15VI CY7C199C–20VC CY7C199C–20ZI CY7C199C–25PC V21 Z28 V21 P21 V21 Z28 V21 V21 Z28 V21 V21 Z28 P21 28 SOJ (8 x 18 x 3.5 mm) 28 TSOP I (8 x 13.4 x 1.2 mm) 28 SOJ (8 x 18 x 3.5 mm) 28 DIP (6.9 x 35.6 x 3.5 mm) 28 SOJ (8 x 18 x 3.5 mm) 28 TSOP I (8 x 13.4 x 1.2 mm) 28 SOJ (8 x 18 x 3.5 mm) 28 SOJ (8 x 18 x 3.5 mm) 28 TSOP I (8 x 13.4 x 1.2 mm) 28 SOJ (8 x 18 x 3.5 mm) 28 SOJ (8 x 18 x 3.5 mm) 28 TSOP I (8 x 13.4 x 1.2 mm) 28 DIP (6.9 x 35.6 x 3.5 mm) Standard Standard Standard Standard Standard Standard Standard Low Power Low Power Low Power Standard Standard Standard Commercial Commercial Industrial Commercial Commercial Commercial Industrial Commercial Commercial Industrial Commercial Industrial Commercial Package Diagram 28 TSOP I (8 × 13.4 × 1.2 mm) – Z28 51-85071-*G Document #: 38-05408 Rev. *A Page 10 of 12 CY7C199C Package Diagram (continued) 28 SOJ (8 × 18 × 3.5 mm) – V21 51-85031-*B 28ÐLead(300ÐMil)Molded DIP P21 51Ð85014Ð*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05408 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C199C Document History Page Document Title: CY7C199C 32K x 8 Static RAM Document Number: 38-05408 REV. ECN No. Issue Date Orig. of Change Description of Change ** *A 129233 129697 09/11/03 09/15/03 HGK KKV New Data Sheet Minor change: Move Product Portfolio from page 4 to page 1 Move Truthtable from page 9 to page 3 Document #: 38-05408 Rev. *A Page 12 of 12