CY7C199CN-12ZXCT

CY7C199CN 256K (32K x 8) Static RAM General Description [1] Features • • • • • • • • Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) CMOS for optimum speed and power TTL-compatible inputs and outputs 2.0V data retention Low CMOS standby power Automated power down when deselected Available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP packages The CY7C199CN is a high performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power down feature that reduces power consumption when deselected. See the “Truth Table” on page 3 in this data sheet for a complete description of read and write modes. The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP package(s). Logic Block Diagram RAM Array Sense Amps Row Decoder Input Buffer I/Ox CE WE Power Down Circuit Column Decoder OE A X X Product Portfolio –12 –15 –20 –25 Unit Maximum Access Time 12 15 20 25 ns Maximum Operating Current 85 80 75 75 mA Maximum CMOS Standby Current (low power) 500 500 500 500 µA Note 1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 001-06435 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 08, 2007 CY7C199CN Pin Layout and Specifications 28 DIP 28 SOJ A5 1 28 VCC A5 1 28 VCC A6 2 27 WE A6 2 27 WE A4 A7 3 26 A4 A8 4 25 A3 24 A2 A7 A8 3 26 4 25 A3 A9 5 24 A9 A10 A2 5 6 23 A1 A10 6 23 A1 A11 7 22 OE A11 7 22 OE A12 8 21 A12 8 21 A0 A13 A0 9 20 CE A13 9 20 CE A14 10 19 A14 10 19 IO7 IO0 IO7 11 18 IO0 11 18 IO6 IO1 IO6 12 17 IO5 IO1 12 17 IO5 IO4 IO2 13 16 IO4 VSS 14 15 IO3 IO2 VSS 13 16 14 15 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 Document #: 001-06435 Rev. *B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IO3 28 TSOP I (8 x 13.4 mm) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 CE IO7 IO6 IO5 IO4 IO3 VSS IO2 IO1 IO0 A14 A13 A12 Page 2 of 14 CY7C199CN Pin Description Pin Type Description DIP SOJ TSOP I 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 28 20 20 27 11, 12, 13, 15, 16, 17, 18, 19 11, 12, 13, 15, 16, 17, 18, 19 18, 19, 20, 22, 23, 24, 25, 26 AX Input Address Inputs CE Control Chip Enable IOX Input or Output Data Input Outputs OE Control Output Enable 22 22 1 VCC Supply Power (5.0V) 28 28 7 VSS Supply Ground 14 14 21 WE Control Write Enable 27 27 6 Truth Table CE OE WE IOx Mode Power H X X High-Z Deselect/Power Down Stand by (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Parameter Description Value Unit TSTG Storage Temperature –65 to +150 °C TAMB Ambient Temperature with Power Applied (that is, case temperature) –55 to +125 °C VCC Core Supply Voltage Relative to VSS –0.5 to +7.0 V VIN, VOUT DC Voltage Applied to Any Pin Relative to VSS –0.5 to VCC + 0.5 V IOUT Output Short-Circuit Current 20 VESD Static Discharge Voltage (in accordance with MIL-STD-883, Method 3015) > 2001 V ILU Latch-up Current > 200 mA mA Operating Range Range Commercial Industrial Ambient Temperature (TA) Voltage Range (VCC) 0°C to 70°C 5.0V ± 10% –40°C to 85°C 5.0V ± 10% Automotive-A Document #: 001-06435 Rev. *B Page 3 of 14 CY7C199CN DC Electrical Characteristics Over the Operating Range (–12, –15) [2] Parameter Description Condition Power –12 –15 Min Max Min Max Unit VIH Input HIGH Voltage – 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input LOW Voltage – –0.5 0.8 –0.5 0.8 V VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA – 2.4 – 2.4 – V VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA – – 0.4 – 0.4 V ICC VCC Operating Supply Current – – 85 – 80 mA ISB1 Automatic CE Power Max VCC, CE ≥ VIH, Down Current TTL VIN ≥ VIH or VIN ≤ VIL, f = Fmax Inputs – – 30 – 30 mA L – 10 – 10 mA Automatic CE Power Max VCC, CE ≥ VCC – 0.3V, Down Current CMOS VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 Inputs – – 10 – 10 mA L – 500 – 500 µA ISB2 VCC = Max, IOUT = 0 mA, f = Fmax = 1/tRC IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled – –5 +5 –5 +5 µA IIX Input Leakage Current GND ≤ VI ≤ VCC – –5 +5 –5 +5 µA DC Electrical Characteristics Over the Operating Range (–20, –25) [2] Parameter Description Condition Power –20 –25 Min Max Min Max Unit VIH Input HIGH Voltage – 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input LOW Voltage – –0.5 0.8 –0.5 0.8 V VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA – 2.4 – 2.4 – V VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA – – 0.4 – 0.4 V ICC VCC Operating Supply Current – – 75 – 75 mA ISB1 Automatic CE Power Max VCC, CE ≥ VIH, Down Current TTL VIN ≥ VIH or VIN ≤ VIL, f = Fmax Inputs – – 30 – 30 mA L – 10 – 10 mA Automatic CE Power Max VCC, CE ≥ VCC – 0.3V, Down Current CMOS VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 Inputs – – 10 – 10 mA L – 500 – 500 µA ISB2 VCC = Max, IOUT = 0 mA, f = Fmax = 1/tRC IOZ Output Leakage Current GND ≤ Vi ≤ VCC, Output Disabled – –5 +5 –5 +5 µA IIX Input Leakage Current GND ≤ Vi ≤ VCC – –5 +5 –5 +5 µA Note 2. VIL (min) = –2.0V for pulse durations of less than 20 ns. Document #: 001-06435 Rev. *B Page 4 of 14 CY7C199CN Capacitance [3] Parameter Description Conditions CIN Input Capacitance COUT Output Capacitance Max Unit 8 pF TA = 25°C, f = 1 MHz, VCC = 5.0V 8 Thermal Resistance [3] Parameter Description ΘJA Thermal Resistance (junction to ambient) ΘJC Thermal Resistance (junction to case) Conditions TSOP I SOJ DIP Unit Still air, soldered on a 3 × 4.5 square inch, two–layer printed circuit board 88.6 79 69.33 °C/W 21.94 41.42 31.62 AC Test Loads O u tp u t L o a d s O u tp u t L o a d s fo r t H Z O E , t H Z C E & t H Z W E R1 R3 VC C VC C O u tp u t C1 R2 C2 (A )* (B )* T h e v e n in E q u iv a le n t O u tp u t R th R4 A ll In p u t P u ls e s VC C 90% VT 90% 10% VS S 10% R is e T im e 1 V /n s F a ll T im e 1 V /n s * in c lu d in g s c o p e a n d jig c a p a c ita n c e AC Test Conditions Parameter Description Nom Unit pF C1 Capacitor 1 30 C2 Capacitor 2 5 R1 Resistor 1 480 R2 Resistor 2 255 R3 Resistor 3 480 R4 Resistor 4 255 RTH Resistor Thevenin 167 VTH Voltage Thevenin 1.73 Ω V Note 3. Tested initially and after any design or process change that may affect these parameters. Document #: 001-06435 Rev. *B Page 5 of 14 CY7C199CN AC Electrical Characteristics [4] Parameter –12 Description –15 –20 –25 Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time 12 – 15 – 20 – 25 – ns tAA Address to Data Valid – 12 – 15 – 20 – 25 ns tOHA Data Hold from Address Change 3 – 3 – 3 – 3 – ns tACE CE to Data Valid – 12 – 15 – 20 – 25 ns tDOE OE to Data Valid Ind’l/Com’l – 5 – 7 – 9 – 9 ns – 6 – – – – – – tLZOE OE to Low-Z [5] 0 – 0 – 0 – 0 – ns tHZOE OE to High-Z [5, 6] – 5 – 7 – 9 – 9 ns tLZCE CE to Low-Z [5] 3 – 3 – 3 – 3 – ns tHZCE CE to High-Z [5, 6] – 5 – 7 – 9 – 9 ns tPU CE to Power Up 0 – 0 – 0 – 0 – ns tPD CE to Power Down – 12 – 15 – 20 – 20 ns tWC Write Cycle Time [7] 12 – 15 – 20 – 25 – ns tSCE CE to Write End 9 – 10 – 15 – 15 – ns tAW Address Setup to Write End 9 – 10 – 15 – 15 – ns tHA Address Hold from Write End 0 – 0 – 0 – 0 – ns tSA Address Setup to Write Start 0 – 0 – 0 – 0 – ns tPWE WE Pulse Width 8 – 9 – 15 – 15 – ns tSD Data Setup to Write End 8 – 9 – 10 – 10 – ns tHD Data Hold from Write End 0 – 0 – 0 – 0 – ns tHZWE WE LOW to High-Z [5, 6] – 7 – 7 – 10 – 10 ns tLZWE WE HIGH to Low-Z [5] 3 – 3 – 3 – 3 – ns Automotive-A Data Retention Characteristics [8] Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Condition VCC = VDR = 2.0V, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V Min Max Unit 2.0 – V – 150 µA 0 – ns 200 – µs Notes 4. Test Conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZCE, tHZWE are specified as in part (b) of the “” on page 1. Transitions are measured ± 200 mV from steady state voltage. 7. The internal memory write time is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 8. L-version only. Document #: 001-06435 Rev. *B Page 6 of 14 CY7C199CN Timing Waveforms Data Retention Waveform VCC DATA RETENTION MODE tCDR tR CE Read Cycle 1 [9, 10] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Read Cycle 2 [11, 12] tRC Address CE tHZCE tACE OE tDOE tHZOE tLZOE High Z Data Out VCC Current ICC ISB High Z Data Valid tLZCE tPU tPD 50% 50% Notes 9. Device is continuously selected. OE = VIL = CE. 10. WE is HIGH for read cycle. 11. This cycle is OE controlled and WE is HIGH read cycle. 12. Address valid before or similar with CE transition LOW. Document #: 001-06435 Rev. *B Page 7 of 14 CY7C199CN Timing Waveforms (continued) Write Cycle 1 (WE controlled) [13, 14, 15] tWC Address tSCE CE tAW tHA tPWE tSA WE OE tHZOE Data In/Out tSD Undefined tHD Data-In Valid see footnotes Write Cycle 2 (CE controlled) [14, 16, 17] tWC Address tSCE CE tSA tHA tAW WE tSD Data In/Out High Z Data-In Valid tHD High Z Notes 13. This cycle is WE controlled, OE is HIGH during write. 14. Data in and/or out is high impedance if OE = VIH. 15. During this period the IOs are in output state and input signals must not be applied. 16. This cycle is CE controlled. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06435 Rev. *B Page 8 of 14 CY7C199CN Timing Waveforms (continued) Write Cycle 3 (WE controlled, OE low) [18] t WC Address tSCE CE tAW tHA t PWE tSA WE tSD Data In Out Undefined tHD Undefined See Footnotes Data In Valid see footnotes t HZWE t LZWE Note 18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 001-06435 Rev. *B Page 9 of 14 CY7C199CN Ordering Information Contact local sales representative regarding availability of these parts. Speed (ns) 12 15 20 25 Ordering Code Package Diagram Package Type Power Option Operating Range CY7C199CN–12VC 51-85031 28-Lead (300-Mil) Molded SOJ Standard Commercial CY7C199CN–12ZC 51-85071 28 TSOP I (8 x 13.4 mm) Standard Commercial CY7C199CN–12ZXC 51-85071 28 TSOP I (8 x 13.4 mm), Pb-free Standard Commercial CY7C199CN–12VI 51-85031 28-Lead (300-Mil) Molded SOJ Standard Industrial CY7C199CN–12VXI 51-85031 28-Lead (300-Mil) Molded SOJ, Pb-free Standard Industrial CY7C199CN–12VXA 51-85031 28-Lead (300-Mil) Molded SOJ, Pb-free Standard Automotive-A CY7C199CN–15PC 51-85014 28 DIP (6.9 x 35.6 x 3.5 mm) Standard Commercial CY7C199CN–15PXC 51-85014 28 DIP (6.9 x 35.6 x 3.5 mm), Pb-free Standard Commercial CY7C199CN–15VC 51-85031 28-Lead (300-Mil) Molded SOJ Standard Commercial CY7C199CN–15VXC 51-85031 28-Lead (300-Mil) Molded SOJ, Pb-free Standard Commercial CY7C199CN–15ZC 51-85071 28 TSOP I (8 x 13.4 mm), Pb-free Standard Commercial CY7C199CN–15ZXC 51-85071 28 TSOP I (8 x 13.4 mm), Pb-free Standard Commercial CY7C199CN–15VI 51-85031 28-Lead (300-Mil) Molded SOJ Standard Industrial CY7C199CNL–15VC 51-85031 28-Lead (300-Mil) Molded SOJ Low Power Commercial CY7C199CNL–15VXC 51-85031 28-Lead (300-Mil) Molded SOJ, Pb-free Low Power Commercial CY7C199CNL–15ZXC 51-85071 28 TSOP I (8 x 13.4 mm), Pb-free Low Power Commercial CY7C199CNL–15VXI 51-85031 28-Lead (300-Mil) Molded SOJ, Pb-free Low Power Industrial CY7C199CN–20VC 51-85031 28-Lead (300-Mil) Molded SOJ Standard Commercial CY7C199CN–20ZI 51-85071 28 TSOP I (8 x 13.4 mm) Standard Industrial CY7C199CN–20ZXI 51-85071 28 TSOP I (8 x 13.4 mm), Pb-free Standard Industrial CY7C199CN–25PC 51-85014 28 DIP (6.9 x 35.6 x 3.5 mm) Standard Commercial CY7C199CN–25PXC 51-85014 28 DIP (6.9 x 35.6 x 3.5 mm), Pb-free Standard Commercial Document #: 001-06435 Rev. *B Page 10 of 14 CY7C199CN Package Diagrams Figure 1. 28-pin TSOP I (8 x 13.4 mm), 51-85071 51-85071-*G Document #: 001-06435 Rev. *B Page 11 of 14 CY7C199CN Package Diagrams (continued) Figure 2. 28-pin (300 Mil) Molded SOJ, 51-85031 NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 28 OPTION 1 0.697 0.713 A Document #: 001-06435 Rev. *B 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.019 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*C Page 12 of 14 CY7C199CN Package Diagrams (continued) Figure 3. 28-pin (300 Mil) PDIP, 51-85014 SEE LEAD END OPTION 14 1 DIMENSIONS IN INCHES [MM] MIN. MAX. REFERENCE JEDEC MO-095 0.260[6.60] 0.295[7.49] 15 PACKAGE WEIGHT: 2.15 gms 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] 0.009[0.23] 0.012[0.30] 0.055[1.39] 0.065[1.65] 3° MIN. 0.310[7.87] 0.385[9.78] 0.015[0.38] 0.020[0.50] SEE LEAD END OPTION LEAD END OPTION 51-85014-*D (LEAD #1, 14, 15 & 28) All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06435 Rev. *B Page 13 of 14 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C199CN Document History Page Document Title: CY7C199CN, 256K (32K x 8) Static RAM Document Number: 001-06435 REV. ECN No. Issue Date Orig. of Change ** 430363 See ECN NXR New Data Sheet *A 684342 See ECN VKN Added Automotive-A Information Updated Ordering Information Table *B 839904 See ECN VKN Added tDOE spec for Automotive-A part in AC Electrical characteristics table Document #: 001-06435 Rev. *B Description of Change Page 14 of 14