CY7C199CN

CY7C199CN 256 K (32 K × 8) Static RAM Features ■ ■ ■ ■ ■ ■ ■ ■ General Description [1] The CY7C199CN is a high performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power down feature that reduces power consumption when deselected. See the “Truth Table” on page 4 in this data sheet for a complete description of read and write modes. The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP package(s). Fast access time: 15 ns and 20 ns Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) CMOS for optimum speed and power TTL-compatible inputs and outputs 2.0 V data retention Low CMOS standby power Automated power down when deselected Available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP packages Logic Block Diagram Input Buffer Row Decoder RAM Array Sense Amps I/Ox CE Column Decoder Power Down Circuit WE OE A X X Product Portfolio –15 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current (low power) 15 80 500 –20 20 75 500 Unit ns mA μA Cypress Semiconductor Corporation Document #: 001-06435 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 17, 2011 [+] Feedback CY7C199CN Contents Pin Layout and Specifications ........................................ 3 Pin Description ................................................................. 4 Truth Table ........................................................................ 4 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Capacitance ........................................................................................ 5 Thermal Resistance ........................................................................ 5 DC Electrical Characteristics .......................................... 5 AC Test Loads .................................................................. 6 AC Test Conditions .......................................................... 6 AC Electrical Characteristics ..................................................... 7 Data Retention Characteristics ................................................. 7 Timing Waveforms ........................................................... 8 Data Retention Waveform ........................................... 8 Read Cycle 1 ............................................................... 8 Read Cycle 2 ............................................................... 9 Write Cycle 1 (WE controlled) ..............................................10 Write Cycle 2 (CE controlled) ...............................................11 Write Cycle 3 (WE controlled, OE low) .............................12 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Document #: 001-06435 Rev. *E Page 2 of 18 [+] Feedback CY7C199CN Pin Layout and Specifications 28 DIP A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 IO 0 IO 1 IO 2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE IO 7 IO 6 IO 5 IO 4 IO 3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 IO 0 IO 1 IO 2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 SOJ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE IO7 IO6 IO5 IO4 IO3 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 TSOP I (8 x 13.4 mm) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 CE IO7 IO6 IO5 IO4 IO3 VSS IO2 IO1 IO0 A14 A13 A12 Note 1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Document #: 001-06435 Rev. *E Page 3 of 18 [+] Feedback CY7C199CN Pin Description Pin AX CE IOX OE VCC VSS WE Input Control Input or Output Control Supply Supply Control Type Description Address Inputs Chip Enable Data Input Outputs Output Enable Power (5.0V) Ground Write Enable DIP 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 TSOP I 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 28 27 18, 19, 20, 22, 23, 24, 25, 26 1 7 21 6 Truth Table CE H L L L OE X L X H WE X H L H IOx High-Z Data Out Data In High-Z Mode Deselect/Power Down Read Write Selected, Outputs Disabled Power Stand by (ISB) Active (ICC) Active (ICC) Active (ICC) Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Parameter TSTG TAMB VCC VIN, VOUT IOUT VESD ILU Storage Temperature Ambient Temperature with Power Applied (that is, case temperature) Core Supply Voltage Relative to VSS DC Voltage Applied to Any Pin Relative to VSS Output Short-Circuit Current Static Discharge Voltage (in accordance with MIL-STD-883, Method 3015) Latch-up Current Description Value –65 to +150 –55 to +125 –0.5 to +7.0 –0.5 to VCC + 0.5 20 > 2001 > 200 Unit °C °C V V mA V mA Operating Range Range Commercial Industrial Ambient Temperature (TA) 0°C to 70°C –40°C to 85°C Voltage Range (VCC) 5.0 V ± 10% 5.0 V ± 10% Document #: 001-06435 Rev. *E Page 4 of 18 [+] Feedback CY7C199CN DC Electrical Characteristics Over the Operating Range (–15, –20) [2] –15 Parameter VIH VIL VOH VOL ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA Condition Min 2.2 –0.5 2.4 – – – – – – –5 –5 Max VCC + 0.3 0.8 – 0.4 80 30 10 10 500 +5 +5 Min 2.2 –0.5 2.4 – – – – – – –5 –5 Max VCC + 0.3 0.8 – 0.4 75 30 10 10 500 +5 +5 V V V V mA mA mA mA μA μA μA –20 Unit VCC Operating Supply VCC = Max, IOUT = 0 mA, Current f = Fmax = 1/tRC Automatic CE Power Down Current TTL Inputs Automatic CE Power Down Current CMOS Inputs Output Leakage Current Max VCC, CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = Fmax Max VCC, CE ≥ VCC – 0.3 V, VIN ≥ VCC – 0.3 V, or VIN ≤ 0.3 V, f = 0 GND ≤ VI ≤ VCC, Output Disabled ISB2 IOZ IIX Input Leakage Current GND ≤ VI ≤ VCC Capacitance [3] Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25°C, f = 1 MHz, VCC = 5.0 V Max 8 8 Unit pF Thermal Resistance [3] Parameter ΘJA ΘJC Description Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Conditions Still air, soldered on a 3 × 4.5 square inch, two–layer printed circuit board TSOP I 88.6 21.94 SOJ 79 41.42 DIP 69.33 31.62 Unit °C/W Note 2. VIL (min) = –2.0 V for pulse durations of less than 20 ns. Document #: 001-06435 Rev. *E Page 5 of 18 [+] Feedback CY7C199CN AC Test Loads O u tp u t L o a d s R1 VC C VC C O u tp u t C1 R2 O u tp u t L o a d s fo r t H Z O E , t H Z C E & t H Z W E R3 C2 R4 (A )* (B )* T h e v e n in E q u iv a le n t A ll In p u t P u ls e s VC C 90% 90% O u tp u t R th VT VS S 10% 10% R is e T im e 1 V /n s F a ll T im e 1 V /n s * in c lu d in g s c o p e a n d jig c a p a c ita n c e AC Test Conditions Parameter C1 C2 R1 R2 R3 R4 RTH VTH Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Description Nom 30 5 480 255 480 255 167 1.73 V Ω Unit pF Note 3. Tested initially and after any design or process change that may affect these parameters. Document #: 001-06435 Rev. *E Page 6 of 18 [+] Feedback CY7C199CN AC Electrical Characteristics [4] –15 Parameter tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Min Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid OE to Data Valid OE to Low-Z [5] –20 Unit Max – 15 – 15 7 – 7 – 7 – 15 – – – – – – – – 7 – Min 20 – 3 – – 0 – 3 – 0 – 20 15 15 0 0 15 10 0 – 3 Max – 20 – 20 9 – 9 – 9 – 20 – – – – – – – – 10 – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 – 3 – – 0 – 3 – 0 – 15 10 10 0 0 9 9 0 – 3 OE to High-Z [5, 6] CE to Low-Z CE to High-Z [5] [5, 6] CE to Power Up CE to Power Down Write Cycle Time CE to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z WE HIGH to Low-Z [5, 6] [5] [7] Data Retention Characteristics [8] Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0 V, CE ≥ VCC – 0.3 V, VIN ≥ VCC – 0.3 V or VIN ≤ 0.3 V Condition Min 2.0 – 0 200 Max – 150 – – Unit V μA ns μs Notes 4. Test Conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZCE, tHZWE are specified as in part (b) of the “” on page 5. Transitions are measured ± 200 mV from steady state voltage. 7. The internal memory write time is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 8. L-version only. Document #: 001-06435 Rev. *E Page 7 of 18 [+] Feedback CY7C199CN Timing Waveforms Data Retention Waveform VCC DATA RETENTION MODE tCDR CE tR Read Cycle 1 [9, 10] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Document #: 001-06435 Rev. *E Page 8 of 18 [+] Feedback CY7C199CN Timing Waveforms Read Cycle 2 [11, 12] (continued) tRC Address CE tACE OE tDOE tLZOE High Z Data Out ICC ISB tLZCE tPU 50% Data Valid tPD 50% High Z tHZOE tHZCE VCC Current Notes 9. Device is continuously selected. OE = VIL = CE. 10. WE is HIGH for read cycle. 11. This cycle is OE controlled and WE is HIGH read cycle. 12. Address valid before or similar with CE transition LOW. Document #: 001-06435 Rev. *E Page 9 of 18 [+] Feedback CY7C199CN Timing Waveforms (continued) Write Cycle 1 (WE controlled) [13, 14, 15] tWC Address tSCE CE tAW tSA WE tPWE tHA OE tHZOE tSD tHD Data In/Out Undefined see footnotes Data-In Valid Document #: 001-06435 Rev. *E Page 10 of 18 [+] Feedback CY7C199CN Timing Waveforms (continued) Write Cycle 2 (CE controlled) [14, 16, 17] tWC Address tSCE CE tSA tAW tHA WE tSD Data In/Out High Z Data-In Valid tHD High Z Notes 13. This cycle is WE controlled, OE is HIGH during write. 14. Data in and/or out is high impedance if OE = VIH. 15. During this period the IOs are in output state and input signals must not be applied. 16. This cycle is CE controlled. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06435 Rev. *E Page 11 of 18 [+] Feedback CY7C199CN Timing Waveforms (continued) Write Cycle 3 (WE controlled, OE low) [18] t WC Address tSCE CE tAW tSA WE tSD Data In Out see footnotes tHA t PWE tHD Undefined See Footnotes Undefined t HZWE Data In Valid t LZWE Note 18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 001-06435 Rev. *E Page 12 of 18 [+] Feedback CY7C199CN Ordering Information Contact local sales representative regarding availability of these parts. Speed (ns) 15 Ordering Code CY7C199CN-15PXC CY7C199CN-15VXC CY7C199CNL-15VXI 20 CY7C199CN-20ZXI Package Diagram 51-85014 51-85031 51-85031 51-85071 Package Type 28 DIP (6.9 x 35.6 x 3.5 mm), Pb-free 28-Pin (300-Mil) Molded SOJ, Pb-free 28-Pin (300-Mil) Molded SOJ, Pb-free 28 TSOP I (8 x 13.4 mm), Pb-free Power Option Standard Standard Low Power Standard Operating Range Commercial Commercial Industrial Industrial Ordering Code Definitions CY 7 C 1 99 CN L - XX XX X Temperature Range: X = C or I C = Commercial; I = Industrial Package Type: XX = VX or PX or ZX VX = 28-lead Molded SOJ (Pb-free) PX = 28-lead DIP (Pb-free) ZX = 28-lead TSOP I (Pb-free) Speed: XX = 15 ns or 20 ns L = low power CN = 0.25 µm Technology 99 = 256 K bit density with datawidth × 8 bits 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 001-06435 Rev. *E Page 13 of 18 [+] Feedback CY7C199CN Package Diagrams Figure 1. 28-pin TSOP I (8 x 13.4 mm), 51-85071 51-85071 *I Document #: 001-06435 Rev. *E Page 14 of 18 [+] Feedback CY7C199CN Package Diagrams (continued) Figure 2. 28-pin (300 Mil) Molded SOJ, 51-85031 51-85031 *D Document #: 001-06435 Rev. *E Page 15 of 18 [+] Feedback CY7C199CN Package Diagrams (continued) Figure 3. 28-pin (300 Mil) PDIP, 51-85014 51-85014 *E Document #: 001-06435 Rev. *E Page 16 of 18 [+] Feedback CY7C199CN Acronyms Acronym CE CMOS I/O OE SRAM SOJ TSOP VFBGA chip enable Complementary metal oxide semiconductor Input/output output enable Static random access memory Small Outline J-Lead Thin Small Outline Package Very Fine-Pitch Ball Grid Array Description Document Conventions Units of Measure Symbol ns V µA mA mV mW MHz pF °C W nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts Unit of Measure Document #: 001-06435 Rev. *E Page 17 of 18 [+] Feedback CY7C199CN Document History Page Document Title: CY7C199CN, 256 K (32 K × 8) Static RAM Document Number: 001-06435 Revision ** *A *B *C *D *E ECN. 430363 684342 839904 2896044 3108898 3198636 Submission Date See ECN See ECN See ECN 03/19/2010 12/13/2010 03/17/11 Orig. of Change NXR VKN VKN NXR PRAS PRAS New Data Sheet Added Automotive-A Information Updated Ordering Information Table Added tDOE spec for Automotive-A part in AC Electrical characteristics table Updated Ordering Information Table Updated Package Diagram Added Ordering Code Definitions. Dislodged Automotive device information to 001-67737 Updated template and styles. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. 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Document #: 001-06435 Rev. *E Revised March 17, 2011 Page 18 of 18 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback