CY7C199CN_09

CY7C199CN 256K (32K x 8) Static RAM Features • • • • • • • • Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) CMOS for optimum speed and power TTL-compatible inputs and outputs 2.0V data retention Low CMOS standby power Automated power down when deselected Available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP packages General Description [1] The CY7C199CN is a high performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power down feature that reduces power consumption when deselected. See the “Truth Table” on page 3 in this data sheet for a complete description of read and write modes. The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP package(s). Logic Block Diagram Input Buffer Row Decoder RAM Array Sense Amps I/Ox CE Column Decoder Power Down Circuit WE OE X A X Product Portfolio –12 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current (low power) 12 85 500 –15 15 80 500 –20 20 75 500 –25 25 75 500 Unit ns mA µA Note 1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 001-06435 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 08, 2007 CY7C199CN Pin Layout and Specifications 28 DIP A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 IO 0 IO 1 IO 2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE IO 7 IO 6 IO 5 IO 4 IO 3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 IO 0 IO 1 IO 2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 SOJ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE IO7 IO6 IO5 IO4 IO3 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 TSOP I (8 x 13.4 mm) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 CE IO 7 IO 6 IO 5 IO 4 IO 3 VSS IO 2 IO 1 IO 0 A14 A13 A12 Document #: 001-06435 Rev. *B Page 2 of 14 CY7C199CN Pin Description Pin AX CE IOX OE VCC VSS WE Input Control Input or Output Control Supply Supply Control Type Description Address Inputs Chip Enable Data Input Outputs Output Enable Power (5.0V) Ground Write Enable DIP 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 TSOP I 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 28 27 18, 19, 20, 22, 23, 24, 25, 26 1 7 21 6 Truth Table CE H L L L OE X L X H WE X H L H IOx High-Z Data Out Data In High-Z Mode Deselect/Power Down Read Write Selected, Outputs Disabled Power Stand by (ISB) Active (ICC) Active (ICC) Active (ICC) Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Parameter TSTG TAMB VCC VIN, VOUT IOUT VESD ILU Storage Temperature Ambient Temperature with Power Applied (that is, case temperature) Core Supply Voltage Relative to VSS DC Voltage Applied to Any Pin Relative to VSS Output Short-Circuit Current Static Discharge Voltage (in accordance with MIL-STD-883, Method 3015) Latch-up Current Description Value –65 to +150 –55 to +125 –0.5 to +7.0 –0.5 to VCC + 0.5 20 > 2001 > 200 Unit °C °C V V mA V mA Operating Range Range Commercial Industrial Automotive-A Ambient Temperature (TA) 0°C to 70°C –40°C to 85°C Voltage Range (VCC) 5.0V ± 10% 5.0V ± 10% Document #: 001-06435 Rev. *B Page 3 of 14 CY7C199CN DC Electrical Characteristics Over the Operating Range (–12, –15) [2] Parameter VIH VIL VOH VOL ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC = Min, IOH = –4.0 mA Output LOW Voltage VCC = Min, IOL = 8.0 mA VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = Fmax = 1/tRC Condition Power – – – – – – L – L – – –12 Min 2.2 –0.5 2.4 – – – – – – –5 –5 Max VCC + 0.3 0.8 – 0.4 85 30 10 10 500 +5 +5 Min 2.2 –0.5 2.4 – – – – – – –5 –5 –15 Max VCC + 0.3 0.8 – 0.4 80 30 10 10 500 +5 +5 Unit V V V V mA mA mA mA µA µA µA Automatic CE Power Max VCC, CE ≥ VIH, Down Current TTL VIN ≥ VIH or VIN ≤ VIL, f = Fmax Inputs Automatic CE Power Max VCC, CE ≥ VCC – 0.3V, Down Current CMOS VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 Inputs Output Leakage Current Input Leakage Current GND ≤ VI ≤ VCC, Output Disabled GND ≤ VI ≤ VCC ISB2 IOZ IIX DC Electrical Characteristics Over the Operating Range (–20, –25) [2] Parameter VIH VIL VOH VOL ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC = Min, IOH = –4.0 mA Output LOW Voltage VCC = Min, IOL = 8.0 mA VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = Fmax = 1/tRC Condition Power – – – – – – L – L – – –20 Min 2.2 –0.5 2.4 – – – – – – –5 –5 Max VCC + 0.3 0.8 – 0.4 75 30 10 10 500 +5 +5 Min 2.2 –0.5 2.4 – – – – – – –5 –5 –25 Max VCC + 0.3 0.8 – 0.4 75 30 10 10 500 +5 +5 Unit V V V V mA mA mA mA µA µA µA Automatic CE Power Max VCC, CE ≥ VIH, Down Current TTL VIN ≥ VIH or VIN ≤ VIL, f = Fmax Inputs Automatic CE Power Max VCC, CE ≥ VCC – 0.3V, Down Current CMOS VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 Inputs Output Leakage Current Input Leakage Current GND ≤ Vi ≤ VCC, Output Disabled GND ≤ Vi ≤ VCC ISB2 IOZ IIX Note 2. VIL (min) = –2.0V for pulse durations of less than 20 ns. Document #: 001-06435 Rev. *B Page 4 of 14 CY7C199CN Capacitance [3] Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 8 8 Unit pF Thermal Resistance [3] Parameter ΘJA ΘJC Description Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Conditions Still air, soldered on a 3 × 4.5 square inch, two–layer printed circuit board TSOP I 88.6 21.94 SOJ 79 41.42 DIP 69.33 31.62 Unit °C/W AC Test Loads O u tp u t L o a d s R1 VC C VC C O u tp u t C1 R2 O u tp u t L o a d s fo r t H Z O E , t H Z C E & t H Z W E R3 C2 R4 (A )* (B )* A ll In p u t P u ls e s 90% 90% T h e v e n in E q u iv a le n t VC C O u tp u t R th VT VS S 10% 10% R is e T im e 1 V /n s F a ll T im e 1 V /n s * in c lu d in g s c o p e a n d jig c a p a c ita n c e AC Test Conditions Parameter C1 C2 R1 R2 R3 R4 RTH VTH Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Description Nom 30 5 480 255 480 255 167 1.73 V Ω Unit pF Note 3. Tested initially and after any design or process change that may affect these parameters. Document #: 001-06435 Rev. *B Page 5 of 14 CY7C199CN AC Electrical Characteristics [4] Parameter tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid OE to Data Valid Ind’l/Com’l Automotive-A OE to Low-Z OE to High-Z [5] [5, 6] –12 Min 12 – 3 – – – 0 – 3 – 0 – 12 9 9 0 0 8 8 0 – 3 Max – 12 – 12 5 6 – 5 – 5 – 12 – – – – – – – – 7 – Min 15 – 3 – – – 0 – 3 – 0 – 15 10 10 0 0 9 9 0 – 3 –15 Max – 15 – 15 7 – – 7 – 7 – 15 – – – – – – – – 7 – Min 20 – 3 – – – 0 – 3 – 0 – 20 15 15 0 0 15 10 0 – 3 –20 Max – 20 – 20 9 – – 9 – 9 – 20 – – – – – – – – 10 – Min 25 – 3 – – – 0 – 3 – 0 – 25 15 15 0 0 15 10 0 – 3 –25 Max – 25 – 25 9 – – 9 – 9 – 20 – – – – – – – – 10 – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE to Low-Z [5] CE to High-Z [5, 6] CE to Power Up CE to Power Down Write Cycle Time [7] CE to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z [5, 6] WE HIGH to Low-Z [5] Data Retention Characteristics [8] Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V Condition Min 2.0 – 0 200 Max – 150 – – Unit V µA ns µs Notes 4. Test Conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZCE, tHZWE are specified as in part (b) of the “” on page 1. Transitions are measured ± 200 mV from steady state voltage. 7. The internal memory write time is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 8. L-version only. Document #: 001-06435 Rev. *B Page 6 of 14 CY7C199CN Timing Waveforms Data Retention Waveform VCC DATA RETENTION MODE tCDR CE tR Read Cycle 1 [9, 10] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Read Cycle 2 [11, 12] tRC Address CE tACE OE tDOE tLZOE Data Out ICC ISB High Z tLZCE tPU 50% Data Valid tPD 50% High Z tHZOE tHZCE VCC Current Notes 9. Device is continuously selected. OE = VIL = CE. 10. WE is HIGH for read cycle. 11. This cycle is OE controlled and WE is HIGH read cycle. 12. Address valid before or similar with CE transition LOW. Document #: 001-06435 Rev. *B Page 7 of 14 CY7C199CN Timing Waveforms (continued) Write Cycle 1 (WE controlled) [13, 14, 15] tWC Address tSCE CE tAW tSA WE tPWE tHA OE tHZOE tSD tHD Data In/Out Undefined see footnotes Data-In Valid Write Cycle 2 (CE controlled) [14, 16, 17] tWC Address tSCE CE tSA tHA tAW WE tSD Data In/Out High Z Data-In Valid tHD High Z Notes 13. This cycle is WE controlled, OE is HIGH during write. 14. Data in and/or out is high impedance if OE = VIH. 15. During this period the IOs are in output state and input signals must not be applied. 16. This cycle is CE controlled. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06435 Rev. *B Page 8 of 14 CY7C199CN Timing Waveforms (continued) Write Cycle 3 (WE controlled, OE low) [18] t WC Address tSCE CE tAW tSA WE tSD Data In Out see footnotes tHA t PWE tHD Undefined See Footnotes Undefined t HZWE Data In Valid t LZWE Note 18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 001-06435 Rev. *B Page 9 of 14 CY7C199CN Ordering Information Contact local sales representative regarding availability of these parts. Speed (ns) 12 Ordering Code CY7C199CN–12VC CY7C199CN–12ZC CY7C199CN–12ZXC CY7C199CN–12VI CY7C199CN–12VXI CY7C199CN–12VXA 15 CY7C199CN–15PC CY7C199CN–15PXC CY7C199CN–15VC CY7C199CN–15VXC CY7C199CN–15ZC CY7C199CN–15ZXC CY7C199CN–15VI CY7C199CNL–15VC CY7C199CNL–15VXC CY7C199CNL–15ZXC CY7C199CNL–15VXI 20 CY7C199CN–20VC CY7C199CN–20ZI CY7C199CN–20ZXI 25 CY7C199CN–25PC CY7C199CN–25PXC Package Diagram 51-85031 51-85071 51-85071 51-85031 51-85031 51-85031 51-85014 51-85014 51-85031 51-85031 51-85071 51-85071 51-85031 51-85031 51-85031 51-85071 51-85031 51-85031 51-85071 51-85071 51-85014 51-85014 Package Type 28-Lead (300-Mil) Molded SOJ 28 TSOP I (8 x 13.4 mm) 28 TSOP I (8 x 13.4 mm), Pb-free 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ, Pb-free 28-Lead (300-Mil) Molded SOJ, Pb-free 28 DIP (6.9 x 35.6 x 3.5 mm) 28 DIP (6.9 x 35.6 x 3.5 mm), Pb-free 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ, Pb-free 28 TSOP I (8 x 13.4 mm), Pb-free 28 TSOP I (8 x 13.4 mm), Pb-free 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ, Pb-free 28 TSOP I (8 x 13.4 mm), Pb-free 28-Lead (300-Mil) Molded SOJ, Pb-free 28-Lead (300-Mil) Molded SOJ 28 TSOP I (8 x 13.4 mm) 28 TSOP I (8 x 13.4 mm), Pb-free 28 DIP (6.9 x 35.6 x 3.5 mm) 28 DIP (6.9 x 35.6 x 3.5 mm), Pb-free Power Option Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Operating Range Commercial Commercial Commercial Industrial Industrial Automotive-A Commercial Commercial Commercial Commercial Commercial Commercial Industrial Low Power Commercial Low Power Commercial Low Power Commercial Low Power Industrial Standard Standard Standard Standard Standard Commercial Industrial Industrial Commercial Commercial Document #: 001-06435 Rev. *B Page 10 of 14 CY7C199CN Package Diagrams Figure 1. 28-pin TSOP I (8 x 13.4 mm), 51-85071 51-85071-*G Document #: 001-06435 Rev. *B Page 11 of 14 CY7C199CN Package Diagrams (continued) Figure 2. 28-pin (300 Mil) Molded SOJ, 51-85031 NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID 14 1 DETAIL A EXTERNAL LEAD DESIGN 0.291 0.300 0.330 0.350 0.013 0.019 OPTION 1 OPTION 2 0.026 0.032 0.014 0.020 15 28 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE 0.007 0.013 0.004 A 0.025 MIN. 0.262 0.272 51-85031-*C Document #: 001-06435 Rev. *B Page 12 of 14 CY7C199CN Package Diagrams (continued) Figure 3. 28-pin (300 Mil) PDIP, 51-85014 SEE LEAD END OPTION 14 1 DIMENSIONS IN INCHES [MM] MIN. MAX. 0.260[6.60] 0.295[7.49] REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 15 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 3° MIN. 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] 0.310[7.87] 0.385[9.78] SEE LEAD END OPTION LEAD END OPTION (LEAD #1, 14, 15 & 28) 51-85014-*D All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06435 Rev. *B Page 13 of 14 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C199CN Document History Page Document Title: CY7C199CN, 256K (32K x 8) Static RAM Document Number: 001-06435 REV. ** *A *B ECN No. 430363 684342 839904 Issue Date See ECN See ECN See ECN Orig. of Change NXR VKN VKN New Data Sheet Added Automotive-A Information Updated Ordering Information Table Added tDOE spec for Automotive-A part in AC Electrical characteristics table Description of Change Document #: 001-06435 Rev. *B Page 14 of 14