CY7C199D-10VXI

CY7C199D 256K (32K x 8) Static RAM Features ■ Functional Description The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE) and tri-state drivers. This device has an automatic power down feature, reducing the power consumption when deselected. The input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A14). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Temperature ranges ❐ Industrial: –40°C to 85°C ❐ Automotive-E: –40°C to 125°C Pin and function compatible with CY7C199C High speed ❐ tAA ■ ■ = 10 ns (Industrial) = 80 mA at 10 ns = 3 mA ■ Low active power ❐ ICC ■ Low CMOS standby power ❐ ISB2 ■ ■ ■ ■ ■ ■ 2.0V Data Retention Automatic power down when deselected CMOS for optimum speed/power TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 28-pin 300-Mil wide Molded SOJ, 28-pin 300-Mil wide SOIC and 28-pin TSOP I packages Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE IO0 IO1 ROW DECODER 32K x 8 ARRAY SENSE AMPS IO2 IO3 IO4 IO5 IO6 COLUMN DECODER POWER DOWN IO7 A10 A12 A13 A11 A14 Cypress Semiconductor Corporation Document #: 38-05471 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 28, 2009 [+] Feedback CY7C199D Pin Configuration Figure 1. 28-Pin SOJ (Top View) Figure 2. 28-Pin SOIC (Top View) Figure 3. 28-Pin TSOP I (Top View) A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 IO0 IO1 IO2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE IO7 IO6 IO5 IO4 IO3 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE IO7 IO6 IO5 IO4 IO3 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A14 A13 A12 Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 (Industrial) 10 80 3 -25 (Automotive) [1] 25 63 15 Unit ns mA mA Note: 1. Automotive product information is preliminary Document #: 38-05471 Rev. *E Page 2 of 12 [+] Feedback CY7C199D Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VCC to Relative GND [2] ....–0.5V to +6.0V DC Voltage Applied to Outputs in High Z State [2] ................................... –0.5V to VCC + 0.5V DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage......................................... > 2,001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Industrial Automotive-E Ambient Temperature –40°C to +85°C –40°C to +125°C VCC 5V ± 0.5V 5V ± 0.5V Speed 10 ns 25 ns Electrical Characteristics Over the Operating Range 7C199D-10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage [2] Input LOW Voltage [2] 7C199D-25 Unit Min 2.4 Max V 0.4 2.2 –0.5 –5 –5 VCC + 0.5 0.8 +5 +5 – – – 63 50 V V V μA μA mA mA mA mA mA Test Conditions Min IOH=–4.0 mA IOL=8.0 mA 2.2 –0.5 GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz –1 –1 2.4 0.4 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 Max Input Leakage Current Output Leakage Current VCC Operating Supply Current ISB1 Automatic CE Power down Current— TTL Inputs Automatic CE Power down Current— CMOS Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax Max VCC, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f=0 ISB2 3 15 mA Note: 2. VIL(min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05471 Rev. *E Page 3 of 12 [+] Feedback CY7C199D Capacitance [3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 8 8 Unit pF pF Thermal Resistance [3] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ 59.16 40.84 TSOP I 54.65 21.49 SOIC TBD TBD Unit °C/W °C/W AC Test Loads and Waveforms [4] Z = 50Ω OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Rise Time: ≤ 3 ns Fall Time: ≤ 3 ns ALL INPUT PULSES 3.0V 30pF* 10% GND 90% 90% 10% (a) High Z characteristics: 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω (b) R1 480Ω (c) Notes: 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure (a). High Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05471 Rev. *E Page 4 of 12 [+] Feedback CY7C199D Switching Characteristics (Over the Operating Range) [5] 7C199D-10 Parameter Read Cycle tpower [6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE [7] [7, 8] 7C199D-25 Unit Min Max Description Min Max VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power up CE HIGH to Power down [10, 11] 100 10 10 3 10 5 0 5 3 5 0 10 100 25 25 3 25 10 0 11 3 11 0 25 μs ns ns ns ns ns ns ns ns ns ns ns [7] tHZCE [7, 8] tPU tPD [9] [9] Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE [7] tLZWE [7, 8] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z 10 7 7 0 0 7 6 0 5 3 25 18 18 0 0 18 12 0 11 3 ns ns ns ns ns ns ns ns ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of “AC Test Loads and Waveforms [4]” on page 4. Transition is measured ±200 mV from steady-state voltage. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05471 Rev. *E Page 5 of 12 [+] Feedback CY7C199D Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [3] tR [12] Description VCC for Data Retention Data Retention Current Conditions Min 2.0 Max Unit V VCC = VDR = 2.0V, CE > VCC – 0.3V, Industrial VIN > VCC – 0.3V or VIN < 0.3V Automotive-E 0 tRC 3 15 mA mA ns ns Chip Deselect to Data Retention Time Operation Recovery Time Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR CE VDR > 2V 4.5V tR Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [14, 15] tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB tHZOE tHZCE DATA VALID HIGH IMPEDANCE DATA OUT Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05471 Rev. *E Page 6 of 12 [+] Feedback CY7C199D Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [10, 16, 17] tWC ADDRESS CE tSA tAW tHA tSCE WE tSD DATA IO DATA IN VALID tHD Write Cycle No. 2 (WE Controlled) [10, 16, 17] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA IO NOTE 18 tHZOE DATAIN VALID tHD Write Cycle No. 3 (WE Controlled, OE LOW) [11, 17] tWC ADDRESS CE tAW tSA WE tHA tSD DATA IO NOTE 18 tHZWE Notes: 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period the IOs are in the output state and input signals should not be applied. tHD DATAIN VALID tLZWE Document #: 38-05471 Rev. *E Page 7 of 12 [+] Feedback CY7C199D Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output disabled Mode Deselect/Power down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 25 Ordering Code CY7C199D-10VXI CY7C199D-10ZXI CY7C199D-25SXE Package Diagram 51-85031 51-85071 51-85026 Package Type 28-pin (300-Mil) Molded SOJ (Pb-Free) 28-pin TSOP Type I (Pb-free) 28-pin (300-Mil) SOIC (Pb-Free) Automotive-E Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 4. 28-Pin (300-Mil) Molded SOJ NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID 14 1 DETAIL A EXTERNAL LEAD DESIGN 0.291 0.300 0.330 0.350 0.013 0.019 OPTION 1 OPTION 2 0.026 0.032 0.014 0.020 15 28 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE 0.007 0.013 0.004 A 0.025 MIN. 0.262 0.272 51-85031-*C Document #: 38-05471 Rev. *E Page 8 of 12 [+] Feedback CY7C199D Package Diagrams (continued) Figure 5. 28-Pin (300-Mil) SOIC NOTE : PIN 1 ID 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. 14 1 0.291[7.39] 0.300[7.62] 4. PACKAGE WEIGHT 0.85gms * 0.394[10.01] 0.419[10.64] 15 28 0.026[0.66] 0.032[0.81] PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.697[17.70] 0.713[18.11] SEATING PLANE 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.013[0.33] 0.050[1.27] TYP. 0.019[0.48] 0.004[0.10] 0.0118[0.30] * 0.015[0.38] 0.050[1.27] 0.0091[0.23] 0.0125[3.17] * 51-85026-*D Document #: 38-05471 Rev. *E Page 9 of 12 [+] Feedback CY7C199D Package Diagrams (continued) Figure 6. 28-Pin Thin Small Outline Package Type 1 (8x13.4 mm) 51-85071-*G Document #: 38-05471 Rev. *E Page 10 of 12 [+] Feedback CY7C199D Document History Page Document Title: CY7C199D 256K (32K x 8) Static RAM Document Number: 38-05471 Revision ** *A *B ECN 201560 233728 262950 Orig. of Change SWI RKF RKF Submission Date See ECN See ECN See ECN Description of Change Advance Information datasheet for C9 IPP DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information Reduced Speed bins to -10, -12 and -15 ns Converted from Preliminary to Final Removed 12 ns and 15 ns speed bin Removed Commercial Operating range Removed “L” part Removed 28-pin PDIP and 28-pin SOIC package Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins Updated Thermal Resistance table Updated Ordering Information Table Included 28-Pin SOIC package Changed VIH level from 2.0V to 2.2V For Industrial grade, changed tSD from 5 ns to 6 ns, and tHZWE from 6 ns to 5 ns Included Automotive-E information *C *D 307594 820660 RKF VKN See ECN See ECN *E 2745093 VKN See ECN Document #: 38-05471 Rev. *E Page 11 of 12 [+] Feedback CY7C199D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com © Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. 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Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05471 Rev. *E Revised July 28, 2009 Page 12 of 12 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback