CY7C199D_11

CY7C199D 256 K (32 K × 8) Static RAM 256 K (32 K × 8) Static RAM Features ■ Functional Description The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8-bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption when deselected. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). Write to the device by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A14). Read from the device by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the I/O pins. Temperature ranges ❐ –40 °C to 85 °C Pin and function compatible with CY7C199C High speed ❐ tAA ■ ■ = 10 ns = 80 mA at 10 ns = 3 mA ■ Low active power ❐ ICC ■ Low CMOS standby power ❐ ISB2 ■ ■ ■ 2.0 V data retention Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed/power Transistor-transistor logic (TTL) compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 28-pin 300-Mil-wide molded small outline J-lead package (SOJ) and 28-pin thin small outline package (TSOP) I packages ■ ■ ■ Logic Block Diagram I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Cypress Semiconductor Corporation Document Number: 38-05471 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 2, 2011 [+] Feedback CY7C199D Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Document Number: 38-05471 Rev. *I Page 2 of 14 [+] Feedback CY7C199D Pin Configuration Figure 1. 28-pin SOJ (Top View) Figure 2. 28-pin TSOP I (Top View) A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current -10 (Industrial) 10 80 3 Unit ns mA mA Document Number: 38-05471 Rev. *I Page 3 of 14 [+] Feedback CY7C199D Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Supply voltage on VCC to relative GND [1] ................................–0.5 V to +6.0 V DC voltage applied to outputs in high Z State [1] ................................ –0.5 V to VCC + 0.5 V DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage ........................................ > 2,001 V (per MIL-STD-883, method 3015) Latch-up current ................................................... > 140 mA Operating Range Range Industrial Ambient Temperature VCC Speed 10 ns –40 C to +85 C 5 V  0.5 V Electrical Characteristics Over the operating range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage [1] Input LOW voltage [1] Test Conditions IOH = –4.0 mA IOL = 8.0 mA CY7C199D-10 Min 2.4 – 2.2 –0.5 Max – 0.4 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 3 Unit V V V V µA µA mA mA mA mA mA mA Input leakage current Output leakage current VCC operating supply current GND < VI < VCC GND < VO < VCC, output disabled VCC = VCC(max), IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz –1 –1 – – – – – – ISB1 ISB2 Automatic CE power-down current— TTL Inputs Automatic CE power-down current— CMOS Inputs VCC = VCC(max), CE > VIH, VIN > VIH or VIN < VIL, f = fmax VCC = VCC(max), CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 Note 1. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document Number: 38-05471 Rev. *I Page 4 of 14 [+] Feedback CY7C199D Capacitance Parameter [2] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max 8 8 Unit pF pF Thermal Resistance Parameter [2] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 28-pin SOJ 59.16 40.84 28-pin TSOP I Unit 54.65 21.49 C/W C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [3] Z = 50  OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V Rise Time: 3 ns ALL INPUT PULSES 3.0 V 30pF* GND 10% 90% 90% 10% (a) High Z characteristics: 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255  (b) Fall Time: 3 ns R1 480  (c) Notes 2. Tested initially and after any design or process changes that may affect these parameters. 3. AC characteristics (except high Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (c). Document Number: 38-05471 Rev. *I Page 5 of 14 [+] Feedback CY7C199D Switching Characteristics Over the operating range Parameter [4] Read Cycle tpower [5] tRC tAA tOHA tACE tDOE tLZOE tLZCE tHZCE tPU [8] [6] Description CY7C199D-10 Min Max Unit VCC(typical) to the first access Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z OE HIGH to high Z CE LOW to low Z CE HIGH to high Z CE LOW to power-up CE HIGH to power-down [9, 10] 100 10 – 3 – – 0 – 3 – 0 – – – 10 – 10 5 – 5 – 5 – 10 s ns ns ns ns ns ns ns ns ns ns ns tHZOE [6, 7] [6] [6, 7] tPD [8] Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [6] [6, 7] Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z WE HIGH to low Z 10 7 7 0 0 7 6 0 – 3 – – – – – – – – 5 – ns ns ns ns ns ns ns ns ns ns Notes 4. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured 200 mV from steady-state voltage. 8. This parameter is guaranteed by design and is not tested. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05471 Rev. *I Page 6 of 14 [+] Feedback CY7C199D Data Retention Characteristics Over the operating range Parameter VDR ICCDR tCDR [11] tR [12] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Conditions Min 2.0 Max – 3 – – Unit V mA ns ns VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V – 0 15 Data Retention Waveform DATA RETENTION MODE VCC CE 4.5 V tCDR VDR > 2 V 4.5 V tR Switching Waveforms Figure 4. Read Cycle No. 1: Address Transition Controlled [13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle No. 2 OE Controlled [14, 15] CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD ICC 50% ISB tHZOE tHZCE tRC HIGH IMPEDANCE Notes 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05471 Rev. *I Page 7 of 14 [+] Feedback CY7C199D Switching Waveforms (continued) Figure 6. Write Cycle No. 1: CE Controlled [16, 17, 18] tWC ADDRESS CE tSA tAW tHA tSCE WE tSD DATA I/O DATA IN VALID tHD Figure 7. Write Cycle No. 3 WE Controlled, OE LOW [18, 19] tWC ADDRESS CE tAW tSA WE tHA tSD DATA IO tHD NOTE 20 tHZWE DATAIN VALID tLZWE Notes 16. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 20. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05471 Rev. *I Page 8 of 14 [+] Feedback CY7C199D Truth Table CE H L L L WE X H L H OE X L X H High Z Data out Data in High Z Inputs/Outputs Read Write Deselect, output disabled Mode Deselect/power-down Active (ICC) Active (ICC) Active (ICC) Power Standby (ISB) Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 10 Ordering Code CY7C199D-10VXI CY7C199D-10ZXI Package Diagram Package Type Operating Range Industrial 51-85031 28-pin (300-Mil) Molded SOJ (Pb-free) 51-85071 28-pin TSOP Type I (Pb-free) Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 9 9 D - XX X X I Temperature Grade: I I = Industrial Pb-free Package Type: V or Z V = 28 pin (300-Mil) Molded SOJ Z = 28 pin TSOP Type 1 Speed Grade: 10 ns Process Technology: 90 nm Bus Width = × 8 Density = 256 K Fast SRAM Family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05471 Rev. *I Page 9 of 14 [+] Feedback CY7C199D Package Diagrams Figure 8. 28-pin SOJ 300-Mils V28.3 (Molded SOJ V21) 51-85031 *D Document Number: 38-05471 Rev. *I Page 10 of 14 [+] Feedback CY7C199D Package Diagrams (continued) Figure 9. 28-pin TSOP Type 1 (8 × 13.4 × 1.2 mm) Z28 (Standard) 51-85071 *I Document Number: 38-05471 Rev. *I Page 11 of 14 [+] Feedback CY7C199D Acronyms Acronym CE CMOS I/O OE SOJ SRAM TSOP TTL WE chip enable complementary metal oxide semiconductor input/output output enable small outline J-lead static random access memory thin small outline package transistor-transistor logic write enable Description Document Conventions Units of Measure Symbol °C µA µs mA mm ns pF V W degree Celsius micro Amperes micro seconds milli Amperes milli meter nano seconds pico Farad Volts Watts Unit of Measure Document Number: 38-05471 Rev. *I Page 12 of 14 [+] Feedback CY7C199D Document History Page Document Title: CY7C199D, 256 K (32 K × 8) Static RAM Document Number: 38-05471 Revision ** *A *B ECN 201560 233728 262950 Orig. of Change SWI RKF RKF Submission Date See ECN See ECN See ECN Description of Change Advance Information datasheet for C9 IPP DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information Reduced Speed bins to -10, -12 and -15 ns Converted from Preliminary to Final Removed 12 ns and 15 ns speed bin Removed Commercial Operating range Removed “L” part Removed 28-pin PDIP and 28-pin SOIC package Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins Updated Thermal Resistance table Updated Ordering Information Table Included 28-Pin SOIC package Changed VIH level from 2.0V to 2.2V For Industrial grade, changed tSD from 5 ns to 6 ns, and tHZWE from 6 ns to 5 ns Included Automotive-E information Removed obsolete parts from ordering information table Updated package diagrams Added Auto-E SOIC package related info Changed TDOE spec from 10 ns to 11 ns in CY7C199D-25. Added Ordering Code Definitions. Added Acronyms and Document Conventions. Dislodged Automotive information to a new datasheet (001-65530) Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated Package Diagrams. Updated in new template. *C *D 307594 820660 RKF VKN See ECN See ECN *E 2745093 VKN See ECN *F *G 2897087 3023234 AJU RAME 03/22/10 09/06/2010 *H *I 3130763 3271782 PRAS PRAS 01/07/11 06/02/2011 Document Number: 38-05471 Rev. *I Page 13 of 14 [+] Feedback CY7C199D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05471 Rev. *I Revised June 2, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback