CY7C199N
32K x 8 Static RAM
Features
Functional Description
• High speed
The CY7C199N is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199NN is in
the standard 300-mil-wide DIP, SOJ, and LCC packages.
— 12 ns
• Fast tDOE
• CMOS for optimum speed/power
• Low active power
— 467 mW (max, 12 ns “L” version)
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
• Low standby power
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Logic Block Diagram
Pin Configurations
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1024 x 32 x 8
ARRAY
I/O3
I/O4
I/O5
CE
WE
I/O6
POWER
DOWN
COLUMN
DECODER
I/O7
A 14
A 12
A 13
A 11
A 10
OE
DIP
Top View
OE
A1
A2
A3
A4
WE
V CC
A5
A6
A7
A8
A9
A 10
A 11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
22
23
24
25
26
27
28
1
2
3
4
5
6
7
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TSOP I
Top View
(not to scale)
A0
CE
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A 14
A 13
A 12
Selection Guide
-12
-15
-20
-25
-35
-55
Unit
Maximum Access Time
12
15
20
25
35
55
ns
Maximum Operating Current
160
155
150
150
140
140
mA
90
90
90
80
70
70
10
10
10
10
10
10
0.05
0.05
0.05
0.05
0.05
0.05
L
Maximum CMOS Standby Current
L
Cypress Semiconductor Corporation
Document #: 001-06493 Rev. **
•
198 Champion Court
•
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised February 2, 2006
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CY7C199N
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
Range
Ambient Temperature[2]
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
–55°C to +125°C
5V ± 10%
Commercial
Industrial
Military
DC Input Voltage[1] .................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range [3]
-12
Parameter
Description
Test Conditions
Min.
-15
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.3V
2.2
VCC + 0.3V
V
VIL
Input LOW Voltage
–0.5
0.8
–0.5
0.8
V
–5
+5
–5
+5
µA
–5
+5
–5
+5
µA
160
155
mA
85
100
mA
180
mA
2.4
2.4
V
0.4
IIX
Input Load Current
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
GND < VI < VCC
VCC = Max., IOUT = 0 mA, Com’l
f = fMAX = 1/tRC
L
Mil
ISB1
ISB2
Automatic CE
Power-down Current—
TTL Inputs
Max. VCC, CE > VIH, VIN > Com’l
VIH or VIN < VIL, f = fMAX L
30
30
mA
5
5
mA
Automatic CE
Power-down Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
10
10
mA
0.05
0.05
mA
15
mA
Com’l
L
Mil
Electrical Characteristics Over the Operating Range[3]
-20
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
IOZ
Output Leakage Current GND < VI < VCC, Output
Disabled
ICC
VCC Operating Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l
-35
-55
Min. Max. Min. Max. Min. Max.
2.4
2.4
0.4
2.2
GND < VI < VCC
-25
2.4
0.4
Min.
Max. Unit
2.4
0.4
VCC 2.2 VCC 2.2 VCC
+0.3V
+0.3V
+0.3V
V
0.4
V
2.2
VCC
+0.3V
V
–0.5
0.8
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
–5
+5
–5
+5
–5
+5
–5
+5
µA
–5
+5
–5
+5
–5
+5
–5
+5
µA
140
mA
150
150
140
L
90
80
70
70
mA
Mil
170
150
150
150
mA
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
Document #: 001-06493 Rev. **
Page 2 of 10
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CY7C199N
Electrical Characteristics Over the Operating Range[3]
-20
Parameter
ISB1
ISB2
Description
Test Conditions
-25
-35
-55
Min. Max. Min. Max. Min. Max.
Min.
Max. Unit
Automatic CE
Power-down Current—
TTL Inputs
Max. VCC, CE > VIH, Com’l
VIN > VIH or VIN <
L
VIL, f = fMAX
30
30
25
25
mA
5
5
5
5
mA
Automatic CE
Power-down Current—
CMOS Inputs
Max. VCC,
Com’l
CE > VCC – 0.3V
L
VIN > VCC – 0.3V or
Mil
VIN < 0.3V, f = 0
10
10
10
10
mA
0.05
0.05
0.05
0.05
mA
15
15
15
15
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
8
pF
AC Test Loads and Waveforms[5]
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
255 Ω
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
3.0V
5 pF
INCLUDING
JIG AND
SCOPE
(a)
10%
R2
255Ω
90%
10%
90%
GND
≤tr
≤tr
(b)
THÉVENIN EQUIVALENT
167 Ω
OUTPUT
1.73V
Data Retention Characteristics Over the Operating Range (L-version only)
Parameter
Conditions[6]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Min.
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
Chip Deselect to Data Retention Time VIN < 0.3V
tCDR
tR
[5]
Operation Recovery Time
Unit
V
µA
Com’l
Com’l L
[4]
Max.
10
µA
0
ns
200
µs
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
tCDR
3.0V
tR
CE
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
5. tR< 3 ns for the -12 and the -15 speeds. tR< 5 ns for the -20 and slower speeds
6. No input may exceed VCC + 0.5V.
Document #: 001-06493 Rev. **
Page 3 of 10
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CY7C199N
Switching Characteristics Over the Operating Range
[3, 7]
7C199-12
Parameter
Description
Min.
Max.
7C199-15
Min.
Max.
7C199-20
Min.
Max.
Unit
Read Cycle
12
20
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
5
7
9
ns
Low-Z[8]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[8, 9]
CE LOW to
Low-Z[8]
tHZCE
CE HIGH to
High-Z[8,9]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
tLZCE
Write
15
12
3
ns
ns
9
7
ns
0
0
12
ns
9
3
3
0
ns
0
7
5
ns
3
0
5
3
20
15
3
0
ns
ns
20
15
ns
Cycle[10, 11]
tWC
Write Cycle Time
12
15
20
ns
tSCE
CE LOW to Write End
9
10
15
ns
tAW
Address Set-up to Write End
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
8
9
15
ns
tSD
Data Set-up to Write End
8
9
10
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[9]
WE HIGH to
Low-Z[8]
7
3
10
7
ns
3
3
ns
Switching Characteristics Over the Operating Range [3, 7]
7C199-25
Parameter
Description
Min.
Max.
7C199-35
Min.
Max.
7C199-55
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z[8]
tHZOE
tLZCE
25
3
CE LOW to
3
3
3
16
0
11
55
ns
16
ns
ns
15
3
ns
ns
0
15
3
ns
55
35
10
0
OE HIGH to High-Z
55
35
25
[8, 9]
Low-Z[8]
35
25
ns
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06493 Rev. **
Page 4 of 10
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CY7C199N
Switching Characteristics Over the Operating Range [3, 7]
7C199-25
Parameter
Description
Min.
Max.
[8, 9]
tHZCE
CE HIGH to High-Z
tPU
CE LOW to Power-up
tPD
Min.
11
0
Max.
7C199-55
Min.
15
0
CE HIGH to Power-down
Write Cycle
7C199-35
20
Max.
Unit
15
ns
0
ns
20
25
ns
[10,11]
tWC
Write Cycle Time
25
35
55
ns
tSCE
CE LOW to Write End
18
22
22
ns
tAW
Address Set-up to Write End
20
30
40
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
18
22
22
ns
tSD
Data Set-up to Write End
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
ns
High-Z[9]
tHZWE
WE LOW to
tLZWE
WE HIGH to Low-Z[8]
11
3
15
3
15
3
ns
ns
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [13, 14]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06493 Rev. **
Page 5 of 10
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CY7C199N
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
tHD
DATAIN VALID
DATA I/O
tHZOE
Write Cycle No. 2 (CE Controlled)[9, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATA IN VALID
Write Cycle No. 3 (WE Controlled OE LOW)[11, 16]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
tHD
DATAIN VALID
tHZWE
tLZWE
Notes:
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 001-06493 Rev. **
Page 6 of 10
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CY7C199N
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
NORMALIZED ICC, ISB
1.2
ICC
0.8
0.6
VIN = 5.0V
TA = 25°C
0.4
0.2
1.0
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
0.2
ISB
0.0
4.0
1.2
4.5
5.0
5.5
ISB
0.0
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
1.4
1.3
NORMALIZED tAA
NORMALIZED tAA
125
1.2
1.1
TA = 25°C
1.0
1.4
1.2
1.0
VCC = 5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
0.6
–55
6.0
120
100
80
VCC = 5.0V
60
TA = 25°C
40
20
0
0.0
25
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
2.5
25.0
DELTA t AA (ns)
30.0
2.0
1.5
1.0
0.5
2.0
3.0
4.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
VCC = 5.0V
TA = 25°C
40
20
0
0.0
125
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
1.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.0
0.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED IPO
25
OUTPUT SINK CURRENT (mA)
1.0
ICC
NORMALIZED ICC vs. CYCLE TIME
1.25
20.0
15.0
VCC = 4.5V
TA = 25°C
10.0
NORMALIZED ICC
NORMALIZED ICC, ISB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
1.00
VCC = 5.0V
TA = 25°C
VIN = 0.5V
0.75
5.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 001-06493 Rev. **
5.0
0.0
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 7 of 10
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CY7C199N
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Output disabled
Active (ICC)
Ordering Information
Speed
(ns)
12
15
20
25
35
55
Ordering Code
CY7C199N-12ZXC
CY7C199N-15ZXC
CY7C199NL-15ZXC
CY7C199N-20PXC
CY7C199N-20ZXC
CY7C199N-25PXC
CY7C199N-35PXC
CY7C199N-55PXC
Package
Diagram
51-85071
51-85071
51-85071
51-85014
51-85071
51-85014
51-85014
51-85014
Package Type
28-Lead TSOP 1 (Pb-free)
28-Lead TSOP 1 (Pb-free)
28-Lead TSOP 1 (Pb-free)
28-Lead (300-Mil) Molded DIP (Pb-free)
28-Lead TSOP 1 (Pb-free)
28-Lead (300-Mil) Molded DIP (Pb-free)
28-Lead (300-Mil) Molded DIP (Pb-free)
28-Lead (300-Mil) Molded DIP (Pb-free)
Operating
Range
Commercial
Commercial
Commercial
Commercial
Contact your Local Cypress sales representative for availability of these parts
Package Diagrams
28-Lead TSOP 1 (8x13.4 mm) (51-85071)
51-85071-*G
Document #: 001-06493 Rev. **
Page 8 of 10
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CY7C199N
Package Diagrams (continued)
28-Lead (300-Mil) PDIP (51-85014)
SEE LEAD END OPTION
14
1
DIMENSIONS IN INCHES [MM] MIN.
MAX.
REFERENCE JEDEC MO-095
0.260[6.60]
0.295[7.49]
15
PACKAGE WEIGHT: 2.15 gms
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.115[2.92]
0.160[4.06]
0.015[0.38]
0.060[1.52]
0.090[2.28]
0.110[2.79]
0.009[0.23]
0.012[0.30]
0.055[1.39]
0.065[1.65]
3° MIN.
0.310[7.87]
0.385[9.78]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
LEAD END OPTION
51-85014-*D
(LEAD #1, 14, 15 & 28)
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06493 Rev. **
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C199N
Document History Page
Document Title: CY7C199N 32K x 8 Static RAM
Document Number: 001-06493
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
423877
See ECN
NXR
Document #: 001-06493 Rev. **
Description of Change
New Data Sheet
Page 10 of 10
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