CY7C199N_10

CY7C199N 32 K × 8 Static RAM Features ■ Functional Description The CY7C199N is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199NN is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity. High speed — 15 ns Fast tDOE CMOS for optimum speed/power Low active power — 550 mW (max, 15 ns “L” version) Low standby power — 0.275 mW (max, “L” version) 2V data retention (“L” version only) Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE ROW DECODER I/O2 SENSE AMPS 1024 x 32 x 8 ARRAY I/O3 I/O4 I/O5 COLUMN DECODER POWER DOWN I/O6 I/O7 A 10 A 12 A 13 A 11 A 14 Cypress Semiconductor Corporation Document #: 001-06493 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 13, 2010 [+] Feedback CY7C199N Pin Configurations OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 14 A 13 A 12 Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current L L -15 15 100 0.05 Unit ns mA mA Document #: 001-06493 Rev. *B Page 2 of 11 [+] Feedback CY7C199N Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65C to +150C Ambient Temperature with Power Applied ............................................ –55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14)............................................–0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[1] .................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Commercial Ambient Temperature[2] 0C to +70C VCC 5V  10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current GND < VI < VCC GND < VO < VCC, Output Disabled L Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –5 –5 -15 Min. 2.4 0.4 VCC + 0.3V 0.8 +5 +5 100 5 Max. Unit V V V V A A mA mA VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Power-down Current— TTL Inputs Max. VCC, CE > VIH, VIN > VIH L or VIN < VIL, f = fMAX L ISB2 Max. VCC, Automatic CE Power-down Current— CMOS CE > VCC – 0.3V Inputs VIN > VCC – 0.3V or VIN < 0.3V, f = 0 0.05 mA Notes 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. Document #: 001-06493 Rev. *B Page 3 of 11 [+] Feedback CY7C199N Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF AC Test Loads and Waveforms[4] 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 255  R1 481  5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 167  OUTPUT 1.73V R2 255 R1 481  ALL INPUT PULSES 3.0V GND 10% tr 90% 90% 10% tr (a) (b) THÉVENIN EQUIVALENT Data Retention Characteristics Over the Operating Range (L-version only) Parameter VDR ICCDR tCDR[3] tR [4] Description VCC for Data Retention Conditions[5] Min. 2.0 Max. 10 Unit V A ns s VCC = VDR = 2.0V, CE > VCC – 0.3V, Data Retention Current L VIN > VCC – 0.3V or Chip Deselect to Data Retention Time VIN < 0.3V Operation Recovery Time 0 200 Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Note 3. Tested initially and after any design or process changes that may affect these parameters. 4. tR< 3 ns for -15 speed. 5. No input may exceed VCC + 0.5V. Document #: 001-06493 Rev. *B Page 4 of 11 [+] Feedback CY7C199N Switching Characteristics Over the Operating Range Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[9, 10] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[8] WE HIGH to Low-Z[7] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[7] [7, 8] [7] [6] Description 7C199-15 Min. 15 15 3 15 7 0 7 3 7 0 15 15 10 10 0 0 9 9 0 7 3 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High-Z CE LOW to Low-Z CE HIGH to High-Z[7,8] CE LOW to Power-up CE HIGH to Power-down Notes: 6. Test conditions assume signal transition time of 3 ns or less for -15 speed, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06493 Rev. *B Page 5 of 11 [+] Feedback CY7C199N Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 [12, 13] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD ICC 50% ISB tRC DATA OUT HIGH IMPEDANCE Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-06493 Rev. *B Page 6 of 11 [+] Feedback CY7C199N Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[9, 14, 15] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O tHZOE DATAIN VALID tHD Write Cycle No. 2 (CE Controlled)[8, 14, 15] tWC ADDRESS CE tSA tAW tHA tSCE WE tSD DATA I/O DATA IN VALID tHD Write Cycle No. 3 (WE Controlled OE LOW)[10, 15] tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O tHZWE Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. tHD DATAIN VALID tLZWE Document #: 001-06493 Rev. *B Page 7 of 11 [+] Feedback CY7C199N Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN = 5.0V TA = 25°C ICC NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE NORMALIZED ICC, ISB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 ICC 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 125 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 NORMALIZED tAA 1.4 1.2 1.0 0.8 0.6 –55 VCC = 5.0V VCC = 5.0V VIN = 5.0V OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25°C SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE OUTPUT SINK CURRENT (mA) 140 120 100 80 60 40 20 TA = 25°C VCC = 5.0V TA = 25°C 25 125 0 0.0 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO DELTA t AA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC OUTPUT VOLTAGE (V) NORMALIZED ICC vs. CYCLE TIME 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 VCC = 4.5V TA = 25°C 1.00 VCC = 5.0V TA = 25°C VIN = 0.5V 0.75 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 001-06493 Rev. *B Page 8 of 11 [+] Feedback CY7C199N Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Selected, Output disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 15 Ordering Code CY7C199NL-15ZXC Package Diagram 51-85071 Package Type 28-lead TSOP 1 (Pb-free) Operating Range Commercial Ordering Code Definitions CY 7 C 1 99 NL - 15 ZX C Temperature Range: C = Commercial Package Type: ZX = 28-lead TSOP 1 (Pb-free) Speed: 15 ns NL = low power 99 = 256 K bit density with datawidth × 8 bits 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Contact your Local Cypress sales representative for availability of these parts Document #: 001-06493 Rev. *B Page 9 of 11 [+] Feedback CY7C199N Package Diagrams Figure 1. 28-pin TSOP 1 (8 x 13.4 mm), 51-85071 51-85071 *H Document #: 001-06493 Rev. *B Page 10 of 11 [+] Feedback CY7C199N Document History Page Document Title: CY7C199N 32 K × 8 Static RAM Document Number: 001-06493 REV. ** *A ECN NO. Issue Date 423877 2892510 See ECN 03/18/2010 Orig. of Change NXR VKN New Data Sheet Removed speed bins from the data sheet: 12ns, 20ns, 25ns, 35ns, and 55ns. Removed Industrial and Military product information Removed 28-pin (300-Mil) PDIP package Updated Ordering Information table Updated Package Diagram Added Ordering Code Definitions. Description of Change *B 3109199 12/13/2010 AJU Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06493 Rev. *B Revised December 13, 2010 Page 11 of 11 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback