CY7C235A-18PC

1CY 7C23 5A CY7C235A 1K x 8 Registered PROM Features • CMOS for optimum speed/power • High speed — 18 ns address set-up — 12 ns clock to output • Low power — 495 mW (commercial) — 660 mW (military) • Synchronous and asynchronous output enables • On-chip edge-triggered registers • Programmable asynchronous registers (INIT) • EPROM technology, 100% programmable • Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin LCC and PLCC • 5V ±10% VCC, commercial and military • TTL-compatible I/O • Direct replacement for bipolar PROMs • Capable of withstanding greater than 2001V static discharge Functional Description The CY7C235A is a high-performance 1024 word by 8 bit electrically programmable read only memory packaged in a slim 300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, or 28-pin plastic leaded chip carrier. The memory cells utilize proven EPROM floating gate technology and byte-wide intelligent programming algorithms. The CY7C235A replaces bipolar devices pin for pin and offers the advantages of lower power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the supervoltage, and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that the product will meet AC specification limits after customer programming. Logic Block Diagram INIT O7 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CP CP O0 COLUMN ADDRESS ADDRESS DECODER ROW ADDRESS PROGRAMMABLE ARRAY MUL TIPLEXER O5 8-BIT EDGETRIGGERED REGISTER O4 O3 O2 O1 O6 Pin Configuration DIP Top View A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 E INIT ES CP O7 O6 O5 O4 O3 C235A-2 LCC/PLCC Top View ES E C235A-1 A4 A3 A2 A1 A0 NC O0 4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 1314151617 18 E INIT ES CP NC O7 O6 C235A-3 Selection Guide Minimum Address Set-Up Time (ns) Maximum Clock to Output (ns) Maximum Operating Commercial Current (mA) Military 7C235A-18 18 12 90 7C235A-25 25 12 90 120 7C235A-30 30 15 90 120 7C235A-40 40 20 90 120 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 1992 – Revised March 1995 CY7C235A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12 for DIP) .................................. − 0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .................................................... − 0.5V to +7.0V DC Input Voltage .................................................−3.0V to +7.0V DC Program Voltage (Pins 7, 18, 20 for DIP) ............... 13.0V Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Military[2] [1] Ambient Temperature 0°C to +70°C − 40°C to +85°C − 55°C to +125°C VCC 5V ±10% 5V ±10% 5V ±10% Electrical Characteristics Over Operating Range[3] Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC VPP IPP VIHP VILP Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Input Clamp Diode Voltage Output Leakage Current Output Short Circuit Current Power Supply Current Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage 3.0 0.4 Test Conditions VCC = Min., IOH = −4.0 mA VIN = VIH or VIL VCC = Min., IOL = 16 mA VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for All Inputs[4] Guaranteed Input Logical LOW Voltage for All Inputs[4] GND < VIN < VCC Note 5 GND < VOUT < VCC Output Disabled[4] VCC = Max., VOUT = IOUT = 0 mA, VCC = Max. 0.0V[6] Commercial Military 12 −10 −20 +10 −90 90 120 13 50 V mA V V µA mA mA −10 2.0 0.8 +10 Min. 2.4 0.4 Max. Unit V V V V µA Capacitance[5] Parameter CIN COUT Notes: 1. 2. 3. 4. 5. 6. a Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC =5.0V Max. 10 10 Unit pF pF Contact a Cypress representative for industrial temperature range specifications. TA i s the “instant on” case temperature. See the last page of this specification for Group A subgroup testing information. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. See Introduction to CMOS PROMs in this Data Book for general information on testing. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 2 CY7C235A AC Test Loads and Waveforms[5] 5V OUTPUT 50pF INCLUDING JIGAND SCOPE R2 167 Ω R1 250 Ω 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R2 167 Ω 3.0V GND ≤ 5 ns C235A-4 R1 250 Ω ALL INPUT PULSES 90% 10% 90% 10% ≤ 5 ns C235A-5 (a) Normal Load Equivalent to: (b) High Z Load TH ÉVENIN EQUIVALENT 100Ω 2.0V C235A-6 OUTPUT Operating Modes The CY7C235A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with synchronous (ES) and asynchronous (E) output enables and asynchronous initialization (INIT). Upon power-up, the synchronous enable (ES) flip-flop will be in the set condition causing the outputs (O0 − O7) to be in the OFF or high-impedance state. Data is read by applying the memory location to the address input (A0 − A9) and a logic LOW to the enable (ES) input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (O0 − O 7), provided the asynchronous enable (E) is also LOW. The outputs may be disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. Regardless of the condition of E, the outputs will go to the OFF or high-impedance state upon the next positive clock edge after the synchronous enable (ES) input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW, the subsequent positive clock edge will return the output to the active state if E is LOW. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C235A decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs. System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers available in the market. The CY7C235A has an asynchronous initialize input (INIT). The initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophisticated functions such as a built-in “jump start” address. When activated the initialize control input causes the contents of a user programmed 1025th 8-bit word to be loaded into the on-chip register. Each bit is programmable and the initialize function can be used to load any desired combination of 1s and 0s into the register. In the unprogrammed state, activating INIT will generate a register CLEAR (all outputs LOW). If all the bits of the initialize word are programmed, activating INIT performs a register PRESET (all outputs HIGH). Applying a LOW to the INIT input causes an immediate load of the programmed initialize word into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW. When power is applied the (internal) synchronous enable flip-flop will be in a state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur and the ES input pin must be LOW at least a set-up time prior to the clock LOW-to-HIGH transition. The E input may then be used to enable the outputs. When the asynchronous initialize input, INIT, is LOW, the data in the initialize byte will be asynchronously loaded into the output register. It will not, however, appear on the output pins until they are enabled, as described in the preceding paragraph. 3 CY7C235A Switching Characteristics Over Operating Range[3, 5] 7C235A-18 Parameter tSA tHA tCO tPWC tSES tHES tDI tRI tPWI tCOS tHZC tDOE tHZE Notes: 7. Applies only when the synchronous (ES) function is used. 7C235A-25 Min. 25 0 Max. 7C235A-30 Min. 30 0 Max. 7C235A-40 Min. 40 0 Max. Unit ns ns 20 20 15 5 ns ns ns ns 35 20 25 ns ns ns 25 25 25 25 ns ns ns ns Description Address Set-Up to Clock HIGH Address Hold from Clock HIGH Clock HIGH to Valid Output Clock Pulse Width ES Set-Up to Clock HIGH ES Hold from Clock HIGH Delay from INIT to Valid Output INIT Recovery to Clock HIGH INIT Pulse Width Inactive to Valid Output from Clock HIGH[7] Inactive Output from Clock Valid Output from E LOW Inactive Output from E HIGH HIGH[7] Min. 18 0 Max. 12 12 10 5 20 15 15 15 15 15 15 20 20 12 10 5 12 15 10 5 25 20 20 20 20 20 20 15 25 20 20 20 20 Switching Waveforms[5] tHA A0 − A10 tSES tHES tSES tHES tSA tHA ES tSES tHES CP tPWC tPWC tPWC tPWC tPWC tPWC O0 − O7 tCO tHZC tCOS tCO tHZE tDOE E tDI INIT tPWI C235A-7 tRI Programming Information Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. 4 CY7C235A Table 1. Mode Selection. Pin Function[8] Read or Output Disable Mode Read Output Disable Output Disable Initialize Program Program Verify Program Inhibit Intelligent Program Program Initialize Byte Blank Check Notes: 8. X = “don’t care” but not to exceed VCC ±5%. DIP Top View A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 E VPP VFY PGM D7 D6 D5 D4 D3 C235A-8 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A0, A3 − A9 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 VPP A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 VILP A2 CP PGM X X X X VILP VIHP VIHP VILP VILP VIHP ES VFY VIL VIH X X VIHP VILP VIHP VIHP VIHP VILP E E VIL X VIH VIL VIHP VIHP VIHP VIHP VIHP VIHP INIT VPP VIH VIH VIH VIL VPP VPP VPP VPP VPP VPP O7 − O0 D7 − D0 O7 − O0 High Z High Z Init Byte D7 − D0 O7 − O0 High Z D7 − D0 D7 − D0 Zeros Other LCC/PLCC Top View A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 4 3 2 1 28 27 26 25 24 23 22 21 20 19 121314151617 18 E VPP VFY PGM NC D7 D6 C235A-9 Figure 1. Programming Pinouts. 5 CY7C235A Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 1.4 1.1 1.2 1.0 1.0 0.8 0.6 4.0 TA =25°C f = fMAX 4.5 5.0 5.5 6.0 0.9 1.0 0.8 0.6 4.0 1.2 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 CLOCK TO OUTPUT TIME vs. V CC TA =25°C 4.5 5.0 5.5 6.0 0.8 −55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) CLOCK TO OUTPUT TIME vs. TEMPERATURE 1.6 1.4 1.2 0.8 1.0 0.8 0.6 −55 0.6 1.2 1.0 NORMALIZED SET-UP TIME vs. SUPPLY VOLTAGE 1.6 1.4 1.2 1.0 TA =25°C 0.8 0.6 −55 NORMALIZED SET-UP TIME vs. TEMPERATURE 25 125 0.4 4.0 4.5 5.0 5.5 6.0 25 125 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0 25 50 75 100 15.0 10.0 5.0 0.0 VCC =5.5V TA =25°C 30.0 25.0 20.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 175 150 125 100 75 50 TA =25°C VCC =4.5V 0 200 400 600 800 1000 25 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE VCC =5.0V TA =25°C 0 0.0 1.0 2.0 3.0 4.0 CLOCK PERIOD (ns) CAPACITANCE (pF) OUTPUT VOLTAGE (V) C235A-10 6 CY7C235A Ordering Information[9] Speed (ns) tSA tCO Ordering Code 18 12 CY7C235A-18DC CY7C235A-18JC CY7C235A-18PC 25 12 CY7C235A-25DC CY7C235A-25JC CY7C235A-25PC CY7C235A-25DMB CY7C235A-25LMB 30 15 CY7C235A-30DC CY7C235A-30JC CY7C235A-30PC CY7C235A-30DMB CY7C235A-30LMB 40 20 CY7C235A-40DC CY7C235A-40JC CY7C235A-40PC CY7C235A-40DMB CY7C235A-40LMB Notes: 9. Most of the above products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability. Package Name D14 J64 P13 D14 J64 P13 D14 L64 D14 J64 P13 D14 L64 D14 J64 P13 D14 L64 Package Type 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier Operating Range Commercial Commercial Military Commercial Military Commercial Military MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter tSA tHA tCO Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Document #: 38-00229-C 7 CY7C235A Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D-9 Config.A 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 8 CY7C235A Package Diagrams (Continued) 24-Lead (300-Mil) Molded DIP P13/P13A © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.