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CY7C25442KV18
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture
(2.0 Cycle Read Latency) with ODT
CY7C25442KV18, 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
Features
■
JTAG 1149.1 compatible test access port
■
Phase Locked Loop (PLL) for accurate data placement
■
Separate independent read and write data ports
❐ Supports concurrent transactions
■
333-MHz clock for high bandwidth
■
Two-word burst for reducing address bus frequency
■
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Functional Description
■
Available in 2.0 clock cycle latency
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
On-die termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
QDR® II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
The CY7C25442KV18 are 1.8-V synchronous pipelined SRAMs,
equipped with QDR II+ architecture. Similar to the QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn around”
the data bus that exists with common devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II+ read and write ports are
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with two 36-bit words
(CY7C25442KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K),
memory bandwidth is maximized while simplifying system
design by eliminating bus “turnarounds”.
■
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■
Available in × 36 configurations
■
Full data coherency, providing most current data
■
Core VDD = 1.8 V ± 0.1 V; VDDQ = 1.4 V to VDD [1]
❐ Supports both 1.5 V and 1.8 V supply
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C25442KV18 – 2M × 36
These devices have an on-die termination feature supported for
D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external
termination resistors, reduce cost, reduce board area, and
simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum operating frequency
Maximum operating current
× 36
333 MHz
333
990
300 MHz
300
910
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation
Document Number: 001-66481 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2020
CY7C25442KV18
Logic Block Diagram – CY7C25442KV18
K
CLK
Gen.
DOFF
20
Address
Register
Read Add. Decode
K
Write
Reg
1M x 36 Array
Address
Register
Write
Reg
1M x 36 Array
A(19:0)
20
36
Write Add. Decode
D[35:0]
A(19:0)
RPS
Control
Logic
Read Data Reg.
CQ
72
VREF
WPS
BWS[3:0]
36
Control
Logic
36
Reg.
Reg. 36
Reg.
36
CQ
36
Q[35:0]
QVLD
Document Number: 001-66481 Rev. *H
Page 2 of 28
CY7C25442KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
On-Die Termination (ODT) .......................................... 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port ....................................................... 10
Performing a TAP Reset ........................................... 10
TAP Registers ........................................................... 10
TAP Instruction Set ................................................... 10
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Electrical Characteristics ...................................... 13
TAP AC Switching Characteristics ............................... 14
TAP Timing and Test Conditions .................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Document Number: 001-66481 Rev. *H
Boundary Scan Order .................................................... 17
Power Up Sequence in QDR II+ SRAM ......................... 18
Power-Up Sequence ................................................. 18
PLL Constraints ......................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write/Deselect Sequence ................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC® Solutions ....................................................... 28
Cypress Developer Community ................................. 28
Technical Support ..................................................... 28
Page 3 of 28
CY7C25442KV18
Pin Configurations
The pin configuration for CY7C25442KV18 follows. [2]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C25442KV18 (2M × 36)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/288M
A
WPS
BWS2
K
BWS1
RPS
A
NC/144M
CQ
B
Q27
Q18
D18
A
BWS3
K
BWS0
A
D17
Q17
Q8
C
D27
Q28
D19
VSS
A
A
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
QVLD
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
ODT
A
A
A
TMS
TDI
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-66481 Rev. *H
Page 4 of 28
CY7C25442KV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous CY7C25442KV18 − D[35:0]
WPS
InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
A
InputAddress Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during
Synchronous active read and write operations. These address inputs are multiplexed for both read and write
operations. Internally, the device is organized as 2M × 36 (2 arrays each of 1M × 36) for
CY7C25442KV18. Therefore, only 20 address inputs for CY7C25442KV18. These inputs are ignored
when the appropriate port is deselected.
Q[x:0]
OutputData Output Signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of the K and K clocks during read operations. When the read port is
deselected, Q[x:0] are automatically tristated.
RPS
InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active,
Synchronous a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge
of the K clock. Each read access consists of a burst of two sequential transfers.
CY7C25442KV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
CY7C25442KV18 − Q[35:0]
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
ODT [3]
On-Die
Termination
input pin
On-Die Termination Input. This pin is used for on-die termination of the input signals. ODT range
selection is made during power-up initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175 Ω < RQ < 350 Ω (where RQ is the resistor tied to ZQ pin). A HIGH on this pin selects
a high range that follows RQ/1.66 for 175 Ω < RQ < 250 Ω (where RQ is the resistor tied to the ZQ pin).
When left floating, a high range termination value is selected by default.
Note
3. On-Die Termination (ODT) feature is supported for D[x:0], BWS[x:0], and K/K inputs.
Document Number: 001-66481 Rev. *H
Page 5 of 28
CY7C25442KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q[x:0].
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free-running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in Switching Characteristics on page 22.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free-running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The
timing in the operation with the PLL turned off differs from those listed in this datasheet. For normal
operation, connect this pin to a pull-up through a 10 KΩ or less pull-up resistor. The device behaves in
the QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of
up to 167 MHz with QDR I timing.
TDO
Output
TDO Pin for JTAG.
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
Input
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
Input
Not Connected to the Die. Can be tied to any voltage level.
VREF
InputReference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD
Power
Supply
VSS
Ground
Ground for the Device.
VDDQ
Power
Supply
Power Supply Inputs for the Outputs of the Device.
Power Supply Inputs to the Core of the Device.
Functional Overview
The CY7C25442KV18 are synchronous pipelined Burst SRAMs
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR II+ eliminates
the need to “turn around” the data bus and avoids any possible
data contention, thereby simplifying system design. Each access
consists of two 36-bit data transfers in the case of
CY7C25442KV18 in one clock cycle.
These devices operate with a read latency of two cycles when
the DOFF pin is tied HIGH. When the DOFF pin is set LOW or
connected to VSS, the device behaves in the QDR I mode with a
read latency of one clock cycle.
Document Number: 001-66481 Rev. *H
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input and output timing
are referenced from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C25442KV18 is described in the following sections.
Read Operations
The CY7C25442KV18 is organized internally as two arrays of
1M × 36. Accesses are completed in a burst of two sequential
36-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
Page 6 of 28
CY7C25442KV18
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next two K clocks rise, the corresponding
lowest order 36-bit word of data is driven on to the Q[35:0] using
K as the output timing reference. On the subsequent rising edge
of K, the next 36-bit data word is driven on to the Q[35:0]. The
requested data is valid 0.45 ns from the rising edge of the input
clock (K and K).
When the read port is deselected, the CY7C25442KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the positive input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise, the data presented to D[35:0] is latched and stored into the
lower 36-bit write data register, provided BWS[3:0] are asserted
active. On the subsequent rising edge of the negative input clock
(K), the address is latched and the information presented to
D[35:0] is also stored into the write data register, provided
BWS[3:0] are asserted active. The 72 bits of data are then written
into the memory array at the specified location.
When deselected, the write port ignores all inputs after the
pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C25442KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0,
BWS1, BWS2 and BWS3, which are sampled with each set of
36-bit data words. Asserting the appropriate Byte Write Select
input during the data portion of a write latches the data being
presented and writes it into the device. Deasserting the Byte
Write Select input during the data portion of a write enables the
data stored in the device for that byte to remain unaltered. This
feature can be used to simplify read, modify, or write operations
to a byte write operation.
Concurrent Transactions
The read and write ports on the CY7C25442KV18 operate
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. The user can start reads and writes in the same clock cycle.
If the ports access the same location at the same time, the SRAM
delivers the most recent information associated with the
specified address location. This includes forwarding data from a
write cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C25442KV18 has a port select input for each port. This
enables easy depth expansion. Both port selects are sampled on
the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Document Number: 001-66481 Rev. *H
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 Ω and 350 Ω, with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR II+. CQ is referenced with respect to K and CQ is
referenced with respect to K. These are free-running clocks and
are synchronized to the input clock of the QDR II+. The timing
for the echo clocks is shown in Switching Characteristics on page
22.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ to simplify data capture on
high-speed systems. The QVLD is generated by the QDR II+
device along with data output. This signal is also edge-aligned
with the echo clock and follows the timing of any data pin. This
signal is asserted half a cycle before valid data arrives.
On-Die Termination (ODT)
These devices have an On-Die Termination feature for Data
inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K
and K). The termination resistors are integrated within the chip.
The ODT range selection is enabled through ball R6 (ODT pin).
The ODT termination tracks the value of RQ where RQ is the
resistor tied to the ZQ pin. The ODT range is selected during
power-up initialization. A LOW on this pin selects a low range
that follows RQ/3.33 for 175 Ω < RQ < 350 Ω (where RQ is the
resistor tied to the ZQ pin). A HIGH on this pin selects a high
range that follows RQ/1.66 for 175 Ω < RQ < 250 Ω (where RQ
is the resistor tied to the ZQ pin). When left floating, a high range
termination value is selected by default. For a detailed
description on the ODT implementation, refer to the application
note, On-Die Termination for QDR® II+/DDR II+ SRAMs AN42468.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power-up, when the DOFF is tied HIGH, the PLL is locked after
20 μs of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 μs after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in the QDR I mode with one cycle latency and a longer
access time). For information, refer to the application note,
AN46982 - PLL Considerations in QDR-II/II+/DDR-II/II+ SRAMS.
Page 7 of 28
CY7C25442KV18
Application Example
Figure 2 shows two QDR II+ used in an application.
Figure 2. Application Example (Width Expansion)
SRAM#1
D[x:0]
A
RPS
WPS
ZQ
CQ/CQ
Q[x:0]
BWS K K
RQ
SRAM#2
D[x:0]
A
RPS
WPS
ZQ
CQ/CQ
Q[x:0]
BWS K K
RQ
DATA IN[2x:0]
DATA OUT [2x:0]
ADDRESS
RPS
WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
FPGA / ASIC
Document Number: 001-66481 Rev. *H
Page 8 of 28
CY7C25442KV18
Truth Table
The truth table for CY7C25442KV18 follows. [4, 5, 6, 7, 8, 9]
Operation
K
RPS WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L–H
X
L
D(A) at K(t) ↑
D(A + 1) at K(t) ↑
Read Cycle: (2.0 cycle Latency)
Load address on the rising edge of K;
wait two cycles; read data on K and K rising edges.
L–H
L
X
Q(A) at K(t + 2) ↑
Q(A + 1) at K(t + 2) ↑
NOP: No Operation
L–H
H
H
D=X
Q = High Z
D=X
Q = High Z
Stopped
X
X
Previous State
Previous State
Standby: Clock Stopped
Write Cycle Descriptions
The write cycle description table for CY7C25442KV18 follows. [4, 10]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
4. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ?represents rising edge.
5. Device powers up deselected with the outputs in a tristate condition.
6. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the internal address sequence in the burst.
7. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
9. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
10. Based on a write cycle that was initiated in accordance with the Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a
write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-66481 Rev. *H
Page 9 of 28
CY7C25442KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power-up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 12. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 16).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-66481 Rev. *H
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 13. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 17 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 16.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 10 of 28
CY7C25442KV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power-up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
Document Number: 001-66481 Rev. *H
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 11 of 28
CY7C25442KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [11]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
1
0
PAUSE-DR
0
0
0
1
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-66481 Rev. *H
Page 12 of 28
CY7C25442KV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
108
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter [12, 13, 14]
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH voltage
IOH = −2.0 mA
1.4
–
V
VOH2
Output HIGH voltage
IOH = −100 μA
1.6
–
V
VOL1
Output LOW voltage
IOL = 2.0 mA
–
0.4
V
VOL2
Output LOW voltage
IOL = 100 μA
–
0.2
V
VIH
Input HIGH voltage
VIL
Input LOW voltage
IX
Input and output load current
0.65 × VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35 × VDD
V
–5
5
μA
Notes
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 19.
13. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3 V (Pulse width less than tCYC/2).
14. All voltage referenced to ground.
Document Number: 001-66481 Rev. *H
Page 13 of 28
CY7C25442KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
Min
Max
Unit
50
–
ns
TCK clock frequency
–
20
MHz
TCK clock HIGH
20
–
ns
TCK clock LOW
20
–
ns
tTCYC
TCK clock cycle time
tTF
tTH
tTL
Setup Times
tTMSS
TMS setup to TCK Clock Rise
5
–
ns
tTDIS
TDI setup to TCK Clock Rise
5
–
ns
tCS
Capture setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
Hold Times
Output Times
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-66481 Rev. *H
Page 14 of 28
CY7C25442KV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [17]
Figure 3. TAP Timing and Test Conditions
0.9 V
ALL INPUT PULSES
1.8 V
0.9 V
50Ω
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTMSH
tTMSS
tTCYC
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Note
17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-66481 Rev. *H
Page 15 of 28
CY7C25442KV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C25442KV18
Revision Number (31:29)
000
Cypress Device ID (28:12)
11010010100100100
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-66481 Rev. *H
Page 16 of 28
CY7C25442KV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-66481 Rev. *H
Page 17 of 28
CY7C25442KV18
Power Up Sequence in QDR II+ SRAM
PLL Constraints
QDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
■
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The PLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 μs of stable clock to
relock to the desired clock frequency.
Power-Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
■
Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs
to lock the PLL
~
~
Figure 4. Power Up Waveforms
K
K
~
~
Unstable Clock
> 20μs Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document Number: 001-66481 Rev. *H
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to VDDQ)
Page 18 of 28
CY7C25442KV18
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Range
Industrial
Ambient
Temperature (TA)
VDD [19]
VDDQ [19]
–40 °C to +85 °C
1.8 ± 0.1 V
1.4 V to
VDD
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD Relative to GND .....–0.5 V to +2.9 V
Supply voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC applied to outputs in High Z ........ –0.5 V to VDDQ + 0.3 V
Neutron Soft Error Immunity
Test
Conditions Typ
DC input voltage [18] ........................... –0.5 V to VDD + 0.3 V
Parameter
Description
Current into outputs (LOW) ........................................ 20 mA
LSBU
Logical
Single-Bit
Upsets
25 °C
LMBU
Logical
Multi-Bit
Upsets
SEL
Single Event
Latch up
Static discharge voltage
(MIL-STD-883, M. 3015) ........................................ > 2,001 V
Latch-up current .................................................... > 200 mA
Max*
Unit
197
216
FIT/
Mb
25 °C
0
0.01
FIT/
Mb
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical χ2, 95% confidence limit calculation. For more details refer to Application
Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure
Rates - AN54908.
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [20]
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power supply voltage
1.7
1.8
1.9
V
VDDQ
Supply voltage
1.4
1.5
VDD
V
VOH
Output HIGH voltage
Note 21
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOL
Output LOW voltage
Note 22
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
–
VDDQ
V
VOL(LOW)
Output LOW voltage
IOL = 0.1 mA, Nominal Impedance
VSS
–
0.2
V
VIH
Input HIGH voltage
VREF + 0.1
–
VDDQ + 0.15
V
VIL
Input LOW voltage
–0.15
–
VREF – 0.1
V
IX
Input leakage current
GND ≤ VI ≤ VDDQ
−2
–
2
μA
IOZ
Output leakage current
GND ≤ VI ≤ VDDQ, Output Disabled
−2
–
2
μA
VREF
Input reference voltage [23] Typical value = 0.75 V
0.68
0.75
0.95
V
Notes
18. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3 V (Pulse width less than tCYC/2).
19. Power up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
20. All Voltage referenced to Ground.
21. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.
22. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.
23. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller.
Document Number: 001-66481 Rev. *H
Page 19 of 28
CY7C25442KV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [20]
IDD [24]
ISB1
Description
VDD Operating Supply
Automatic Power down
Current
Test Conditions
Min
Typ
Max
Unit
VDD = Max, IOUT = 0 mA, 333 MHz (× 36)
f = fMAX = 1/tCYC
300 MHz (× 36)
–
–
990
mA
–
–
910
mA
Max VDD,
333 MHz (× 36)
Both Ports Deselected,
300 MHz (× 36)
VIN ≥ VIH or VIN ≤ VIL,
f = fMAX = 1/tCYC,
Inputs Static
–
–
290
mA
–
–
280
mA
Note
24. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-66481 Rev. *H
Page 20 of 28
CY7C25442KV18
AC Electrical Characteristics
Over the Operating Range
Parameter [25]
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH voltage
VREF + 0.2
–
VDDQ + 0.24
V
VIL
Input LOW voltage
–0.24
–
VREF – 0.2
V
Max
Unit
4
pF
4
pF
Capacitance
Parameter [26]
Description
Test Conditions
TA = 25 °C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
CIN
Input capacitance
CO
Output capacitance
Thermal Resistance
Parameter [26]
ΘJA (0 m/s)
ΘJA (1 m/s)
Description
165-ball FBGA Unit
Package
Test Conditions
Thermal resistance
(junction to ambient)
Socketed on a 170 × 220 × 2.35 mm, eight-layer printed
circuit board
ΘJA (3 m/s)
14.43
°C/W
13.40
°C/W
12.66
°C/W
ΘJB
Thermal resistance
(junction to board)
11.38
°C/W
ΘJC
Thermal resistance
(junction to case)
3.30
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
VREF
0.75 V
VREF
OUTPUT
DEVICE
UNDER
TEST
ZQ
Z0 = 50Ω
RL = 50Ω
VREF = 0.75 V
R = 50Ω
ALL INPUT PULSES
1.25 V
0.75 V
OUTPUT
DEVICE
UNDER
TEST ZQ
RQ =
250Ω
(a)
0.75 V
INCLUDING
JIG AND
SCOPE
5 pF
[27]
0.25 V
SLEW RATE= 2 V/ns
RQ =
250Ω
(b)
Note
25. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3 V (Pulse width less than tCYC/2).
26. Tested initially and after any design or process change that may affect these parameters.
27. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250Ω, VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5.
Document Number: 001-66481 Rev. *H
Page 21 of 28
CY7C25442KV18
Switching Characteristics
Over the Operating Range [27, 28]
Cypress Consortium
Parameter Parameter
333 MHz
Description
VDD(typical) to the first access [29]
tPOWER
300 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
tCYC
tKHKH
K Clock cycle time
3.0
8.4
3.3
8.4
ns
tKH
tKHKL
Input clock (K/K) HIGH
1.20
–
1.32
–
ns
tKL
tKLKH
Input clock (K/K) LOW
1.20
–
1.32
–
ns
tKHKH
tKHKH
K clock rise to K clock rise (rising edge to rising edge)
1.35
–
1.49
–
ns
Setup Times
tSA
tAVKH
Address setup to K clock rise
0.3
–
0.3
–
ns
tSC
tIVKH
Control setup to K clock rise (RPS, WPS)
0.3
–
0.3
–
ns
tSCDDR
tIVKH
DDR control setup to clock (K/K) rise (BWS0, BWS1, BWS2, BWS3)
0.3
–
0.3
–
ns
tSD
tDVKH
D[X:0] setup to clock (K/K) rise
0.3
–
0.3
–
ns
Hold Times
tHA
tKHAX
Address hold after K clock rise
0.3
–
0.3
–
ns
tHC
tKHIX
Control hold after K clock rise (RPS, WPS)
0.3
–
0.3
–
ns
tHCDDR
tKHIX
DDR control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3)
0.3
–
0.3
–
ns
tHD
tKHDX
D[X:0] hold after clock (K/K) rise
0.3
–
0.3
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
0.27
ns
Output Times
tCO
tCHQV
K/K clock rise to data valid
tDOH
tCHQX
Data output hold after output K/K clock rise (active to active)
tCCQO
tCHCQV
K/K clock rise to echo clock valid
tCQOH
tCHCQX
Echo clock hold after K/K clock rise
tCQD
tCQHQV
Echo clock high to data valid
tCQDOH
tCQHQX
Echo clock high to data invalid
–0.25
–
–0.27
–
ns
tCQH
tCQHCQL
Output clock (CQ/CQ) HIGH [30]
1.25
–
1.40
–
ns
1.25
–
1.40
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–0.20
0.20
–0.20
0.20
ns
tCQHCQH
tCHZ
tCQHCQH
tCHQZ
0.25
CQ clock rise to CQ clock rise (rising edge to rising edge)
Clock (K/K) rise to high Z (active to high Z)
[31, 32]
tCLZ
tCHQX1
Clock (K/K) rise to low Z
tQVLD
tCQHQVLD
Echo clock high to QVLD valid [33]
[31, 32]
[30]
PLL Timing
tKC Var
tKC Var
Clock phase jitter
–
0.20
–
0.20
ns
tKC lock
tKC lock
PLL lock time (K)
20
–
20
–
μs
tKC Reset
tKC Reset
K static to PLL reset [34]
30
–
30
–
ns
Notes
28. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
29. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before initiating a read or write operation.
30. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
31. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 21. Transition is measured ± 100 mV from steady state voltage.
32. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
33. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
34. Hold to >VIH or
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