CY7C263-55WMB

1 CY7C261 CY7C263/CY7C264 8K x 8 Power-Switched and Reprogrammable PROM Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns (Commercial) — 25 ns (Military) • Low power — 660 mW (Commercial) — 770 mW (Military) • Super low standby power (7C261) — Less than 220 mW when deselected • • • • — Fast access: 20 ns EPROM technology 100% programmable Slim 300-mil or standard 600-mil packaging available 5V ± 10% VCC, commercial and military Capable of withstanding greater than 2001V static discharge • TTL-compatible I/O • Direct replacement for bipolar PROMs the CY7C261 automatically powers down into a low-power standby mode. It is packaged in a 300-mil-wide package. The CY7C263 and CY7C264 are packaged in 300-mil-wide and 600-mil-wide packages respectively, and do not power down when deselected. The reprogrammable packages are equipped with an erasure window; when exposed to UV light, these PROMs are erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The CY7C261, CY7C263, and CY7C264 are plug-in replacements for bipolar devices and offer the advantages of lower power, superior performance and programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming the product will meet DC and AC specification limits. Read is accomplished by placing an active LOW signal on CS. The contents of the memory location addressed by the address line (A0−A12) will become available on the output lines (O0−O7). Functional Description The CY7C261, CY7C263, and CY7C264 are high-performance 8192-word by 8-bit CMOS PROMs. When deselected, Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 O1 POWER DOWN (7C261) COLUMN ADDRESS O3 ADDRESS DECODER O4 O5 ROW ADDRESS PROGRAMMABLE ARRAY COLUMN MULTIPLEXER O7 Pin Configurations DIP/Flatpack Top View A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 7C261 17 8 7C263 9 7C264 16 10 15 11 14 12 13 VCC A8 A9 A10 CS A11 A12 O7 O6 O5 O4 O3 O6 LCC/PLCC (OpaqueOnly) Top View 4 3 2 1 28 27 26 25 5 24 6 23 7C261 7 22 8 7C263 21 9 20 10 19 11 12 1314151617 18 O1 O2 GND NC O3 O4 O5 A5 A6 A7 NC VCC A8 A9 A4 A3 A2 A1 A0 NC O0 A10 CS A11 A12 NC O7 O6 O2 O0 CS For an 8K x 8 Registered PROM, see theCY7C265. Cypress Semiconductor Corporation Document #: 38-04010 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 28, 2002 CY7C261 CY7C263/CY7C264 Selection Guide 7C261-20 7C263-20 7C264-20 Maximum Access Time Maximum Operating Current Maximum Standby Current (7C261 only) Commercial Military Commercial Military 40 20 120 7C261-25 7C263-25 7C264-25 25 120 140 40 40 7C261-35 7C263-35 7C264-35 35 100 120 30 30 7C261-45 7C263-45 7C264-45 45 100 120 30 30 7C261-55 7C263-55 7C264-55 55 100 120 30 30 Unit ns mA mA mA mA Maximum Ratings[1] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperatures .................................–65°C to+150°C Ambient Temperature with Power Applied..............................................–55°C to+125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12) ............................................ –0.5V to+7.0V DC Voltage Applied to Outputs in High Z State ................................................ –0.5V to+7.0V DC Input Voltage........................................... –3.0V to + 7.0V DC Program Voltage (Pin 19 DIP, Pin 23 LCC) ..............................................13.0V Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA UV Exposure ................................................ 7258 Wsec/cm2 Operating Range Range Commercial Military[2] Ambient Temperature 0°C to + 70°C –55°C to + 125°C VCC 5V ± 10% 5V ± 10% Notes: 1. The volatge on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the “instant on” case temperature. Document #: 38-04010 Rev. *B Page 2 of 14 CY7C261 CY7C263/CY7C264 Electrical Characteristics Over the Operating Range[3,4] 7C261-20, 25 7C263-20, 25 7C264-20, 25 Parameter VOH VOH VOL VOL VIH VIL IIX VCD IOZ IOS ICC ISB VPP IPP VIHP VILP Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Input Diode Clamp Voltage Output Leakage Current Output Short Circuit Current[5] Power Supply Current Standby Supply Current (7C261) Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage 4.75 0.4 GND < VOUT < VCC Output Disabled Com’l Mil Com’l Mil Com’l Mil 12 GND < VIN < VCC –10 –10 –40 –20 Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8 mA (6 mA Mil) VCC = Min., IOL = 16 mA 2.0 0.8 +10 +10 +40 –90 120 140 40 40 13 50 4.75 0.4 12 –10 Note 4 –10 –40 –20 +10 +40 –90 100 120 30 30 13 50 V mA V V mA µA µA mA mA Note 4 2.0 0.8 +10 0.4 0.4 Min. 2.4 2.4 Max. 7C261-35, 45, 55 7C263-35, 45, 55 7C264-35, 45, 55 Min. Max. Unit V V V V V V µA VCC = Max., VOUT = GND VCC = Max., f = Max. IOUT = 0 mA VCC = Max., CS > VIH Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF Notes: 3. See the last page of this specification for Group A subgroup testing information. 4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing. 5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.] Document #: 38-04010 Rev. *B Page 3 of 14 CY7C261 CY7C263/CY7C264 AC Test Loads and Waveforms[4] Test Load for -20 through -30 speeds R1 500 (658Ω MIL) 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 333Ω (403Ω MIL) 5 pF INCLUDING JIG AND SCOPE R2 333Ω (403Ω MIL) R1 500Ω (658Ω MIL) 3.0V GND ≤ 5 ns 90% 10% 90% 10% ≤ 5 ns (a) Normal Load Equivalent to: (b) High Z Load THÉVENIN EQUIVALENT RTH 200Ω (250Ω MIL) OUTPUT 2.0V(1.9VMIL) Test Load for -35 through -55 speeds R1250 Ω 5V OUTPUT 30pF INCLUDING JIG AND SCOPE 5V OUTPUT R2167 Ω 5 pF INCLUDING JIG AND SCOPE R2167 Ω R1 250Ω (c) Normal Load Equivalent to: THÉVENIN EQUIVALENT RTH 100Ω 2.0V (d) High Z Load OUTPUT Switching Characteristics Over the Operating Range [1,3,4] 7C261-20 7C263-20 7C264-20 Parameter tAA tHZCS1 tHZCS2 tACS1 tACS2 tPU tPD Description Address to Output Valid Chip Select Inactive to High Z (7C263 and 7C264) Chip Select Inactive to High Z (7C261) Chip Select Active to Output Valid (7C263 and 7C264) Chip Select Active to Output Valid (7C261) Chip Select Active to Power-Up (7C261) Chip Select Inactive to Power-Down (7C261) 0 20 Min. Max. 20 12 20 12 20 0 25 7C261-25 7C263-25 7C264-25 Min. Max. 25 12 25 12 25 0 35 7C261-35 7C263-35 7C264-35 Min. 35 20 35 20 35 0 45 7C261-45 7C263-45 7C264-45 Max. 45 30 45 30 45 0 55 7C261-55 7C263-55 7C264-55 Min. Max. 55 35 55 35 55 Unit ns ns ns ns ns ns ns Max. Min. Document #: 38-04010 Rev. *B Page 4 of 14 CY7C261 CY7C263/CY7C264 Switching Waveforms[4] tPD 50% tPU 50% VCC SUPPLY CURRENT A0 - A12 ADDRESS CS tAA O0 - O7 tHZCS tACS Erasure Characteristics Wavelengths of light less than 4000 angstroms begin to erase the devices in the windowed package. For this reason, an opaque label should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time. The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating, the exposure time would be approximately 35 minutes. The 7C261 or 7C263 needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage. Operating Modes Read Read is the normal operating mode for programmed device. In this mode, all signals are normal TTL levels. The PROM is addressed with a 13-bit field, a chip select, (active LOW), is applied to the CS pin, and the contents of the addressed location appear on the data out pins. Program, Program Inhibit, Program Verify These modes are entered by placing a high voltage VPP on pin 19, with pins 18 and 20 set to VILP. In this state, pin 21 becomes a latch signal, allowing the upper 5 address bits to be latched into an onboard register, pin 22 becomes an active LOW program (PGM) signal and pin 23 becomes an active LOW verify (VFY) signal. Pins 22 and 23 should never be active LOW at the same time. The PROGRAM mode exists when PGM is LOW, and VFY is HIGH. The verify mode exists when the reverse is true, PGM HIGH and VFY LOW and the program inhibit mode is entered with both PGM and VFY HIGH. Program inhibit is specifically provided to allow data to be placed on and removed from the data pins without conflict Table 1. Mode Selection Pin Function[6, 7] Read or Output Disable Mode Read Output Disable Program Program Inhibit Program Verify Blank Check Program A12 NA A12 A12 VILP VILP VILP VILP A11 VPP A11 A11 VPP VPP VPP VPP A10 LATCH A10 A10 VILP VILP VILP VILP A9 PGM A9 A9 VILP VIHP VIHP VIHP A8 VFY A8 A8 VIHP VIHP VILP VILP CS CS VIL VIH VILP VILP VILP VILP O7–O0 D7–D0 O7–O0 High Z D7–D0 High Z O7–O0 O7–O0 Notes: 6. X = “don’t care” but not to exceed VCC ±5%. 7. Addresses A8-A12 must be latched through lines A0-A4 in programming modes. Document #: 38-04010 Rev. *B Page 5 of 14 CY7C261 CY7C263/CY7C264 DIP/Flatpack Top View A7 A6 A5 A4 /A2 1 A 3/ A 11 A2/A10 A1/A9 A0/A8 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 7C261 17 VCC VFY PGM LATCH CS VPP NA D7 D6 D5 D4 D3 A4/A12 A3/A11 A2/A10 A1/A9 A0/A8 NC D0 LCC/PLCC (Opaque only) Top View VFY PGM LATCH CS VPP NA NC D7 D6 D5 A5 A6 A7 NC VCC GND D1 D2 7C263 16 10 7C264 15 11 12 14 13 4 3 2 1 28 27 26 25 5 24 6 7C261 23 7 22 8 21 9 7C263 20 10 19 11 12 13 14 15 16 17 18 NC D3 D4 Figure 1. Programming Pinouts Programming Information Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. Document #: 38-04010 Rev. *B Page 6 of 14 CY7C261 CY7C263/CY7C264 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 CC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 NORMALIZED ACCESS TIME NORMALIZED I CC 1.2 NORMALI ZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.2 1.0 0.8 0.6 4.0 TA = 25°C f = f MAX 4.5 5.0 5.5 6.0 NORMALIZED I 1.1 1.0 1.0 0.8 0.9 0.6 TA = 25°C 0.4 4.0 4.5 5.0 5.5 6.0 0.8 –55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA) NORMALIZED ACCESS TIME vs. TEMPERATURE NORMALIZED ACCESS TIME 1.6 1.4 1.2 1.0 0.8 0.6 –55 OUTPUT SOURCE CURRENT vs. VOLTAGE 60 50 DELTA t AA (ns) 40 30 20 10 0 0 1.0 2.0 3.0 4.0 35 30 25 20 15 10 5 0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING VCC = 4.5V TA = 25°C 0 200 400 600 800 1000 25 125 AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) CAPACITANCE (pF) OUTPUT SINK CURRENT (mA) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 175 150 NORMALIZED I CC 125 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25°C 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 NORMALIZED SUPPLY CURRENT vs. CYCLE PERIOD VCC = 5.5V TA = 25°C 0 25 50 75 100 OUTPUT VOLTAGE (V) CYCLE PERIOD (ns) Document #: 38-04010 Rev. *B Page 7 of 14 CY7C261 CY7C263/CY7C264 ] Ordering Information Speed (ns) 20 25 Ordering Code CY7C261-20PC CY7C261-20WC CY7C261-25JC CY7C261-25PC CY7C261-25WMB 35 CY7C261-35PC CY7C261-35WC CY7C261-35WMB 45 CY7C261-45PC CY7C261-45WC CY7C261-45WMB 55 20 CY7C261-55WC CY7C263-20JC CY7C263-20PC CY7C263-20WC 25 CY7C263-25JC CY7C263-25PC CY7C263-25WC CY7C263-25DMB CY7C263-25QMB CY7C263-25WMB 35 CY7C263-35PC CY7C263-35WC CY7C263-35WMB 45 55 CY7C263-45WMB CY7C263-55JI CY7C263-55PC CY7C263-55WMB 35 45 55 CY7C264-35PC CY7C264-45WC CY7C264-45WMB CY7C264-55WC Package Name P13 W14 J64 P13 W14 P13 W14 W14 P13 W14 W14 W14 J64 P13 W14 J64 P13 W14 D14 Q64 W14 P13 W14 W14 W14 J64 P13 W14 P11 W12 W12 W12 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Windowed CerDIP 224-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 28-Pin Windowed Leadless Chip Carrier 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (600-Mil) Molded DIP 24-Lead (600-Mil) Windowed CerDIP 24-Lead (600-Mil) Windowed CerDIP 24-Lead (600-Mil) Windowed CerDIP Military Military Industrial Commercial Military Commercial Commercial Military Commercial Commercial Military Commercial Military Commercial Commercial Military Commercial Military Commercial Commercial Operating Range Commercial Document #: 38-04010 Rev. *B Page 8 of 14 CY7C261 CY7C263/CY7C264 MILITARY SPECIFICATION Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC ISB[8] 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Subgroups Switching Characteristics Parameter tAA tACS1[9] tACS2[8] Notes: 8. 7C261 only. 9. 7C263 and 7C264 only. Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Document #: 38-04010 Rev. *B Page 9 of 14 CY7C261 CY7C263/CY7C264 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A 51-80031 28-Lead Plastic Leaded Chip Carrier J64 51-85001-A Document #: 38-04010 Rev. *B Page 10 of 14 CY7C261 CY7C263/CY7C264 Package Diagrams (continued) 24-Lead (600-Mil) Molded DIP P11 51-85016-A 24-Lead (300-Mil) Molded DIP P13/P13A 51-85013-A Document #: 38-04010 Rev. *B Page 11 of 14 CY7C261 CY7C263/CY7C264 Package Diagrams (continued) 28-Pin Windowed Leadless Chip Carrier Q64 MIL–STD–1835 C–4 51-80102 Document #: 38-04010 Rev. *B Page 12 of 14 CY7C261 CY7C263/CY7C264 Package Diagrams (continued) 24-Lead (600-Mil) Windowed CerDIP W12 MIL-STD-1835 D-3 Config. A 51-80089-** 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D-9 Config. A 51-80086 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-04010 Rev. *B Page 13 of 14 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C261 CY7C263/CY7C264 Document History Page Document Title: CY7C261 CY7C263/CY7C264 8K x 8 Power Switched and Reprogrammable PROM Document Number: 38-04010 REV. ** *A *B ) ECN NO. 113866 118895 122251 Issue Date 3/6/02 10/09/02 12/28/02 Orig. of Change DSG GBI RBI Description of Change Change from Spec number: 38-00005 to 38-04010 Update Ordering Information Add power up requirements to Maximum Ratings information Document #: 38-04010 Rev. *B Page 14 of 14