CY7C276-25JC

THIS SPEC IS OBSOLETE Spec No: 38-04004 Spec Title: CY7C276 16K x 16 Reprogrammable PROM Sunset Owner: P Indira (PCI) Replaced by: None [+] [+] Feedback 1CY7C276 CY7C276 16K x 16 Reprogrammable PROM Features • 0.8-micron CMOS for optimum speed/power • High speed — 25-ns access time • 16-bit-wide words • Three programmable chip selects • Programmable output enable • 44-pin PLCC and 44-pin LCC packages • 100% reprogrammable in windowed packages • TTL-compatible I/O • Capable of withstanding greater than 2001V static discharge Functional Description The CY7C276 is a high-performance 16K-word by 16-bit CMOS PROM. It is available in a 44-pin PLCC and a 44-pin LCC packages, and is 100% reprogrammable in windowed packages. The memory cells utilize proven EPROM floating gate technology and word-wide programming algorithms. The CY7C276 allows the user to independently program the polarity of each chip select (CS2−CS0). This provides on-chip decoding of up to eight banks of PROM. The polarity of the asynchronous output enable pin (OE) is also programmable. In order to read the CY7C276, all three chip selects must be active and OE must be asserted. The contents of the memory location addressed by the address lines (A13−A0) will become available on the output lines (D15−D0). The data will remain on the outputs until the address changes or the outputs are disabled. Logic Block Diagram A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 16K x 16 PROGRAMMABLE ARRAY D14 Pin Configuration LCC/PLCC/CLCC Top View D13 D14 D15 VSS VCC VSS VCC VSS D12 D11 D10 D9 D8 VSS VCC D7 D6 D5 D4 D12 D11 D10 D9 D8 D7 D6 D5 D4 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 CS 2 CS 1 CS 0 A13 A12 A11 A10 A9 VSS VSS A8 A7 A6 A5 D13 CS0 CS1 CS2 D3 CS DECODE D2 D1 D0 OE Cypress Semiconductor Corporation Document #: 38-04004 Rev. *C • 3901 North First Street • San Jose D 3 D 2 D 1 D 0 OE V SS A 0 A 1 A 2 A 3 A 4 • CA 95134 • 408-943-2600 Revised September 22, 2006 [+] Feedback CY7C276 Selection Guide CY7C276-25 Maximum Access Time Maximum Operating Current Commercial 25 175 CY7C276-30 30 175 Unit ns mA Maximum Ratings[1] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to+150°C Ambient Temperature with Power Applied............................................. –55°C to+125°C Supply Voltage to Ground Potential ................ –0.5V to+7.0V DC Voltage Applied to Outputs in High Z State ................................................ –0.5V to+7.0V DC Input Voltage............................................ –3.0V to +7.0V DC Program Voltage .................................................... 13.0V UV Erasure................................................... 7258 Wsec/cm2 Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ±10% Electrical Characteristics[2, 3] CY7C276-25 CY7C276-30 Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Input Clamp Diode Voltage Output Leakage Current Output Short Circuit Current Power Supply Current VCC = Max., VOL < VOUT < VOH, Output Disabled VCC = Max., VOUT = 0.0V[4] VCC = Max., IOUT = 0.0 mA Com’l Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA (6.0 mA Mil) Guaranteed Input Logical HIGH Voltage for All Inputs Guaranteed Input Logical LOW Voltage for All Inputs GND < VIN < VCC 2.0 –3.0 –10 –40 –20 Min. 2.4 0.4 VCC 0.8 +10 +40 –90 175 Max. Unit V V V V µA µA µA mA mA Note 2 Capacitance[2] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF Notes: 1. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. See Introduction to CMOS PROMs in this Data Book for general information on testing. 3. See the last page of this specification for Group A subgroup testing information. 4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document #: 38-04004 Rev. *C Page 2 of 10 [+] Feedback CY7C276 AC Test Loads and Waveforms R1 500Ω (658Ω MIL) R2 333Ω (403Ω MIL) R1 500Ω (658Ω MIL) R2 333Ω (403Ω MIL) 3.0V GND < 3 ns ALL INPUT PULSES 90% 10% 90% 10% < 3 ns 5V OUTPUT 50 pF INCLUDING JIG AND SCOPE 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (a) Normal Load (b) High Z Load Equivalent to: THÉVENIN EQUIVALENT OUTPUT 200Ω (250ΩMIL) 2.0V (1.9V Mil) Switching Characteristics Over the Operating Range[2,3] CY7C276-25 Parameter tAA tCSOV tCSOZ tOEV tOEZ Description Address to Output Data Valid CS Active to Output Valid CS Inactive to High Z Output OE Active to Output Valid OE Inactive to High Z Output Min. Max. 25 13 13 11 11 CY7C276-30 Min. Max. 30 15 15 12 12 Unit ns ns ns ns ns Erasure Characteristics The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure time would be approximately 35 minutes. The CY7C276 needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the EPROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage. Wavelengths of light less than 4000 Angstroms begin to erase the CY7C276 in the windowed package. For this reason, an opaque label should be placed over the window if the EPROM is exposed to sunlight or fluorescent lighting for extended periods of time. Document #: 38-04004 Rev. *C Page 3 of 10 [+] Feedback CY7C276 Switching Waveforms Read Operation Timing Diagram [5] A13 − A0 tAA D15 −D0 ADDR A ADDR B tAA DATA A DATA B Chip Select and Output Enable Timing Diagrams A13− A0 CS2 − CS0 OE ACTIVE HIGH INACTIVE ACTIVE INACTIVE tCSOV D −D0 15 VALID tOEZ tOEV tCSOZ VALID HIGH Z Note: 5. CS2 – CS0, OE assumed active. Architecture Configuration Bits The CY7C276 has four user-programmable options in addition to the reprogrammable data array. For detailed programming information contact your local Cypress representative. The programmable options determine the active polarity for the three chip selects (CS2–CS0) and OE. When these control bits are programmed with a 0 the inputs are active LOW. When these control bits are programmed with a 1 the inputs are active HIGH. Programming Information Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. Document #: 38-04004 Rev. *C Page 4 of 10 [+] Feedback CY7C276 Table 1. Control Word for Architecture Configuration Control Word Control Option OE CS0 CS1 CS2 Bit D0 D12 D13 D14 Programmed Level 0 = Default 1 = Programmed 0 = Default 1 = Programmed 0 = Default 1 = Programmed 0 = Default 1 = Programmed Function OE Active LOW OE Active HIGH CS0 Active LOW CS0 Active HIGH CS1 Active LOW CS1 Active HIGH CS2 Active LOW CS2 Active HIGH Bit Map Programmer Address (Hex) 0000 . . . 3FFF 4000 Data . . . Data Control Word RAM Data Control Word (4000H) D15 D0 X CS2 CS1 CS0 X X X X X X X X 1 X X OE Table 2. Program Mode Table Mode Program Inhibit Program Enable Program Verify VPP VPP VPP VPP PGM VIHP VILP VIHP VFY VIHP VIHP VILP D0−D15 High Z Data Data Table 3. Configuration Mode Table Mode Program Inhibit Program Control Word Verify Control Word VPP VPP VPP VPP PGM VIHP VILP VIHP VFY VIHP VIHP VILP A2 VPP VPP VPP D0−D15 High Z Control Word Control Word D12 D11 D10 D9 D8 VSS VCC D7 D6 D5 D4 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 CY7C276 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 PGM VFY CS 0 A13 A12 A11 A10 A9 VSS VSS A8 A7 A6 A5 Figure 1. Programming Pinout Document #: 38-04004 Rev. *C D 3 D 2 D 1 D 0 OE V SS A 0 A 1 A 2 A 3 A 4 D13 D14 D15 VSS VPP VSS VCC VSS Page 5 of 10 [+] Feedback CY7C276 Typical DC and AC Characteristics NORMALIZED I CC vs. tCKA CYCLE 1.2 NORMALIZED I CC (mA) NORMALIZED ICC (mA) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 100 200 300 400 500 TA = 25°C VCC= 5.5V 1.4 TA = 25°C f = fMAX NORMALIZED ICC vs. OUTPUT VOLTAGE NORMALIZED ACCESS TIME NORMALIZED t CKA vs. TEMPERATURE 1.4 1.2 V = 4.5V CC 1.2 1.0 0.8 1.0 0.8 0.6 −55 0.6 4 ACCESS TIME (ns) NORMALIZED t CKA vs. SUPPLY VOLTAGE NORMALIZED ACCESS TIME 1.2 DELTA ACCESS TIME (ns) 1.1 25 20 15 10 5 0 0 4.5 5 5.5 OUTPUT VOLTAGE (V) 6 25 125 AMBIENT TEMPERATURE (°C) NORMALIZED I CC vs. AMBIENT TEMPERATURE 1.1 NORMALIZED I CC (mA) VCC= 5.6V tCKA CHANGE vs. OUTPUT LOADING TA = 25°C VCC = 4.5V 1.05 1.0 0.95 0.90 0.85 −55 25 1.0 0.9 TA =90°C 0.9 4.0 4.5 5.0 5.5 6.0 200 400 600 800 1000 125 SUPPLYVOLTAGE(V) NORMALIZED t OEV vs. TEMPERATURE OUTPUT LOAD (pF) AMBIENT TEMPERATURE (°C) tOEV CHANGE vs. OUTPUT LOADING 1.2 NORMALIZED t OEV (ns) 1.1 35 30 DELTA t OEV (ns) 25 20 15 10 5 1.0 VCC = 4.5V 0.9 0 −55 VCC = 4.5V TA = 25°C 0 200 400 600 800 1000 25 TEMPERATURE(°C) 125 0 OUTPUT LOAD (pF) Document #: 38-04004 Rev. *C Page 6 of 10 [+] Feedback CY7C276 Ordering Information Speed (ns) 25 Ordering Code CY7C276-25HC CY7C276-25JC 30 CY7C276-30JC Package Name H67 J67 J67 Package Type 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier Commercial Operating Range Commercial MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter tAA tCSOV tOEV Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Document #: 38-04004 Rev. *C Page 7 of 10 [+] Feedback CY7C276 Package Diagrams 44-Pin Windowed Leaded Chip Carrier H67 51-80079-** Document #: 38-04004 Rev. *C Page 8 of 10 [+] Feedback CY7C276 Package Diagrams (continued) 44-Lead Plastic Leaded Chip Carrier J67 51-85003-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-04004 Rev. *C Page 9 of 10 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. [+] Feedback CY7C276 Document History Page Document Title: CY7C276 16K x 16 Reprogrammable PROM Document Number: 38-04004 REV. ** *A *B *C ECN NO. 113860 118900 122245 504720 Issue Date 03/06/02 10/09/02 12/27/02 See ECN Orig. of Change DSG GBI RBI PCI Description of Change Change from Spec number: 38-00183 to 38-04004 Update ordering information Add power up requirements to Maximum Ratings information Obsolete Device. Datasheet to be removed from Cypress web and spec. system Document #: 38-04004 Rev. *C Page 10 of 10 [+] Feedback