CY7C331-20PC

1CY7C331 fax id: 6016 CY7C331 Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent (product term) set, reset, and clock inputs on all registers — Asynchronous bypass capability on all registers under product term control (r = s = 1) — Global or local output enable on three-state I/O • • • • • — Feedback from either register to the array 192 product terms with variable distribution to macrocells 13 inputs, 12 feedback I/O pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inputs High speed: 20 ns maximum tPD Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin PLCC • Low power — 90 mA typical ICC quiescent — 180 mA ICC maximum — UV-erasable and reprogrammable — Programming and operation 100% testable Functional Description The CY7C331 is the most versatile PLD available for asynchronous designs. Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability. For increased utility, XOR gates are provided at the D-inputs and the product term allocation per flip-flop is variably distributed. I/O Resources Pins 1 through 7 and 9 through 14 serve as array inputs; pin 14 may also be used as a global output enable for the I/O macrocell three-state outputs. Pins 15 through 20 and 23 through 28 are connected to I/O macrocells and may be managed as inputs or outputs depending on the configuration and the macrocell OE terms. Logic Block Diagram OE/I12 14 I11 13 I10 12 I9 11 I8 10 I7 9 GND 8 I6 7 I5 6 I4 5 I3 4 I2 3 I1 2 I0 1 PROGRAMMABLE AND ARRAY (192x62) 4 12 6 10 8 8 8 8 10 6 12 4 15 I/O11 16 I/O10 17 I/O9 18 I/O8 19 I/O7 20 I/O6 21 GND 22 VCC 23 I/O5 24 I/O4 25 I/O3 26 I/O2 27 I/O1 28 I/O0 C331–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 1989 – Revised December 1992 CY7C331 Selection Guide Generic Part Number CY7C331–20 CY7C331–25 CY7C331–30 CY7C331–40 ICC1 (mA) Com’l 130 120 160 150 150 Mil 20 25 25 30 40 tPD (ns) Com’l Mil Com’l 12 12 15 15 20 tS (ns) Mil 20 25 25 30 40 tCO (ns) Com’l Mil Pin Configuration TopView I3 I2 I1 I0 I/O0 I/O1 I/O2 I/O Resources (continued) It should be noted that there are two ground connections (pins 8 and 21) which, together with VCC (pin 22) are located centrally on the package. The reason for this placement and dual-ground structure is to minimize the ground-loop noise when the outputs are driving simultaneously into a heavy capacitive load. I/O3 I/O4 I/O5 VCC GND I/O6 I/O7 C331–2 4 3 2 1 2827 26 I4 I5 I6 GND I7 I8 I9 5 6 7 8 9 10 11 25 24 23 22 21 20 19 121314 1516 1718 10 11 OE/I12 I/O11 I/O10 I/O9 The CY7C331 has twelve I/O macrocells (see Figure 1). Each macrocell has two D-type flip-flops. One is fed from the array, and one from the I/O pin. For each flip-flop there are three dedicated product terms driving the R, S, and clock inputs, respectively. Each macrocell has one input to the array and for each pair of macrocells there is one shared input to the array. The macrocell input to the array may be configured to come from the ‘Q’ output of either flip-flop. TO PIN 14 (INVERTED) OE PTERM I/O8 OUT SET PTERM C0 OUTPUT FLIP–FLOP S DQ QB R 1S 0 O TO I/O PIN OUT CLK PTERM OUT RESET PTERM IN CLK PTERM IN SET PTERM IN RESET PTERM XOR PTERM OR PTERMS TO INPUT BUFFER TO SHARED INPUT MUX I I 0 1S O O 0 S1 C1 O S1 0 S QD QB R INPUT FLIP–FLOP C331–3 TO PIN 14 (INVERTED) Figure 1. I/O Macrocell 2 CY7C331 I/O Resources (continued) The D-type flip-flop that is fed from the array (i.e., the state flip-flop) has a logical XOR function on its input that combines a single product term with a sum(OR) of a number of product terms. The single product term is used to set the polarity of the output or to implement toggling (by including the current output in the product term). The R and S inputs to the flip-flops override the current setting of the ‘Q’ output. The S input sets ‘Q’ true and the R input resets ‘Q’ (sets it false). If both R and S are asserted (true) at once, then the output will follow the input (‘Q’ = ‘D’) (see Table 1). Table 1. RS Truth Table R 1 0 1 S 0 1 1 Q 0 1 D OUTPUT FROM LOGIC ARRAY FEEDBACK TO LOGIC ARRAY Q– OUTPUT FROM INPUT REGISTEROF I/O MACROCELLA MACROCELL A I/O PIN INPUT TO LOGIC ARRAY MACRO– 0 CELL INPUT 1 MUX C3 OUTPUT FROM LOGIC ARRAY FEEDBACK TO LOGIC ARRAY Q– OUTPUT FROM INPUT REGISTEROF I/O MACROCELLB MACROCELL B I/O PIN C331–4 Figure 2. Shared Input Multiplexer The CY7C331 is configured by three arrays of configuration bits (C0, C1, C2). For each macrocell, there is one C0 bit and one C1 bit. For each pair of macrocells there is one C2 bit. There are twelve C0 bits, one for each macrocell. If C0 is programmed for a macrocell, then the three-state enable (OE) will be controlled by pin 14 (the global OE). If C0 is not programmed, then the OE product term for that macrocell will be used. There are twelve C1 bits, one for each macrocell. The C1 bit selects inputs for the product term (PT) array from either the state register (if the bit is unprogrammed) or the input register (if the bit is programmed). There are six C2 bits, providing one C2 bit for each pair of macrocells. The C2 bit controls the shared input multiplexer; if the C2 bit is not programmed, then the input to the product term array comes from the upper macrocell (A). If the C2 bit is programmed, then the input comes from the lower macrocell (B). The timing diagrams for the CY7C331 cover state register, input register, and various combinational delays. Since internal clocks are the outputs of product terms, all timing is from the transition of the inputs causing the clock transition. Shared Input Multiplexer The input associated with each pair of macrocells may be configured by the shared input multiplexer to come from either macrocell; the ‘Q’ output of the flip-flop coming from the I/O pin is used as the input signal source (see Figure 2). Product Term Distribution The product terms are distributed to the macrocells such that 32 product terms are distributed between two adjacent macrocells. The pairing of macrocells is the same as it is for the shared inputs. Eight of the product terms are used in each macrocell for set, reset, clock, output enable, and the upper part of the XOR gate. This leaves 16 product terms per pair of macrocells to be divided between the sum-of-products inputs to the two state registers. The following table shows the I/O pin pairing for shared inputs, and the product term (PT) allocation to macrocells associated with the I/O pins (see Table 2). Table 2. . Product Term Distribution Macrocell 0 1 2 3 4 5 6 7 8 9 10 11 Pin Number 28 27 26 25 24 23 20 19 18 17 16 15 Product Terms 4 12 6 10 8 8 8 8 10 6 12 4 3 CY7C331 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied .............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 8 or 21) .................................... –0.5V to +7.0V DC Input Voltage............................................ –3.0V to +7.0V Output Current into Outputs (LOW) .............................12 mA Static Discharge Voltage............................................>1500V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA DC Programming Voltage ............................................ 13.0 V Operating Range Range Commercial Military [1] Ambient Temperature 0°C to +70°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[2] Parameter VOH VOL VIH VIL IIX IOZ ISC ICC1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Output Short Circuit Current[4] Standby Power Supply Current Test Conditions VCC = Min., VIN = VIH or VIL IOH = –3.2 mA (Com’l), IOH = –2 mA (Mil) VCC = Min., VIN = VIH or VIL IOL = 12 mA (Com’l), IOL = 8 mA (Mil) Guaranteed HIGH Input, all Inputs[3] Guaranteed LOW Input, all VSS < VIN < VCC, VCC = Max. VSS < VOUT < VCC, VCC = Max. VCC = Max., VOUT = 0.5V[5] Com’l –20 Com’l –25 Mil –25 Mil –30, –40 ICC2 Power Supply Current at Frequency[4, 6] VCC = Max., Outputs Disabled (in High Z State) Device Operating at fMAX External (fMAX1) Com’l Mil Inputs[3] –10 –40 –30 2.2 0.8 +10 +40 –90 130 120 160 150 180 200 mA mA Min. 2.4 0.5 Max. Unit V V V V µA µA mA mA VCC = Max., VIN = GND, Outputs Open Capacitance[4] Parameter CIN COUT Description Input Capacitance Test Conditions VIN = 2.0V at f = 1 MHz Max. 10 Unit pF Output Capacitance VOUT = 2.0V at f = 1 MHz 10 pF Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Because these input signals are controlled by product terms, active input polarity may be of either polarity. Internal active input polarity has been shown for clarity. 4 CY7C331 AC Test Loads and Waveforms R1 313 Ω (470Ω Mil) 5V OUTPUT 50pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 208 Ω (319Ω Mil) R1 313 Ω (470Ω Mil) 3.0V 90% 5 pF R2 208 Ω GND (319Ω Mil) ≤ 5 ns 10% 90% 10% ≤ 5 ns ALL INPUT PULSES INCLUDING JIG AND SCOPE (a) (b) C331–5 C331–6 to: THÉVENIN EQUIVALENT (Commercial) 125Ω Equivalent 2.00V=V thc OUTPUT C331–7 Equivalent to: THÉVENIN EQUIVALENT (Military) 190Ω 2.02V=V thm OUTPUT C331–8 Parameter t PXZ(– ) VX 1.5V V OH Output Waveform—Measurement Level 0.5V VX 0.5V V OL VX C331–10 C331–9 t PXZ(+) 2.6V t PZX(+) V thc VX 0.5V V OH C331–11 t PZX(– ) V thc VX 0.5V V OL C331–12 t ER(– ) 1.5V V OH 0.5V VX VX C331–13 t ER(+) 2.6V V OL V thc VX 0.5V C331–14 t EA(+) 0.5V V OH C331–15 t EA(– ) V thc VX 0.5V (c) Test Waveforms and Measurement Levels V OL C331–16 Switching Characteristics Over the Operating Range[2] ) Commercial –20 Parameter tPD tICO tIOH tIS tIH tIAR Description Input to Output Propagation Delay[7] Input Register Clock to Output Delay[8] Clock[8] Clock[8] 5 2 11 35 Output Data Stable Time from Input Input Register Hold Time from Input Min. Max. 20 35 5 2 13 40 Min. –25 Max. 25 40 Unit ns ns ns ns ns ns Input or Feedback Set-Up Time to Input Register Clock[8] Input to Input Register Asynchronous Reset Delay[8] 5 CY7C331 Switching Characteristics Over the Operating Range[2] (continued) Commercial –20 Parameter tIRW tIRR tIAS tISW tISR tWH tWL fMAX1 fMAX2 tIOH–tIH33X tCO tOH tS tH tOAR tORW tORR tOAS tOSW tOSR tEA tER tPZX tPXZ fMAX3 fMAX4 tOH–tIH33X fMAX5 Description Input Register Reset Width [4, 8] –25 Min. 40 40 35 40 40 40 15 15 23.8 25.0 0 20 25 3 12 8 20 25 25 25 20 25 25 25 25 25 20 20 25 25 20 20 27.0 33.3 0 30.0 Max. Unit ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns MHz Min. 35 35 [8] Max. Input Register Reset Recovery Time[4, 8] Input to Input Register Asynchronous Set Delay Input Register Set Width [4, 8] 35 35 12 12 27.0 28.5 0 [8, 9, 10] Input Register Set Recovery Time[4, 8] Input and Output Clock Width HIGH Input and Output Clock Width LOW[8, 9, 10] Maximum Frequency with Feedback in Input Registered Mode (1/(tICO + tIS))[11] Maximum Frequency Data Path in Input Registered Mode (Lowest of 1/tICO, 1/(tWH + tWL), or 1/(tIS + tIH)[8] Output Data Stable from Input Clock Minus Input Register Input Hold Time for 7C335[12, 13] Output Register Clock to Output Delay[9] Output Data Stable Time from Output Clock[9] Clock[9] Delay[9] 3 12 8 20 20 Output Register Input Set-Up Time to Output Output Register Input Hold Time from Output Clock[9] Input to Output Register Asynchronous Reset Output Register Reset Width[9] Delay[9] Output Register Reset Recovery Time[9] Input to Output Register Asynchronous Set Output Register Set Width[9] Output Register Set Recovery Input to Output Enable Time[9] Delay[14, 15] Delay[14, 15] Delay[14, 15] 20 20 Input to Output Disable Delay[14, 15] Pin 14 to Output Enable Pin 14 to Output Disable Maximum Frequency with Feedback in Output Registered Mode (1/(tCO + tS))[16, 17] Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/tCO, 1/(tWH + tWL), or 1/(tS + tH))[9] Output Data Stable from Output Clock Minus Input Register Input Hold Time for 7C335[13, 18] Maximum Frequency Pipelined Mode[10, 17] 31.2 41.6 0 35.0 Notes: 7. Refer to Figure 3, configuration 1. 8. Refer to Figure 3, configuration 2. 9. Refer to Figure 3, configuration 3. 10. Refer to Figure 3, configuration 6. 11. Refer to Figure 3, configuration 7. 12. Refer to Figure 3, configuration 9. 13. This specification is intended to guarantee interface compatibility of the other members of the CY7C330 family with the CY7C331. This specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product. 14. Part (a) of AC Test Loads and Waveforms used for all parameters except tPZXI, tPXZI, tPZX, and tPXZ, which use part (b). Part (c) shows the test waveforms and measurement levels. 15. Refer to Figure 3, configuration 4. 16. Refer to Figure 3, configuration 8. 17. This specification is intended to guarantee that a state machine configuration created with internal or external feedback can be operated with output register and input register clocks controlled by the same source. These parameters are tested by periodic sampling of production product. 6 CY7C331 Switching Characteristics Over the Operating Range[2] (continued) Military –25 Parameter tPD tICO tIOH tIS tIH tIAR tIRW tIRR tIAS tISW tISR tWH tWL fMAX1 fMAX2 tIOH–tIH33X tCO tOH tS tH tOAR tORW tORR tOAS tOSW tOSR tEA tER tPZX tPXZ fMAX3 fMAX4 tOH–tIH33X fMAX5 Description Input to Output Propagation Delay [7] –30 Min. Max. 30 50 5 5 15 45 50 50 50 45 50 50 50 20 20 18.1 20.0 0 25 30 3 15 10 25 30 30 30 25 30 30 30 25 25 20 20 30 30 25 25 22.2 25.0 0 23.5 40 40 40 40 3 20 12 65 65 25 25 65 65 5 5 20 25 45 –40 Min. Max. 40 65 Unit ns ns ns ns ns 65 ns ns ns 65 ns ns ns ns ns MHz MHz ns 40 ns ns ns ns 40 ns ns ns 40 ns ns ns 40 40 35 35 16.6 20.0 0 18.5 ns ns ns ns MHz MHz ns MHz Min. Max. Input Register Clock to Output Delay[4, 8] Output Data Stable Time from Input Clock [4, 8] 5 Clock[8] 5 13 45 Input or Feedback Set-Up Time to Input Register Input Register Hold Time from Input Clock Input Register Reset Width [8] [4, 8] Input to Input Register Asynchronous Reset Delay[4, 8] Input Register Reset Recovery Input Register Set Width[8] Time[8] Low[8, 9, 10] Time[8] 45 45 45 15 15 20.0 22.2 0 Input to Input Register Asynchronous Set Delay[8] Input Register Set Recovery Input and Output Clock Width High[8, 9, 10] Input and Output Clock Width Maximum frequency with Feedback in Input Registered Mode (1/(tICO + tIS))[11] Maximum frequency Data Path in Input Registered Mode (Lowest of 1/tICO, 1/(tWH + tWL), or 1/(tIS + tIH)[8] Output Data Stable from Input Clock Minus Input Register Input Hold Time for 7C335[12, 13] Output Register Clock to Output Delay[9] Output Data Stable Time from Output Clock[9] Clock[9] Delay[9] 14.2 15.3 0 3 15 10 25 Output Register Input Set-Up Time to Output Clock[9] Output Register Input Hold Time from Output Input to Output Register Asynchronous Reset Output Register Reset Width[9] Output Register Reset Recovery Output Register Set Width[9] Delay[14, 15] Delay[14, 15] Delay[14, 15] Time[9] Delay[9] Input to Output Register Asynchronous Set Output Register Set Recovery Time[9] Input to Output Enable Input to Output Disable 25 25 25 Pin 14 to Output Enable Delay[14, 15] Pin 14 to Output Disable Maximum Frequency with Feedback in Output Registered Mode )1/(tCO + tS)[16, 17] Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/tCO, 1/(tWH + tWL), or 1/(tS + tH)[9] Output Data Stable from Output Clock Minus Input Register Input Hold Time for 7C335[13, 18] Maximum Frequency Pipelined Mode[10, 17] 25.0 33.3 0 28.0 Note: 18. Refer to Figure 3, configuration 10. 7 CY7C331 Switching Waveforms INPUT OR I/O PIN tIS I/O INPUT REGISTER CLOCK [6] OUTPUT REGISTER CLOCK[6] tWH tWL tIH tS [20] tH tWH tWL tIOH[19] OUTPUT tICO[19] SET AND RESET INPUTS[6] tORR, tOSR[22] tPD[21] [21] tOH tCO tORR, tOSR[23] tORR, tOSR[21] C331–17 OE PRODUCT TERM INPUT [6, 15] PIN 14 AS OE[24] tPXZ OUTPUT OUTPUT REGISTER RESET INPUT [6,9] OUTPUT REGISTER CLOCK [6,9] OUTPUT REGISTER SET INPUT [6,9] I/O INPUT REGISTER RESET INPUT [6,8] I/O INPUT REGISTER CLOCK[6,8] I/O INPUT REGISTER SET INPUT [6,8] tER tEA tPZX tOAR tORW tORR tOAS tOSR tOSW tIAR tIRW tIRR tIAS tISW C331–18 tISR Notes: 19. Output register is set in Transparent mode. Output register set and reset inputs are in a HIGH state. 20. Dedicated input or input register set in Transparent mode. Input register set and reset inputs are in a HIGH state. 21. Combinatorial Mode. Reset and set inputs of the input and output registers should remain in a HIGH state at least until the output responds at tPD. When returning set and reset inputs to a LOW state, one of these signals should go LOW a minimum of tOSR (set input) or tORR (reset input) prior to the other. This guarantees predictable register states upon exit from Combinatorial mode. 22. When entering the Combinatorial mode, input and output register set and reset inputs must be stable in a HIGH state a minimum of tISR or tIRR and tOSR or tORR respectively prior to application of logic input signals. 23. When returning to the input and/or output Registered mode, register set and reset inputs must be stable in a LOW state a minimum of tISR or tIRR and tOSR or tORR respectively prior to the application of the register clock input. 24. Refer to Figure 3, configuration 5. 8 CY7C331 CONFIGURATION 1 PIN INPUT OR I/O PIN PRODUCT TERM ARRAY OE PIN I/O PIN PIN UNREGISTERED INPUT OR I/O PIN CLOCK/S/R INPUT INPUT REGISTER D Q RESET OE PRODUCT TERM ARRAY PIN I/O PIN CONFIGURATION 2 PIN I/O PIN ONL Y OUTPUT REGISTER PIN UNREGISTERED INPUT OR I/O PIN CLOCK/S/R INPUT UNREGISTERED INPUT OR I/O PIN PRODUCT TERM ARRAY D Q OE SET RESET PIN I/O PIN CONFIGURATION 3 PIN PIN CONFIGURATION 4 INPUT OR I/O PIN PIN INPUT OR I/O PIN PRODUCT TERM ARRAY OUTPUT ENABLE PIN I/O PIN PIN 14 CONFIGURATION 5 INPUT OR I/O PIN PIN INPUT OR I/O PIN PRODUCT TERM ARRAY OUTPUT ENABLE PIN I/O PIN INPUT REGISTER I/O PIN ONL Y PIN DATA INPUT D Q CLOCK PRODUCT TERM ARRAY OUTPUT REGISTER I/O PIN PIN OE CLOCK DATA OUTPUT CONFIGURATION 6 UNREGISTERED INPUT OR I/O PIN PIN CLOCK INPUT C331–19 Figure 3. Timing Configurations . 9 CY7C331 DATA INPUT PIN INPUT REGISTER D Q CLOCK PIN DATA OUTPUT CLOCK INPUT OE CLOCK PRODUCT TERM ARRAY Q OE PIN CONFIGURATION 7 D INPUT REGISTER PIN OUTPUT REGISTER PIN DATA INPUT D OUTPUT REGISTER PIN DATA OUTPUT OE CLOCK Q D PRODUCT TERM ARRAY CLOCK Q Q OE PIN CONFIGURATION 8 PIN CLOCK INPUT C331–20 331 INPUT REGISTER D Q OE PIN PIN 330 OR 332 INPUT REGISTER D Q CONFIGURATION 9 PRODUCT TERM ARRAY CLOCK 331 OUTPUT REGISTER D Q OE PIN PIN 330 OR 332 INPUT REGISTER D Q CONFIGURATION 10 PRODUCT TERM ARRAY C331–21 CLOCK Figure 3. Timing Configurations (continued) 10 CY7C331 CY7C331 Logic Diagram (Upper Half) 11 CY7C331 CY7C331 Logic Diagram (Lower Half) 12 CY7C331 Ordering Information ICC1 (mA) 130 tPD (ns) 20 tS (ns) 12 tCO (ns) 20 Ordering Code CY7C331–20HC CY7C331–20JC CY7C331–20PC CY7C331–20WC 160 25 15 25 CY7C331–25DMB CY7C331–25HMB CY7C331–25LMB CY7C331–25QMB CY7C331–25TMB CY7C331–25WMB 120 25 12 25 CY7C331–25HC CY7C331–25JC CY7C331–25PC CY7C331–25WC 150 30 15 30 CY7C331–30DMB CY7C331–30HMB CY7C331–30LMB CY7C331–30QMB CY7C331–30TMB CY7C331–30WMB 150 40 20 40 CY7C331–40DMB CY7C331–40HMB CY7C331–40LMB CY7C331–40QMB CY7C331–40TMB CY7C331–40WMB Package Name H64 J64 P21 W22 D22 H64 L64 Q64 T74 W22 H64 J64 P21 W22 D22 H64 L64 Q64 T74 W22 D22 H64 L64 Q64 T74 W22 Package Type 28-Pin Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Pin Windowed Leaded Chip Carrier 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead Windowed Cerpack 28-Lead (300-Mil) Windowed CerDIP 28-Pin Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Pin Windowed Leaded Chip Carrier 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead Windowed Cerpack 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Pin Windowed Leaded Chip Carrier 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead Windowed Cerpack 28-Lead (300-Mil) Windowed CerDIP Military Military Commercial Military Operating Range Commercial 13 CY7C331 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC1 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tIS tIH tWH tWL tCO tPD tIAR tIAS tPXZ tPZX tER tEA tS tH Switching Characteristics Parameter Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Document #: 38–00066–D 14 CY7C331 Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D– 15Config.A 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C–4 28-Pin Windowed Leadless Chip Carrier Q64 MIL-STD-1835 C–4 15 CY7C331 Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier 16 CY7C331 Package Diagrams (continued) 28-Lead (300-Mil) Molded DIP P21 28-Lead Windowed Cerpack T74 17 CY7C331 Package Diagrams (continued) 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D– 15Config.A © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.