CY7C344B_05

USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C344B 32-Macrocell MAX® EPLD Features • High-performance, high-density replacement for TTL, 74HC, and custom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins • Advanced 0.65-micron CMOS EPROM technology to increase performance • 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344B LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 “buried” registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB. The speed and density of the CY7C344B makes it a natural for all types of applications. With just this one device, the designer can implement complex state machines, registered logic, and combinatorial “glue” logic, without using multiple chips. This architectural flexibility allows the CY7C344B to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three. Functional Description Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344B represents the Logic Block Diagram [1] 15(22) 15(23) 27(6) 28(7) INPUT INPUT INPUT INPUT INPUT INPUT INPUT 1(8) 13(20) 14(21) Pin Configurations HLCC Top View I/O I/O I/O VCC GND I/O I/O 4 3 2 1 28 27 26 I/O I/O I O C O N T R O L I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3(10) 4(11) 5(12) 6(13) 9(16) 10(17) 11(18) 12(19) 17(24) 18(25) 19(26) 20(27) 23(2) 24(3) 25(4) 26(5) INPUT INPUT/CLK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT I/O INPUT INPUT INPUT INPUT/CLK I/O I/O 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O INPUT INPUT INPUT INPUT I/O 12 13 14 1516 1718 V CC GND I/O I/O I/O I/O INPUT/CLK 2(9) MACROCELL 2 MACROCELL 4 MACROCELL 6 MACROCELL 8 MACROCELL 10 MACROCELL 12 MACROCELL 14 MACROCELL 16 MACROCELL 18 MACROCELL 20 MACROCELL 22 MACROCELL 24 MACROCELL 26 MACROCELL 28 MACROCELL 30 MACROCELL 32 G L O B A L B U S MACROCELL 1 MACROCELL 3 MACROCELL 5 MACROCELL 7 MACROCELL 9 MACROCELL 11 MACROCELL 13 MACROCELL 15 MACROCELL 17 MACROCELL 19 MACROCELL 21 MACROCELL 23 MACROCELL 25 MACROCELL 27 MACROCELL 29 MACROCELL 31 CerDIP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INPUT INPUT I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT 64 EXPANDER PRODUCT TERM ARRAY 32 Selection Guide 7C344B-15 Maximum Access Time Note: 1. Number in () refers to J-leaded packages. 7C344B-20 20 7C344B-25 25 I/O Unit ns 15 Cypress Semiconductor Corporation Document #: 38-03036 Rev. *D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 6, 2005 USE ULTRA37000™ FOR ALL NEW DESIGNS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +135°C Ambient Temperature with Power Applied..............................................-65°C to +135°C Maximum Junction Temperature (Under Bias)............. 150°C Supply Voltage to Ground Potential[2] ............ –2.0V to +7.0V CY7C344B DC Output Current, per Pin[2] ...................–25 mA to +25 mA DC Input Voltage[2] .........................................–2.0V to +7.0V Operating Range[3] Range Commercial Industrial Ambient Temperature –0°C to +70°C –40°C to +85°C VCC 5V ±5% 5V ±10% Electrical Characteristics Over the Operating Range Parameter VCC VOH VOL VIH VIL IIX IOZ tR tF Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Recommended Input Rise Time Recommended Input Fall Time GND ≤ VIN ≤ VCC VO = VCC or GND Test Conditions Maximum VCC rise time is 10 ms IOH = – 4.0 mA IOL = 8 mA DC[4] DC[4] 2.0 –0.3 –10 –40 Min. 4.75(4.5) 2.4 0.45 VCC+0.3 0.8 +10 +40 100 100 Max. 5.25(5.5) Unit V V V V V µA µA ns ns Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V, f = 1.0 MHz VOUT = 0V, f = 1.0 MHz Max. 10 12 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 50 pF INCLUDING JIGAND SCOPE Equivalent to: R2 250Ω R1 464Ω 5V OUTPUT 5 pF R2 250Ω R1 464Ω 3.0V GND ≤ 6 ns ALL INPUT PULSES 90% 10% tf 90% 10% tR tF ≤ 6 ns (a) (b) THÉVENIN EQUIVALENT (commercial) 163Ω OUTPUT 1.75V Notes: 2. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 4. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. Document #: 38-03036 Rev. *D Page 2 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS Design Recommendations Operation of the devices described herein with conditions above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C344B contains circuitry to protect device pins from high-static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled. CY7C344B are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. Typical ICC vs. fMAX 240 ICC ACTIVE (mA) Typ. 180 VCC =5.0V Room Temp. 120 60 Timing Considerations Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. When calculating synchronous frequencies, use tSU if all inputs are on the input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tSU) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz MAXIMUM FREQUENCY Output Drive Current IO OUTPUT CURRENT (mA) TYPICAL 250 IOL 200 150 100 50 IOH VCC =5.0V Room Temp. 0 1 2 3 4 5 VO OUTPUT VOLTAGE (V) Document #: 38-03036 Rev. *D Page 3 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C344B EXPANDER DELAY t EXP LOGIC ARRAY CONTROLDELAY tCLR tLAC tPRE INPUT DELAY tIN LOGIC ARRAY tRSU DELAY tRH tLAD SYSTEM CLOCK DELAYtICS I/O I/O DELAY tIO CLOCK DELAY tIC REGISTER OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX INPUT I/O FEEDBACK DELAY tFD Figure 1. CY7C344B Timing Model External Synchronous Switching Characteristics Over Operating Range 7C344B-15 Parameter tPD1 tPD2 tSU tCO1 tH tWH tWL fMAX tCNT tODH fCNT Description Dedicated Input to Combinatorial Output Delay[5] Com’l/Ind I/O Input to Combinatorial Output Global Clock Set-up Time Synchronous Clock Input to Output Delay[5] Input Hold Time from Synchronous Clock Input Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Maximum Register Toggle Frequency[6] Minimum Global Clock Period Output Data Hold Time After Clock Maximum Internal Global Clock Frequency[7] Delay[5] Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind 1 76.9 0 6 6 83.3 13 1 62.5 9 10 0 7 7 71.4 16 1 50 Min. Max. 15 15 12 12 0 8 8 62.5 20 7C344B-20 Min. Max. 20 20 15 15 7C344B-25 Min. Max. 25 25 Unit ns ns ns ns ns ns ns MHz ns ns MHz Notes: 5. C1 = 35 pF 6. The fMAX values represent the highest frequency for pipeline data. 7. This parameter is measured with a 32-bit counter programmed into each LAB. Document #: 38-03036 Rev. *D Page 4 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS External Asynchronous Switching Characteristics Over Operating Range 7C344B-15 Parameter tACO1 tAS1 tAH tAWH tAWL tACNT fACNT Description Asynchronous Clock Input to Output Delay [5] CY7C344B 7C344B-20 Min. 6 6 7 9 Max. 18 7C344B-25 Min. 8 8 9 11 Max. 22 Unit ns ns ns ns ns 20 50 ns MHz Min. Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind [7] Max. 15 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time Asynchronous Clock Input LOW Time [8] [8] 5 5 6 7 13 76.9 Minimum Internal Array Clock Frequency Maximum Internal Array Clock Frequency 16 62.5 Com’l/Ind Typical Internal Switching Characteristics Over Operating Range 7C344B-15 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tIC tICS tFD tPRE tCLR Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay[5] Output Buffer Enable Output Buffer Disable Delay[5] Delay[5] Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l /Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind Com’l/Ind 4 5 1 1 1 7 2 1 5 5 Min. Max. 3 3 8 7 4 4 7 7 4 8 1 1 1 8 2 1 6 6 7C344B-20 Min. Max. 5 5 10 10 4 4 7 7 5 10 1 1 1 10 3 1 9 9 7C344B-25 Min. Max. 7 7 15 13 4 4 7 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow-Through Latch Delay Register Delay Transparent Mode Delay Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Note: 8. This parameter is measured with a positive-edge-triggered clock at the register. For the negative-edge clocking, the tACH and tACL parameter must be swapped. Document #: 38-03036 Rev. *D Page 5 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT CY7C344B External Synchronous tWH tWL SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER DATA FROM LOGIC ARRAY tSU tCO1 tH REGISTERED OUTPUTS External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAH tAWH tAWL Internal Synchronous CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE tRD tOD Document #: 38-03036 Rev. *D Page 6 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS Switching Waveforms (continued) Internal Combinatorial INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT tIN CY7C344B tCOMB OUTPUT PIN tOD Internal Asynchronous tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY REGISTER OUTPUT TO ANOTHER LAB tFD tCLR,tPRE tFD tAWH tAWL tF tIC tRSU tRH tPIA Document #: 38-03036 Rev. *D Page 7 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS Switching Waveforms (continued) Internal Synchronous CY7C344B SYSTEM CL OCK PIN tIN SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY tICS tRSU tRH Ordering Information Speed (ns) 15 Ordering Code CY7C344B-15HC/HI CY7C344B-15JC/JI CY7C344B-15PC/PI CY7C344B-15WC/WI 20 CY7C344B-20HC/HI CY7C344B-20JC/JI CY7C344B-20PC/PI CY7C344B-20WC/WI 25 CY7C344B-25HC/HI CY7C344B-25JC/JI CY7C344B-25PC/PI Package Name H64 J64 P21 W22 H64 J64 P21 W22 H64 J64 P21 Package Type 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP Commercial/Industrial Commercial/Industrial Operating Range Commercial/Industrial Document #: 38-03036 Rev. *D Page 8 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams 28-Pin Windowed Leaded Chip Carrier H64 CY7C344B 51-80077-** Document #: 38-03036 Rev. *D Page 9 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 28-Lead Plastic Leaded Chip Carrier J64 CY7C344B 51-85001-*A 28-Lead (300-Mil) PDIP P21 SEE LEAD END OPTION 14 1 DIMENSIONS IN INCHES [MM] MIN. MAX. 0.260[6.60] 0.295[7.49] REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 15 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 3° MIN. 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] 0.310[7.87] 0.385[9.78] SEE LEAD END OPTION LEAD END OPTION (LEAD #1, 14, 15 & 28) 51-85014-*D Document #: 38-03036 Rev. *D Page 10 of 12 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config. A CY7C344B 51-80087-** MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-03036 Rev. *D Page 11 of 12 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS Document History Page Document Title: CY7C344 32-Macrocell MAX® EPLD Document Number: 38-03036 REV. ** *A *B *C *D ECN NO. 106381 122235 213375 238565 373715 Issue Date 06/15/01 12/28/02 See ECN See ECN See ECN Orig. of Change SZV RBI FSG KKV PCX Description of Change Change from Spec #: 38-00860 to 38-03036 CY7C344B Power-up requirements added to Operating Range Information Added note to title page: “Use Ultra37000 For All New Designs” Minor change: fixed error in part number in header Corrected header information Document #: 38-03036 Rev. *D Page 12 of 12