CY7C346B

USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C346B 128-Macrocell MAX® EPLD Features • 128 macrocells in eight logic array blocks (LABs) • 20 dedicated inputs, up to 64 bidirectional I/O pins • Programmable interconnect array • Advanced 0.65-micron CMOS technology to increase performance • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 128 macrocells in the CY7C346B are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected through the programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C346B allow it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C346B allows the replacement of over 50 TTL CY7C346B. By replacing large amounts of logic, the CY7C346B reduces board space, part count, and increases system reliability. Functional Description The CY7C346B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. Logic Block Diagram . 1 (C7) [16] . 78 (A10) [9] . 79 (B9) [10] 80 (A9) [11] . 83 (A8) [14] . 84 (B7) [15] . 2 (A7) [17] . 5 (C6) [20] . 6 (A5) [21] . 7 (B5) [22] . INPUT/CLK ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT SYSTEM CLOCK LAB A MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 MACROCELL 121–128 LAB G MACROCELL 104 MACROCELL 103 MACROCELL 102 MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 P I A MACROCELL 105–112 LAB F MACROCELL 88 MACROCELL 87 MACROCELL 86 MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 86–96 LAB E 49 50 51 52 53 54 55 56 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 72 71 70 69 68 67 66 65 [58] [57] [56] [55] [54] [53] [52] [51] (M4) NC (N3) NC (M3) 55 (N2) 54 (M2) 53 (N1) 52 (L2) 51 (M1) 50 INPUT [59] INPUT [60] INPUT [61] INPUT [64] INPUT [65] INPUT [66] INPUT [67] INPUT [70] INPUT [71] INPUT [72] (N4) (M5) (N5) (N6) (M7) (L7) (N7) (L8) (N9) (M9) . . . . . . . . . . 36 37 38 41 42 43 44 47 48 49 8 (B13) [1] 9 (C12) [2] 10 (A13) [3] 11 (B12) [4] 12 (A12) [5] 13 (11) [6] NC (A11) [7] NC (B10) [8] 1 2 3 4 5 6 7 8 [100] (C13) NC [99] (D12) NC [98] (D13) 77 [97] (E12) 76 [96] (E13) 75 [95] (F11) 74 [92] (G13) 73 [91] (G11) 72 MACROCELL 9–16 LAB B MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 14 (A4) 15 (B4) 16 (A3) 17 (A2) 18 (B3) 21 (A1) NC (B2) NC (B1) [23] [24] [25] [26] [27] [28] [29] [30] 17 18 19 20 21 22 23 24 [90] [89] [86] [85] [84] [83] [82] [81] (G12) NC (H13) NC (J13) 71 (J12) 70 (K13) 69 (K12) 68 (L13) 67 (L12) 64 MACROCELL 25–32 LAB C MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 22 (C2) [31] 25 (C1) [32] 26 (D2) [33] 27 (D1) [34] 28 (E2) [35] 29 (E1) [36] NC (F1) [39] NC (G2) [40] 33 34 35 36 37 38 39 40 [80] [79] [78] [77] [76] [75] [74] [73] (M13) (M12) (N13) (M11) (N12) (N11) (M10) (N10) NC NC 63 60 59 58 57 56 MACROCELL 41–48 LAB D 30 (G3) [41] 31 (G1) [42] 32 (H3) [45] 33 (J1) [46] 34 (J2) [47] 35 (K1) [48] NC (K2) [49] NC (L1) [50] MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 57– 64 3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) 16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [18, 19, 43, 44, 68, 69, 93, 94] [12, 13, 37, 38, 62, 63, 87, 88] VCC GND MACROCELL 73– 80 () – PERTAIN TO 100-PIN PGA PACKAGE [ ] – PERTAIN TO 100-PIN PQFP PACKAGE Cypress Semiconductor Corporation Document #: 38-03037 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 9, 2004 USE ULTRA37000™ FOR ALL NEW DESIGNS Selection Guide 7C346B-25 Maximum Access Time 25 7C346B-35 35 CY7C346B Unit ns Pin Configurations INPUT/CLK PLCC/CLCC Top View INPUT INPUT INPUT V CC V CC INPUT INPUT INPUT INPUT INPUT INPUT GND GND PGA Bottom View I/O I/O I/O I/O I/O I/O I/O 11 10 9 8 7 6 I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O N M L K J H G F E D C B A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INP I/O INP INP INP VCC INP INP GND INP VCC INP GND INP INP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O 13 VCC VCC I/O I/O I/O I/O 7C346B GND GND I/O I/O I/O VCC I/O I/O INP INP GND /CLK I/O I/O I/O 11 I/O I/O I/O 12 I/O GND GND I/O I/O I/O I/O I/O 1 I/O I/O I/O I/O I/O 2 I/O I/O 3 I/O I/O 4 7C346B INP VCC INP GND INP INP VCC INP 5 6 7 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 INPUT GND GND INPUT INPUT INPUT INPUT INPUT INPUT V CC V CC INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O INP INP INP 8 9 10 Document #: 38-03037 Rev. *C Page 2 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Pin Configurations (continued) PQFP Top View GND VCC GND CC CY7C346B I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT GND GND INPUT INPUT INPUT/CLK INPUT VCC VCC INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 V 87 86 85 84 83 I/O 82 81 80 79 78 77 76 75 74 73 72 71 70 I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT VCC VCC INPUT INPUT INPUT INPUT GND GND INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O CY7C346B 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Document #: 38-03037 Rev. *C VCC VCC I/O I/O Page 3 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Logic Array Blocks There are eight logic array blocks in the CY7C346B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. CY7C346B Externally, the CY7C346B provides 20 dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that may be individually configured for input, output, or bidirectional data flow. Programmable Interconnect Array The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tCLR tLAC tPRE INPUT DELAY tIN LOGIC ARRAY DELAY tLAD tRSU tRH REGISTER OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX INPUT SYSTEM CLOCK DELAY tICS CLOCK DELAY tIC FEEDBACK DELAY tFD PIA DELAY tPIA I/O DELAY tIO C346B–9 Figure 1. CY7C346B Internal Timing Model Design Recommendations Operation of the devices described herein with conditions above those listed in the “Maximum Ratings” section of this datasheet may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C346B contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must Document #: 38-03037 Rev. *C be connected directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have. Design Security The CY7C346B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other Page 4 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS program data, may be reset simply by erasing the entire device. The CY7C346B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages. CY7C346B Timing Considerations Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from straight input pin. When calculating synchronous frequencies, use tSU if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tSU) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on the dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. Typical ICC vs. fMAX 400 ICC ACTIVE (mA) Typ. 300 VCC = 5.0V Room Temp. 200 100 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz MAXIMUM FREQUENCY Output Drive Current IO OUTPUT CURRENT (mA) TYPICAL 250 IOL 200 150 100 IOH 50 VCC = 5.0V Room Temp. 0 1 2 3 4 5 VO OUTPUT VOLTAGE (V) Document #: 38-03037 Rev. *C Page 5 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to+135°C Ambient Temperature with Power Applied............................................. –65°C to+135°C Maximum Junction Temperature (under bias).................................................................. 150°C Supply Voltage to Ground Potential[1] ............. –2.0V to+7.0V CY7C346B DC Output Current per Pin[1] .................... –25 mA to+25 mA DC Input Voltage[1] ........................................–2.0V to + 7.0V Operating Range[2] Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 5% 5V ± 10% Electrical Characteristics Over the Operating Range Parameter VCC VOH VOL VIH VIL IIX IOZ tR tF Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Current Output Leakage Current Recommended Input Rise Time Recommended Input Fall Time VI = VCC or ground VO = VCC or ground Test Conditions Maximum VCC rise time is 10 ms IOH = –4 mA DC [3] Min. 4.75(4.5) 2.4 Max. 5.25(5.5) 0.45 Unit V V V V V µA µA ns ns IOL = 8 mA DC[3] 2.0 –0.3 –10 –40 VCC +0.3 0.8 +10 +40 100 100 Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V, f = 1.0 MHz VOUT = 0V, f = 1.0 MHz Max. 10 20 Unit pF pF AC Test Loads and Waveforms R1 464 Ω 5V OUTPUT 50 pF INCLUDING JIG AND SCOPE Equivalent to: R2 250Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 250Ω 3.0V 10% GND ≤ 6 ns R1 464 Ω ALL INPUT PULSES 90% 90% 10% ≤ 6 ns (a) (b) THÉVENIN EQUIVALENT (commercial/military) 163Ω OUTPUT 1.75V Notes: 1. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 3. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. Document #: 38-03037 Rev. *C Page 6 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS 7C346B-25 Parameter tPD1 tPD2 tSU tCO1 tH tWH tWL fMAX tCNT tODH fCNT Description Dedicated Input to Combinatorial Output Delay[4] I/O Input to Combinatorial Output Global Clock Set-Up Time Synchronous Clock Input to Output Delay[4] Input Hold Time from Synchronous Clock Input Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Maximum Register Toggle Frequency[5] Minimum Global Clock Period Output Data Hold Time After Clock Maximum Internal Global Clock Frequency[6] 2 50 0 8 8 62.5 20 2 33.3 Delay[4] 15 14 0 12.5 12.5 40 Min. Max. 25 40 25 CY7C346B Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range 7C346B-35 Min. Max. 35 55 20 Unit ns ns ns ns ns ns ns MHz 30 ns ns MHz Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range 7C346B-25 Parameter tACO1 tAS1 tAH tAWH tAWL tACNT fACNT Description Asynchronous Clock Input to Output Delay[4] 5 6 11 9 20 50 33.3 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input LOW Time[7] Minimum Internal Array Clock Frequency Maximum Internal Array Clock Frequency[6] Min. Max. 25 10 10 16 14 30 7C346B-35 Min. Max. 35 Unit ns ns ns ns ns ns MHz Commercial and Industrial Internal Switching Characteristics Over Operating Range 7C346B-25 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay[4] Output Buffer Enable Delay[4] Output Buffer Disable Delay[8] Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow Through Latch Delay 6 4 3 Min. Max. 5 6 12 12 10 5 10 10 12 8 4 7C346B-35 Min. Max. 11 11 20 14 13 6 13 13 Unit ns ns ns ns ns ns ns ns ns ns ns tRD Register Delay 1 2 ns Notes: 4. C1 = 35 pF. 5. The fMAX values represent the highest frequency for pipeline data. 6. This parameter is measured with a 16-bit counter programmed into each LAB. 7. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped. 8. C1 = 5 pF. Document #: 38-03037 Rev. *C Page 7 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS 7C346B-25 Parameter tCOMB tIC tICS tFD tPRE tCLR tPIA Description Transparent Mode Delay Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Programmable Interconnect Array Delay Time Min. Max. 3 14 3 1 5 5 14 CY7C346B 7C346B-35 Min. Max. 4 16 1 2 7 7 20 Unit ns ns ns ns ns ns ns Commercial and Industrial Internal Switching Characteristics Over Operating Range (continued) Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT External Synchronous tWH tWL SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER DATA FROM LOGIC ARRAY tSU tH tCO1 REGISTERED OUTPUTS External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAH tAWH tAWL Document #: 38-03037 Rev. *C Page 8 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Switching Waveforms (continued) Internal Combinatorial tIN INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT CY7C346B LOGIC ARRAY OUTPUT tCOMB OUTPUT PIN tOD Internal Asynchronous tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB tFD tCLR,tPRE tFD tAWH tAWL tF tIC tRSU tRH Document #: 38-03037 Rev. *C Page 9 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Switching Waveforms (continued) Internal Synchronous CY7C346B SYSTEM CL OCK PIN tIN SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY tICS tRSU tRH Internal Synchronous CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE tRD tOD Ordering Information Speed (ns) 25 Ordering Code CY7C346B-25HC/HI CY7C346B-25JC/JI CY7C346B-25NC/NI CY7C346B-25RC/RI 35 CY7C346B-35HC/HI CY7C346B-35JC/JI CY7C346B-35NC/NI CY7C346B-35RC/RI Package Name H84 J83 N100 R100 H84 J83 N100 R100 Package Type 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Pin Grid Array 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Pin Grid Array Commercial/Industrial Operating Range Commercial/Industrial Document #: 38-03037 Rev. *C Page 10 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams 84-leaded Windowed Leaded Chip Carrier H84 CY7C346B 51-80081-** Document #: 38-03037 Rev. *C Page 11 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 84-lead Plastic Leaded Chip Carrier J83 CY7C346B 51-85006-*A Document #: 38-03037 Rev. *C Page 12 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 100-Lead Plastic Quad Flatpack N100 CY7C346B 51-85052-*A Document #: 38-03037 Rev. *C Page 13 of 15 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 100-pin Windowed Ceramic Pin Grid Array R100 100-pin CY7C346B 51-80010-*C MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-03037 Rev. *C Page 14 of 15 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS Document History Page Document Title: CY7C346B 128-Macrocell Max® EPLD Document Number: 38-03037 REV. ** *A *B *C ECN NO. 106460 113615 122236 213375 Issue Date 07/11/01 04/11/02 12/28/02 See ECN Orig. of Change SZV OOR RBI FSG Description of Change Change from Spec Number: 38-00861 to 38-03037 PGA diagram dimensions were updated CY7C346B Power up requirements added to Operating Range Information Added note to title page: “Use Ultra37000 For All New Designs” Document #: 38-03037 Rev. *C Page 15 of 15