CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K x 9
Synchronous FIFOs
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9
Synchronous FIFOs
Features
■
High speed, low power, First-In First-Out (FIFO) memories
❐ 64 × 9 (CY7C4421)
❐ 256 × 9 (CY7C4201)
❐ 512 × 9 (CY7C4211)
❐ 1K × 9 (CY7C4221)
❐ 2K × 9 (CY7C4231)
❐ 4K × 9 (CY7C4241)
❐ 8K × 9 (CY7C4251)
■
Pin-compatible and functionally equivalent to IDT72421,
72201, 72211, 72221, 72231, and 72241
■
Pb-free Packages Available
Functional Description
■
High speed 100 MHz operation (10 ns read/write cycle time)
■
Low power (ICC = 35 mA)
■
Fully asynchronous and simultaneous read and write operation
■
Empty, Full, and Programmable Almost Empty and Almost Full
status flags
■
TTL-compatible
■
Expandable in width
■
Output Enable (OE) pin
■
Independent read and write enable pins
■
Center power and ground pins for reduced noise
■
Width-expansion capability
■
Space saving 7 mm × 7 mm 32-pin TQFP
The CY7C42X1 are high speed, low power FIFO memories with
clocked read and write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high speed data acquisition, multiprocessor interfaces,
and communications buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a free-running clock (WCLK) and two write-enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1,
WEN2/LD is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the CY7C42X1 has
an output enable pin (OE). The Read (RCLK) and Write (WCLK)
clocks can be tied together for single-clock operation or the two
clocks can run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic to
direct the flow of data.
D0 - 8
Logic Block Diagram
INPUT
REGISTER
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
Write
CONTROL
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
Write
POINTER
RS
EF
PAE
PAF
FF
Read
POINTER
8k x 9
RESET
LOGIC
THREE-STATE
OUTPUT REGISTER
Read
CONTROL
OE
Q0 - 8
Cypress Semiconductor Corporation
Document #: 38-06016 Rev. *D
•
198 Champion Court
RCLK REN1 REN2
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 4, 2010
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Contents
Features .............................................................................. 1
Functional Description ...................................................... 1
Logic Block Diagram ......................................................... 1
Contents ............................................................................. 2
Selection Guide ................................................................. 3
Pin Configuration .............................................................. 3
Functional Description ...................................................... 5
Architecture ....................................................................... 5
Resetting the FIFO ............................................................. 5
FIFO Operation .................................................................. 5
Programming ..................................................................... 5
Programmable Flag (PAE, PAF) Operation ................. 7
Width Expansion Configuration ....................................... 8
Flag Operation ................................................................... 8
Full Flag ........................................................................ 8
Empty Flag ................................................................... 8
Maximum Ratings[4] ........................................................... 9
Document #: 38-06016 Rev. *D
Operating Range ................................................................ 9
Electrical Characteristics Over the Operating Range ...... 9
Capacitance[9] ................................................................... 9
Switching Characteristics Over the Operating Range .. 10
Switching Waveforms ...................................................... 11
Typical AC and DC Characteristics ................................ 17
256 x 9 Synchronous FIFO ......................................... 18
1K x 9 Synchronous FIFO ........................................... 18
2K x 9 Synchronous FIFO ........................................... 18
4K x 9 Synchronous FIFO ........................................... 18
8K x 9 Synchronous FIFO ........................................... 18
Package Diagrams ............................................................ 19
Document History Page ................................................... 20
Sales, Solutions, and Legal Information ........................ 20
Worldwide Sales and Design Support ......................... 20
Products ...................................................................... 20
PSoC Solutions ...........................................................20
Page 2 of 20
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Selection Guide
Description
Maximum Frequency
-10
-15
-25
Unit
100
66.7
40
MHz
Maximum Access Time
8
10
15
ns
Minimum Cycle Time
10
15
25
ns
Minimum Data or Enable Setup
3
4
6
ns
Minimum Data or Enable Hold
0.5
1
1
ns
8
10
15
ns
Commercial
35
35
35
ICC1
Industrial
40
40
40
Maximum Flag Delay
Active Power Supply Current
CY7C4421
CY7C4201
CY7C4211
CY7C4221
CY7C4231
CY7C4241
CY7C4251
64 × 9
256 × 9
512 × 9
1K × 9
2K × 9
4K × 9
8K × 9
Density
Pin Configuration
Figure 1. Pin Diagram
D2
D3
D2
D3
D4
D5
D6
D7
D8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
9 10 11 12 13 14 15 16
OE
EF
PAF
PAE
GND
REN1
RCLK
REN2
1
2
3
4
5
6
7
8
Q3
Q4
D1
D0
Q2
RS
WEN1
WCLK
WEN2/LD
V CC
Q8
Q7
Q6
Q5
FF
Q0
Q1
4 3 2 1 32 3130
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
14151617 181920
EF
FF
Q0
Q1
Q2
Q3
Q4
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
D4
D5
D6
D7
D8
RS
TQFP
Top View
PLCC
Top View
Table 1. Pin Definitions
Pin
Name
I/O
Description
D0–8
Data Inputs
I
Data inputs for 9-bit bus.
Q0–8
Data Outputs
O
Data outputs for 9-bit bus.
WEN1
Write Enable 1
I
The only write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD Dual
Mode Pin
Write Enable 2
I
Load
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data is not written into the
FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD
is held LOW to write or read the programmable flag offsets.
REN1, REN2
Read Enable
Inputs
I
Enables device for read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and
the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
Document #: 38-06016 Rev. *D
Page 3 of 20
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Table 1. Pin Definitions (continued)
I/O
Description
RCLK
Pin
Read Clock
Name
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
Document #: 38-06016 Rev. *D
Page 4 of 20
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Functional Description
maintains the data of the last valid read on its Q0–8 outputs even
after additional reads occur.
The CY7C42X1 provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are
programmable to single word granularity. The programmable
flags default to Empty – 7 and Full – 7.
Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1) is
LOW, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every Write clock (WCLK).
Data is stored is the RAM array sequentially and independently
of any on-going read operation.
The flags are synchronous - they change state relative to either
the Read clock (RCLK) or the Write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle.
All configurations are fabricated using advanced 0.65μ N-Well
CMOS technology. Input ESD protection is greater than 2001V,
and latch up is prevented by the use of guard rings.
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals (RCLK, WCLK, REN1,
REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
During power up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q0–8) go LOW tRSF
after the rising edge of RS. For the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW. All flags are guaranteed to be valid tRSF
after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D0–8 pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory is
presented on the Q0–8 outputs. New data is presented on each
rising edge of RCLK while REN1 and REN2 are active. REN1
and REN2 must set up tENS before RCLK for it to be a valid read
function. WEN1 and WEN2 must occur tENS before WCLK for it
to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW), data
in the output register is available to the Q0–8 outputs after tOE.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
Document #: 38-06016 Rev. *D
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows depth expansion. If Write
Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS =
LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every Write clock (WCLK).
Data is stored in the RAM array sequentially and independently
of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset least
significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again. Figure 2 shows the registers sizes and default
values for the various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW, a
write operation stores data in the next offset register in
sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK Read register contents
to the data outputs. Writes and reads should not be preformed
simultaneously on the offset registers.
Page 5 of 20
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Figure 2. Offset Register Location and Default Values
64 × 9
8
256 × 9
0
6 5
8
Empty Offset (LSB) Reg.
Default Value = 007h
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
512 × 9
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
1K × 9
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
1
8
0
7
(MSB)
0
8
0
6 5
8
Full Offset (LSB) Reg
Default Value = 007h
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
0
8
Full Offset (LSB) Reg
Default Value = 007h
0
1
8
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
0
8
(MSB)
00
0
7
2K × 9
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
8
(MSB)
000
Document #: 38-06016 Rev. *D
8
Full Offset (LSB) Reg
Default Value = 007h
0
2
(MSB)
00000
0
7
8
(MSB)
0000
0
7
Full Offset (LSB) Reg
Default Value = 007h
0
3
0
4
8
(MSB)
0000
0
7
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
3
8
(MSB)
000
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
2
8
(MSB)
00
8K × 9
4K × 9
0
7
0
1
8
(MSB)
0
8
0
1
8
8
0
4
(MSB)
00000
Page 6 of 20
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Programmable Flag (PAE, PAF) Operation
(512 – m), CY7C4221 (1K – m), CY7C4231 (2K – m),
CY7C4241 (4K – m), and CY7C4251 (8K – m). PAF is set HIGH
by the LOW-to-HIGH transition of WCLK when the number of
available memory locations is greater than m.
Whether the flag offset registers are programmed as described
in Table 2 or the default values are used, the programmable
almost-empty flag (PAE) and programmable almost-full flag
(PAF) states are determined by their corresponding offset
registers and the difference between the read and write pointers.
Table 2. Writing the Offset Registers
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred to
as n and determines the operation of PAE. PAE is synchronized
to the LOW-to-HIGH transition of RCLK by one flip-flop and is
LOW when the FIFO contains n or fewer unread words. PAE is
set HIGH by the LOW-to-HIGH transition of RCLK when the
FIFO contains (n + 1) or greater unread words.
WCLK[1]
LD
WEN
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
The number formed by the full offset least significant bit register
and full offset most significant bit register is referred to as m and
determines the operation of PAF. PAE is synchronized to the
LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW
when the number of unread words in the FIFO is greater than or
equal to CY7C4421. (64 – m), CY7C4201 (256 – m), CY7C4211
Selection
Table 3. Status Flags
Number of Words in FIFO
CY7C4421
CY7C4201
CY7C4211
FF
PAF
PAE
EF
0
0
0
H
H
L
L
1 to n[2]
1 to n[2]
1 to n[2]
H
H
L
H
(n + 1) to 32
(n + 1) to 128
(n + 1) to 256
H
H
H
H
33 to (64 – (m + 1))
129 to (256 – (m + 1))
257 to (512 – (m + 1))
H
H
H
H
H
L
H
H
L
L
H
H
FF
PAF
PAE
EF
(64 –
m)[3] to 63
64
(256 –
m)[3] to 255
(512 –
256
m)[3] to 511
512
Number of Words in FIFO
CY7C4221
CY7C4231
CY7C4241
CY7C4251
0
0
0
0
H
H
L
L
1 to n[2]
1 to n[2]
1 to n[2]
1 to n[2]
H
H
L
H
(n + 1) to 512
(n + 1) to 1024
(n + 1) to 2048
(n + 1) to 4096
H
H
H
H
513 to (1024 – (m + 1))
1025 to (2048 – (m + 1)) 2049 to (4096 – (m + 1)) 4097 to (8192 – (m + 1))
H
H
H
H
H
L
H
H
L
L
H
H
(1024 –
1024
m)[3] to 1023
(2048 –
2048
m)[3] to 2047
(4096 –
4096
m)[3] to 4095
(8192 –
8192
m)[3] to 8191
Notes
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06016 Rev. *D
Page 7 of 20
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Width Expansion Configuration
Flag Operation
Word width may be increased by connecting the corresponding
input controls signals of multiple devices. A composite flag
should be created for each of the end-point status flags (EF and
FF). The partial status flags (PAE and PAF) can be detected from
any one device. Figure 3 demonstrates a 18-bit word width by
using two CY7C42X1s. Any word width can be attained by
adding additional CY7C42X1s.
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) goes LOW when device is full. Write operations are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK - it is
exclusively updated by each rising edge of WCLK.
When the CY7C42X1 is in a Width Expansion Configuration, the
Read Enable (REN2) control input can be grounded (See
Figure 3). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN1 and REN2. EF is synchronized to RCLK - it is
exclusively updated by each rising edge of RCLK.
Figure 3. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory Used
in a Width Expansion Configuration
RESET (RS)
DATA IN (D) 18
Write
Write
Write
RESET (RS)
9
9
Read CLOCK (RCLK)
CLOCK (WCLK)
Read ENABLE 1 (REN1)
ENABLE 1 (WEN1)
OUTPUT ENABLE (OE)
ENABLE 2/LOAD
(WEN2/LD)
CY7C42X1
PROGRAMMABLE (PAF)
CY7C42X1
EF EMPTY FLAG (EF) #2
EF
FULL FLAG (FF) # 1
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
FF
FF
9
FULL FLAG (FF) # 2
DATA OUT (Q)
18
9
Read Enable 2 (REN2)
Document #: 38-06016 Rev. *D
Read Enable 2 (REN2)
Page 8 of 20
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Maximum Ratings[4]
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................... –65°C to +150°C
Ambient Temperature with
Power Applied .............................................. –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
5V ±10%
–40°C to +85°C
5V ±10%
Commercial
[5]
Industrial
DC Input Voltage ............................................–3.0V to +7.0V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
-10
Min
-15
Max
Max
Min
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
2.2
VCC
VIL
Input LOW Voltage
–3.0
0.8
–3.0
0.8
IIX
Input Leakage
Current
VCC = Max.
–10
+10
–10
+10
–10
IOS[6]
Output Short
Circuit Current
VCC = Max.,
VOUT = GND
–90
IOZL
IOZH
Output OFF,
High-Z Current
OE > VIH,
VSS < VO < VCC
–10
ICC1[7]
Active Power Supply
Current
Commercial
35
Industrial
Average Standby Current
ICC2[8]
2.4
Min
-25
2.4
0.4
2.4
0.4
–90
+10
–10
Unit
Max
V
0.4
V
2.2
VCC
V
–3.0
0.8
V
+10
μA
–90
+10
–10
mA
+10
mA
35
35
mA
40
40
40
mA
Commercial
10
10
10
mA
Industrial
15
15
15
mA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max
Unit
5
pF
7
pF
Notes
4. The voltage on any input or I/O pin cannot exceed the power pin during power up.
5. TA is the “instant on” case temperature.
6. Test no more than one output at a time for not more than one second.
7. Outputs open. Tested at frequency = 20 MHz.
8. All inputs = VCC – 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06016 Rev. *D
Page 9 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Figure 4. AC Test Loads and Waveforms[10, 11]
R1 1.1 KΩ
ALL INPUT PULSES
5V
OUTPUT
3.0V
R2
680Ω
CL
INCLUDING
JIG AND
SCOPE
Equivalent to:
GND
≤ 3 ns
THÉVENIN EQUIVALENT
420Ω
OUTPUT
90%
10%
90%
10%
≤ 3 ns
1.91V
Switching Characteristics Over the Operating Range
Parameter
Description
-10
Min
-15
Max
Min
100
-25
Max
Min
Unit
tS
Clock Cycle Frequency
tA
Data Access Time
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Setup Time
3
4
6
ns
tDH
Data Hold Time
0.5
1
1
ns
tENS
Enable Setup Time
3
4
6
ns
tENH
Enable Hold Time
0.5
1
1
ns
tRS
Reset Pulse Width[12]
10
15
25
ns
tRSS
Reset Setup Time
8
10
15
ns
tRSR
Reset Recovery Time
8
10
15
ns
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low-Z[13]
0
tOE
Output Enable to Output Valid
3
7
3
8
3
12
ns
tOHZ
Output Enable to Output in High-Z[13]
3
7
3
8
3
12
ns
tWFF
Write Clock to Full Flag
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
ns
tSKEW1
Skew Time between Read Clock and Write Clock for
Empty Flag and Full Flag
5
6
10
ns
tSKEW2
Skew Time between Read Clock and Write Clock for
Almost-Empty Flag and Almost-Full Flag
10
15
18
ns
2
8
66.7
Max
2
10
10
2
15
0
40
MHz
15
ns
25
0
ns
ns
Notes
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
Document #: 38-06016 Rev. *D
Page 10 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms
Figure 5. Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D8
tENS
tENH
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
tWFF
tWFF
FF
[14]
tSKEW1
RCLK
REN1,REN2
Figure 6. Read Cycle Timing
tCKL
tCLKH
tCLKL
RCLK
tENS
tENH
REN1,REN2
NO OPERATION
tREF
tREF
EF
tA
Q0 –Q8
VALID DATA
tOLZ
tOHZ
tOE
OE
[15]
tSKEW1
WCLK
WEN1
WEN2
Notes
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
Document #: 38-06016 Rev. *D
Page 11 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Figure 7. Reset Timing[16]
tRS
RS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN1,
REN2
WEN1
WEN2/LD
[17]
tRSF
EF,PAE
tRSF
FF,PAF,
tRSF
OE = 1 [18]
Q0 - Q8
OE = 0
Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t DS
D 0 –D8
D0 (FIRSTVALID Write)
D1
tENS
D2
D3
D4
[19]
tFRL
WEN1
WEN2
(if applicable)
tSKEW1
RCLK
tREF
EF
tA
[]
tA
REN1,
REN2
Q0 –Q8
D0
D1
tOLZ
tOE
OE
Notes
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. Holding WEN2/LD HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the
programmable flag offset registers.
18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK +
tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06016 Rev. *D
Page 12 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Figure 9. Empty Flag Timing
WCLK
tDS
tDS
DATAWRITE2
DATAWRITE1
D0 –D8
tENS
tENH
tENH
tENS
WEN1
WEN2
(if applicable)
tENS
tENH
tFRL
tENS
[19]
tENH
[19]
tFRL
RCLK
tSKEW1
tREF
tREF
tREF
tSKEW1
EF
REN1,
REN2
LOW
OE
tA
Q0 –Q8
DATA IN OUTPUT REGISTER
Document #: 38-06016 Rev. *D
DATA Read
Page 13 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Figure 10. Full Flag Timing
NO Write
NO Write
NO Write
WCLK
tSKEW1[14]
tSKEW1[14]
tDS
DATA Write
DATA Write
D0 –D8
tWFF
tWFF
tWFF
FF
WEN1
WEN2
(if applicable)
RCLK
tENH
REN1,
REN2
OE
tENH
tENS
tENS
LOW
tA
Q0 –Q8
tA
DATA Read
DATA IN OUTPUT REGISTER
NEXT DATA Read
Figure 11. Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLK
tENS tENH
WEN1
WEN2
(if applicable)
tENS tENH
PAE
tSKEW2[21]
Note
22
N + 1 WORDS
INFIFO
tPAE
Note
23
tPAE
RCLK
tENS
tENS tENH
REN1,
REN2
Notes
21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
22. PAE offset = n.
23. If a read is performed on this rising edge of the read clock, there are Empty + (n – 1) words in the FIFO when PAE goes LOW.
Document #: 38-06016 Rev. *D
Page 14 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Figure 12. Programmable Almost Full Flag Timing
Note
24
tCLKL
tCLKH
WCLK
tENS tENH
WEN1
Note
25
WEN2
(if applicable)
tPAF
tENS tENH
PAF
FULL − M WORDS
IN FIFO[26]
FULL − M+1 WORDS
IN FIFO
tSKEW2 [27]
tPAF
RCLK
tENS
tENS tENH
REN1,
REN2
Figure 13. Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
WEN2/LD
tENS
WEN1
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes
24. If a write is performed on this rising edge of the write clock, there are Full – (m – 1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231,
4096 – m words for CY7C4241, 8192 – m words for CY7C4251.
27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of
RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06016 Rev. *D
Page 15 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Figure 14. Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
WEN2/LD
tENS
PAF OFFSET
MSB
REN1,
REN2
tA
Q0 –Q8
Document #: 38-06016 Rev. *D
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
Page 16 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Typical AC and DC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.20
1.2
1.0
VIN = 3.0V
TA = 25°C
f = 100 MHz
0.8
0.6
4
4.5
5
5.5
1.10
VIN = 3.0V
VCC = 5.0V
f = 100 MHz
1.10
1.00
0.90
SUPPLY VOLTAGE (V)
25
125
0.60
0
1.0
0.9
0.8
4.5
5
5.5
35
25
1
2
3
OUTPUT VOLTAGE (V)
Document #: 38-06016 Rev. *D
4
OUTPUT SINK CURRENT (mA)
45
0
40
1.00
0.75
25
10
VCC = 5.0V
TA = 25°C
0
125
25
AMBIENT TEMPERATURE (°C)
55
100
1.25
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
75
VCC = 5.0V
0.50
−55
6
50
TYPICAL tA CHANGE vs.
OUTPUT LOADING
Delta tA (ns)
1.1
25
FREQUENCY (MHz)
1.50
NORMALIZED tA
NORMALIZED tA
0.80
NORMALIZED tA vs.
AMBIENT TEMPERATURE
1.2
OUTPUT SOURCE CURRENT (mA)
0.90
AMBIENT TEMPERATURE (°C)
NORMALIZED tA vs. SUPPLY
VOLTAGE
4
VCC = 5.0V
TA = 25°C
VIN = 3.0V
1.00
0.70
0.80
−55
6
NORMALIZED ICC
NORMALIZED ICC
NORMALIZED ICC
1.4
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
0
200
400
600
800 1000
CAPACITANCE (pF)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
160
140
120
100
80
60
40
20
0
0
1
2
3
4
OUTPUT VOLTAGE (V)
Page 17 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
256 x 9 Synchronous FIFO
Speed (ns)
15
Ordering Code
Package Name
Package Type
CY7C4201-15JC
J65
32-Pin Plastic Leaded Chip Carrier
CY7C4201-15JXC
J65
32-Pin Pb-free Plastic Leaded Chip Carrier
Operating Range
Commercial
1K x 9 Synchronous FIFO
Speed (ns)
15
Ordering Code
Package Name
Package Type
CY7C4221-15AXC
A32
32-Pin Pb-free Thin Quad Flatpack
CY7C4221-15JXC
J65
32-Pin Pb-free Plastic Leaded Chip Carrier
Operating Range
Commercial
2K x 9 Synchronous FIFO
Speed (ns)
15
Ordering Code
Package Name
Package Type
CY7C4231-15AXC
A32
32-Pin Pb-free Thin Quad Flatpack
CY7C4231-15JXC
J65
32-Pin Pb-free Plastic Leaded Chip Carrier
Operating Range
Commercial
4K x 9 Synchronous FIFO
Speed (ns)
10
15
Ordering Code
Package Name
Package Type
Operating Range
CY7C4241-10AC
A32
32-Pin Thin Quad Flatpack
CY7C4241-10AXC
A32
32-Pin Pb-free Thin Quad Flatpack
Commercial
CY7C4241-10JI
J65
32-Pin Plastic Leaded Chip Carrier
Industrial
CY7C4241-15AC
A32
32-Pin Thin Quad Flatpack
Commercial
CY7C4241-15JC
J65
32-Pin Plastic Leaded Chip Carrier
CY7C4241-15JXC
J65
32-Pin Pb-free Plastic Leaded Chip Carrier
8K x 9 Synchronous FIFO
Speed (ns)
10
15
Ordering Code
Package Name
Package Type
CY7C4251-10AC
A32
32-Pin Thin Quad Flatpack
CY7C4251-10JC
J65
32-Pin Plastic Leaded Chip Carrier
CY7C4251-10JXC
J65
32-Pin Pb-free Plastic Leaded Chip Carrier
CY7C4251-10AI
A32
32-Pin Thin Quad Flatpack
CY7C4251-10AXI
A32
32-Pin Pb-free Thin Quad Flatpack
CY7C4251-15AC
A32
32-Pin Thin Quad Flatpack
CY7C4251-15AXC
A32
32-Pin Pb-free Thin Quad Flatpack
CY7C4251-15JC
J65
32-Pin Plastic Leaded Chip Carrier
CY7C4251-15JXC
J65
32-Pin Pb-free Plastic Leaded Chip Carrier
Document #: 38-06016 Rev. *D
Operating Range
Commercial
Industrial
Commercial
Page 18 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Package Diagrams
Figure 15. 32-Pin Pb-free Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32, 51-85063
9.00±0.25 SQ
7.00±0.10 SQ
32
25
DIMENSIONS ARE IN MILLIMETERS
0.37±0.05
24
1
0° MIN.
R. 0.08 MIN.
0.20 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
8
17
9
16
SEATING PLANE
0.80
B.S.C.
0.25
GAUGE PLANE
R. 0.08 MIN.
0.20 MAX.
0-7°
0.20 MIN.
12°±1°
(8X)
1.20 MAX.
1.00±0.05
0.60±0.15
1.00 REF.
DETAIL
A
0.08
0.20 MAX.
SEE DETAIL
A
51-85063 *C
Figure 16. 32-Pin Pb-free Plastic Leaded Chip Carrier J65, 51-85002
51-85002-*B
Document #: 38-06016 Rev. *D
Page 19 of 20
[+] Feedback
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Document History Page
Document Title: CY7C4421/4201/4211/4221, CY7C4231/4241/4251 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Document Number: 38-06016
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
106477
09/10/01
SZV
Description of Change
Change from Spec number: 38-00419 to 38-06016
*A
110725
03/20/02
FSG
Change Input Leakage current IIX unit from mA to μA (typo)
*B
122268
12/26/02
RBI
Power up requirements added to Maximum Ratings Information
*C
386306
See ECN
ESH
Added Pb-free logo to top of front page
Added CY7C4421-10JXC, CY7C4201-15AXC. CY7C4201-15JXC,
CY7C4211-10AXI, CY7C4211-15AXC, CY7C4211-15JXC,
CY7C4221-15AXC, CY7C4221-15JXC, CY7C4231-15JXC,
CY7C4231-15AXC, CY7C4241-10AXC, CY7C4241-15AXC,
CY7C4241-15JXC, CY7C4251-10JXC, CY7C4251-10AXI,
CY7C4251-15AXC, CY7C4251-15JXC
*D
2863896
01/22/10
VKN/PYRS
Removed inactive/pruned parts from the Ordering Information table
Added Table of Contents
Updated TQFP package diagram
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06016 Rev. *D
Revised February 4, 2010
Page 20 of 20
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