CY7C421-20JXCT

CY7C421512 × 9 Asynchronous FIFO CY7C421 512 × 9 Asynchronous FIFO 512 × 9 Asynchronous FIFO Features Functional Description ■ Asynchronous First-In First-Out (FIFO) Buffer Memories ❐ 512 × 9 (CY7C421) ■ Dual-Ported RAM Cell ■ High Speed 50 MHz Read and Write Independent of Depth and Width ■ Low Operating Power: ICC = 35 mA ■ Empty and Full Flags (Half Full Flag in Standalone) ■ TTL Compatible ■ Retransmit in Standalone ■ Expandable in Width ■ PLCC, 7 × 7 TQFP, 300-Mil Molded SOJ ■ Pb-free Packages Available ■ Pin Compatible and Functionally Equivalent to IDT7201, and AM7201 The CY7C421 is a first-in first-out (FIFO) memory offered in 300-mil wide SOJ, TQFP & PLCC packages and it is 512 words by 9 bits wide. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and empty flags are provided to prevent overflow and underflow. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel. This eliminates the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high impedance state when R is HIGH. A Half Full (HF) output flag that is valid in the standalone and width expansion configurations is provided. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it is activated. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFO to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C421 is fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000 V and latch up is prevented by careful layout and guard rings. For a complete list of related documentation, click here. Selection Guide 512 × 9 -15 -20 Frequency (MHz) 40 33.3 Maximum Access Time (ns) 15 20 ICC1 (mA) 35 35 Cypress Semiconductor Corporation Document Number: 38-06001 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 14, 2016 CY7C421 Logic Block Diagram DATA INPUTS (D0–D 8) W WRITE CONTROL RAM ARRAY 512 x 9 WRITE POINTER READ POINTER THREESTATE BUFFERS DATA OUTPUTS (Q0–Q 8) R RESET LOGIC READ CONTROL FLAG LOGIC XI Document Number: 38-06001 Rev. *K EXPANSION LOGIC MR FL/RT EF FF XO/HF Page 2 of 22 CY7C421 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 Electrical Characteristics ................................................. 6 Electrical Characteristics ................................................. 6 Capacitance ...................................................................... 7 AC Test Loads and Waveforms ....................................... 7 Switching Characteristics ................................................ 8 Switching Waveforms ...................................................... 9 Architecture .................................................................... 13 Dual-Port RAM .......................................................... 13 Resetting the FIFO .................................................... 13 Writing Data to the FIFO ........................................... 13 Reading Data from the FIFO ..................................... 13 Standalone/Width Expansion Modes ........................ 13 Document Number: 38-06001 Rev. *K Depth Expansion Mode ............................................. 13 Use of the Empty and Full Flags ............................... 14 Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagrams .......................................................... 16 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC®Solutions ....................................................... 22 Cypress Developer Community ................................. 22 Technical Support ..................................................... 22 Page 3 of 22 CY7C421 Pin Configurations 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc D4 D5 D6 D7 FL/RT MR EF XO/HF Q7 Q6 Q5 Q4 32 3130 29 28 27 26 25 D1 D0 NC NC XI FF Q0 Q1 1 2 3 4 5 6 7 8 Document Number: 38-06001 Rev. *K 24 23 22 21 20 19 18 17 7C421 D7 FL/RT NC NC MR EF XO/HF Q7 9 10 11 12 13 14 15 16 R Q2 Q3 Q8 GND R Q4 1 2 3 4 5 6 7 7C421 8 9 10 11 12 13 14 Q6 XO/HF Q7 Q6 W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND Q5 D3 D8 W NC Vcc D4 D5 D6 D7 NC FL/RT MR EF Q3 Q8 GND NC R Q4 Q5 D2 D1 D0 XI FF Q0 Q1 NC Q2 4 3 2 1 323130 5 29 6 28 7 27 8 26 7C421 9 25 10 24 11 23 12 22 13 21 14 15 1617 181920 D5 D6 Figure 3. 32-pIn TQFP (Top View) D3 D8 W VCC D4 Figure 2. 28-pin DIP (Top View) D2 Figure 1. 32-pin PLCC/LCC (Top View) Page 4 of 22 CY7C421 Pin Definitions Signal Name Description I/O Function W Write Signal I Write into the FIFO R Read Signal I Read from the FIFO D0–D8 Input Data I Data into the FIFO Q0–Q8 Output Data O Data Out from the FIFO XI Expansion In I XO Expansion Out O Cascaded: Connected to XI of next device Non-Cascaded: Connected to VCC HF Half Full Flag O Half-full flag: When HF is LOW, half of the FIFO is full. FF Full Flag O When FF is LOW, the FIFO is full. EF Empty Flag O When EF is LOW, the FIFO is empty. MR Master Reset I RT Retransmit I Causes FIFO to retransmit the data FL First Load I Width expansion: Connected to VCC Depth expansion: when Gnd indicates that part is first to be loaded all others connected to VCC VCC Power I Voltage Supply GND Ground I Ground Document Number: 38-06001 Rev. *K Cascaded: Connected to XO of pervious device Non-Cascaded: Connected to VCC FIFO Reset Page 5 of 22 CY7C421 Maximum Ratings Power Dissipation ........................................................ 1.0 W Output Current, into Outputs (LOW) ........................... 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[1] Static Discharge Voltage (per MIL–STD–883, Method 3015) ......................... > 2000 V Storage Temperature ............................... –65 °C to +150 °C Latch Up Current ................................................... > 200 mA Ambient Temperature with Power Applied .................................. –55 °C to +125 °C Operating Range Supply Voltage to Ground Potential .............–0.5 V to +7.0 V Range DC Voltage Applied to Outputs in High Z State .............................................–0.5 V to +7.0 V Ambient Temperature[2] VCC 0 °C to +70 °C 5 V ± 10% –40 °C to +85 °C 5 V ± 10% Commercial Industrial DC Input Voltage .........................................–0.5 V to +7.0 V Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VCC = Min, IOH = –2.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current IOZ Output Leakage Current IOS Output Short Circuit Current All Speed Grades Test Conditions [4] Min Max Unit 2.4 – V – 0.4 V Commercial 2.0 VCC V Industrial 2.2 VCC [3] 0.8 V GND < VI < VCC –10 +10 μA R > VIH, GND < VO < VCC –10 +10 μA VCC = Max, VOUT = GND – –90 mA Electrical Characteristics Over the Operating Range Parameter ICC Description Operating Current Test Conditions -15 -20 Min Max Min Max VCC = Max, IOUT = 0 mA, f = fMAX Commercial – 65 – 55 Industrial – 100 – 90 Unit mA ICC1 Operating Current VCC = Max, IOUT = 0 mA, f = 20 MHz Commercial – 35 – 35 mA ISB1 Standby Current All Inputs = VIH Min Commercial – 10 – 10 mA Industrial – 15 – 15 Commercial – 5 – 5 Industrial – 8 – 8 ISB2 Power Down Current All Inputs > VCC – 0.2 V mA Notes 1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up. 2. TA is the “instant on” case temperature. 3. VIL(Min) = –2.0 V for pulse durations of less than 20 ns. 4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document Number: 38-06001 Rev. *K Page 6 of 22 CY7C421 Capacitance Parameter [5] Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 6 pF 6 pF TA = 25 °C, f = 1 MHz, VCC = 4.5 V AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms R1 500 Ω 5V R1 500 Ω 5V OUTPUT ALL INPUT PULSES 3.0 V OUTPUT R2 333 Ω 30 pF INCLUDING JIGAND SCOPE (a) R2 333 Ω 5 pF INCLUDING JIGAND SCOPE GND ≤ 3 ns 90% 10% 90% 10% ≤ 3 ns (b) Equivalent to: THÉVENIN EQUIVALENT 200Ω OUTPUT 2V Note 5. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-06001 Rev. *K Page 7 of 22 CY7C421 Switching Characteristics Over the Operating Range Parameter [6] Description -15 -20 Unit Min Max Min Max 25 – 30 – ns tRC Read Cycle Time tA Access Time – 15 – 20 ns tRR Read Recovery Time 10 – 10 – ns tPR Read Pulse Width 15 – 20 – ns tLZR[7] Read LOW to Low Z 3 – 3 – ns tDVR[7, 8] tHZR[7, 8] Data Valid after Read HIGH 5 – 5 – ns Read HIGH to High Z – 15 – 15 ns tWC Write Cycle Time 25 – 30 – ns tPW Write Pulse Width 15 – 20 – ns tHWZ[7] Write HIGH to Low Z 5 – 5 – ns tWR Write Recovery Time 10 – 10 – ns tSD Data Setup Time 8 – 12 – ns tHD Data Hold Time 0 – 0 – ns tMRSC MR Cycle Time 25 – 30 – ns tPMR MR Pulse Width 15 – 20 – ns tRMR MR Recovery Time 10 – 10 – ns tRPW Read HIGH to MR HIGH 15 – 20 – ns tWPW Write HIGH to MR HIGH 15 – 20 – ns tRTC Retransmit Cycle Time 25 – 30 – ns tPRT Retransmit Pulse Width 15 – 20 – ns tRTR Retransmit Recovery Time 10 – 10 – ns tEFL MR to EF LOW – 25 – 30 ns tHFH MR to HF HIGH – 25 – 30 ns tFFH MR to FF HIGH – 25 – 30 ns tREF Read LOW to EF LOW – 15 – 20 ns tRFF Read HIGH to FF HIGH – 15 – 20 ns tWEF Write HIGH to EF HIGH – 15 – 20 ns tWFF Write LOW to FF LOW – 15 – 20 ns tWHF Write LOW to HF LOW – 15 – 20 ns tRHF Read HIGH to HF HIGH – 15 – 20 ns tRAE Effective Read from Write HIGH – 15 – 20 ns tRPE Effective Read Pulse Width after EF HIGH 15 – 20 – ns tWAF Effective Write from Read HIGH – 15 – 20 ns tWPF Effective Write Pulse Width after FF HIGH 15 – 20 – ns tXOL Expansion Out LOW Delay from Clock – 15 – 20 ns tXOH Expansion Out HIGH Delay from Clock – 15 – 20 ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V and output loading of the specified IOL/IOH and 30 pF load capacitance, as in part (a) of Figure 4 on page 7, unless otherwise specified. 7. tHZR transition is measured at +200 mV from VOL and –200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured at ±100 mV from the steady state. 8. tHZR and tDVR use capacitance loading as in part (b) of Figure 4 on page 7. Document Number: 38-06001 Rev. *K Page 8 of 22 CY7C421 Switching Waveforms Figure 5. Asynchronous Read and Write tA R tRC tPR tA tRR tLZR tDVR tHZR DATA VALID Q0–Q 8 tPW tWC DATA VALID tWR W tSD tHD DATA VALID D0–D 8 DATA VALID Figure 6. Master Reset tMRSC [10] tPMR MR R, W [9] tRPW tWPW tEFL tRMR EF tHFH HF tFFH FF Figure 7. Half-full Flag HALF FULL HALF FULL+1 HALF FULL W tRHF R tWHF HF Notes 9. W and R ≥ VIH around the rising edge of MR. 10. tMRSC = tPMR + tRMR. Document Number: 38-06001 Rev. *K Page 9 of 22 CY7C421 Switching Waveforms (continued) Figure 8. Last Write to First Read Full Flag R LAST WRITE FIRST READ ADDITIONAL READS FIRST WRITE W tRFF tWFF FF Figure 9. Last Read to First Write Empty Flag W LAST READ FIRST WRITE ADDITIONAL WRITES FIRST READ R tWEF tREF EF tA Q0–Q8 VALID VALID Figure 10. Retransmit [11] tRTC[12] FL/RT tPRT R,W tRTR Notes 11. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTC. 12. tRTC = tPRT + tRTR. Document Number: 38-06001 Rev. *K Page 10 of 22 CY7C421 Switching Waveforms (continued) Figure 11. Empty Flag and Read Data Flow-through Mode D0–D8 W tRAE R tREF EF tWEF tHWZ tRPE tA Q0–Q8 DATA VALID Figure 12. Full Flag and Write Data Flow-through Mode R tWAF tWPF W tRFF tWFF FF tHD D0–D8 DATA VALID tA Q0–Q8 tSD DATA VALID Document Number: 38-06001 Rev. *K Page 11 of 22 CY7C421 Switching Waveforms (continued) Figure 13. Expansion Timing Diagrams WRITE TO LAST PHYSICAL LOCATION OF DEVICE 1 WRITE TO FIRST PHYSICAL LOCATION OF DEVICE 2 W tWR tXOH tXOL XO1(XI2)[13] tSD tHD DATA VALID D0–D 8 READ FROM LAST PHYSICAL LOCATION OF DEVICE 1 tHD tSD DATA VALID READ FROM FIRST PHYSICAL LOCATION OF DEVICE 2 R tRR [13] tXOL tXOH XO1(XI2) tHZR tLZR tDVR tDVR DATA VALID Q0–Q 8 tA DATA VALID tA Note 13. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2). Document Number: 38-06001 Rev. *K Page 12 of 22 CY7C421 Architecture Reading Data from the FIFO The CY7C421 FIFO consist of an array of 512 words of 9 bits each (implemented by an array of dual-port RAM cells), a read pointer, a write pointer, control signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags. The falling edge of R initiates a read cycle provided EF is not LOW. Data outputs (Q0–Q8) are in a high impedance condition between read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. Dual-Port RAM The dual-port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment the read and write pointers is much less than the time required for data propagation through the memory, which is the case if memory is implemented using the conventional register array architecture. Resetting the FIFO Upon power up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W) must be HIGH tRPW/tWPW before and tRMR after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs are in the high impedance state. Writing Data to the FIFO The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (D0–D8) tSD before and tHD after the rising edge of W are stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs tWEF after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW tWHF after the falling edge of W following the FIFO actually being Half Full. Therefore, the HF is active after the FIFO is filled to half its capacity plus one word. HF remains LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tRHF after the rising edge of R when the FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. FF goes LOW tWFF after the falling edge of W, during the cycle in which the last available location is filled. Internal logic prevents FIFO overflow. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tRFF after a read from a full FIFO. When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. The rising edge of R causes the data outputs to go to the high impedance state and remain such until a write is performed. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read tWEF after a valid write. The retransmit feature is beneficial when transferring packets of data. It enables the receiver to acknowledge receipt of data and retransmit, if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH for tPRT and tRTR after retransmit is asserted. With every read cycle after retransmit, the data from the first physical location of FIFO is read until the read pointer equals write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are also transmitted. Full depth of FIFO data can be repeatedly retransmitted. Standalone/Width Expansion Modes Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. Depth Expansion Mode Depth expansion mode (see Figure 14 on page 14) is entered when, during a MR cycle, Expansion Out (XO) of one device is connected to Expansion In (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and pulsed LOW again when the last physical location is read. Only one FIFO is enabled for read and one for write at any particular time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created of word widths in increments of 9. When expanding in depth, a composite FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode. Document Number: 38-06001 Rev. *K Page 13 of 22 CY7C421 Use of the Empty and Full Flags For example, consider an empty FIFO that is receiving read pulses. Because the FIFO is empty, the read pulses are ignored by the FIFO, and nothing happens. Next, a single word is written into the FIFO, with a signal that is asynchronous to the read signal. The (internal) state machine in the FIFO goes from empty to empty+1. However, it does this asynchronously with respect to the read signal, so that the effective pulse width of the read signal cannot be determined, because the state machine does not look at the read signal until it goes to the empty+1 state. Similarly, the minimum write pulse width may be violated by trying to write into a full FIFO, and asynchronously performing a read. The empty and full flags are used to avoid these effective pulse width violations, but to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next cycle. To achieve maximum frequency, the flags must be valid at the beginning of the next cycle. However, because they can be updated by either edge of the read or write signal, they must be valid by one-half of a cycle. Cypress FIFOs meet this requirement. The reason for why the flags should be valid by the next cycle is complex. The “effective pulse width violation” phenomenon can occur at the full and empty boundary conditions, if the flags are not properly used. The empty flag must be used to prevent reading from an empty FIFO and the full flag must be used to prevent writing into a full FIFO. Figure 14. Depth Expansion XO R W FF 9 EF 9 9 Q CY7C421 D FL VCC XI XO FULL EF FF EMPTY 9 CY7C421 FL XI XO * FF EF 9 CY7C421 MR FL XI * FIRST DEVICE Document Number: 38-06001 Rev. *K Page 14 of 22 CY7C421 Ordering Information Speed (ns) Package Diagram Ordering Code Package Type Operating Range 15 CY7C421-15AXC 51-85063 32-pin TQFP (Pb-free) Commercial 20 CY7C421-20JXC 51-85002 32-pin PLCC (Pb-free) Commercial CY7C421-20VXC 51-85031 28-pin (300 Mils) Molded SOJ (Pb-free) Ordering Code Definitions CY 7 C 4 2 1 - XX X X X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: X = A or J or V A = 32-pin TQFP J = 32-pin PLCC V = 28-pin Molded SOJ Speed: XX = 15 ns or 20 ns Depth: 1 = 512 Width: 2 = × 9 4 = FIFO Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-06001 Rev. *K Page 15 of 22 CY7C421 Package Diagrams Figure 15. 32-pin TQFP (7 × 7 × 1.0 mm) A3210 Package Outline, 51-85063 51-85063 *E Document Number: 38-06001 Rev. *K Page 16 of 22 CY7C421 Package Diagrams (continued) Figure 16. 32-pin PLCC (0.453 × 0.553 Inches) J32 Package Outline, 51-85002 51-85002 *E Document Number: 38-06001 Rev. *K Page 17 of 22 CY7C421 Package Diagrams (continued) Figure 17. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031 51-85031 *F Document Number: 38-06001 Rev. *K Page 18 of 22 CY7C421 Acronyms Acronym Document Conventions Description Units of Measure DIP Dual In-line Package FIFO First-In First-Out °C degree Celsius I/O Input/Output MHz megahertz LCC Leadless Chip Carrier μA microampere PLCC Plastic Leaded Chip Carrier mA milliampere RAM Random Access Memory mm millimeter SOJ Small Outline J-lead mV millivolt TQFP Thin Quad Flat Pack ns nanosecond TTL Transistor-Transistor Logic % percent pF picofarad V volt W watt Document Number: 38-06001 Rev. *K Symbol Unit of Measure Page 19 of 22 CY7C421 Document History Page Document Title: CY7C421, 512 × 9 Asynchronous FIFO Document Number: 38-06001 Rev. ECN No. Orig. of Change Submission Date ** 106462 SZV 07/11/01 Change from Spec Number: 38-00079 to 38-06001 *A 122332 RBI 12/30/02 Updated Maximum Ratings: Added Note 1 and referred the same note in “maximum ratings”. *B 383597 PCX See ECN Added Pb-Free Logo. Updated Ordering Information (Added the following MPNs: CY7C419-10JXC, CY7C419-15JXC, CY7C419-15VXC, CY7C421-10JXC, CY7C421-15AXC, CY7C421-20JXC, CY7C421-20VXC, CY7C425-10AXC, CY7C425-10JXC, CY7C425-15JXC, CY7C425-20JXC, CY7C425-20VXC, CY7C429-10AXC, CY7C429-15JXC, CY7C429-20JXC, CY7C433-10AXC, CY7C433-10JXC, CY7C433-15JXC, CY7C433-20AXC, CY7C433-20JXC). *C 2623658 VKN / PYRS 12/17/08 Removed 26-pin CerDIP, 32-pin RLCC, 28-pin molded DIP packages related information in all instances across the document. Removed Military Temperature Range related Information in all instances across the document. Updated Ordering Information (Added MPN CY7C421-20JXI, removed MPNs CY7C419/25/29/33). *D 2714768 VKN / AESA 06/04/2009 Updated Logic Block Diagram. Updated Pin Configurations. Updated Package Diagrams. *E 2896039 RAME 03/19/2010 Added Contents. Updated Ordering Information (Removed inactive parts from the data sheet). Updated Package Diagrams. Updated Sales, Solutions, and Legal Information (Updated links). Description of Change *F 3110157 ADMU 12/14/2010 Added Ordering Code Definitions under Ordering Information. *G 3324980 ADMU 07/26/2011 Updated title to read as “CY7C421, 512 × 9 Asynchronous FIFO”. Updated Features. Updated Functional Description (Removed CY7C420/424/425/428/429/432/433 related information). Updated Selection Guide (Removed -10, -25, -30, -40 and -65 speed bins related information). Updated Electrical Characteristics (Removed -10, -25, -30, -40 and -65 speed bins related information). Updated Switching Characteristics (Removed -10, -25, -30, -40 and -65 speed bins related information). Updated Architecture (Removed CY7C420/424/425/428/429/432/433 related information). Updated Package Diagrams. Added Acronyms and Units of Measure. Updated to new template. *H 3697624 SMCH 08/07/2012 Added Pin Definitions. Updated Architecture (Updated Reading Data from the FIFO (Updated description)). *I 4082890 SMCH 07/31/2013 Updated Ordering Information (Updated part numbers). Updated to new template. Completing Sunset Review. *J 4581652 SMCH 11/26/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Document Number: 38-06001 Rev. *K Page 20 of 22 CY7C421 Document History Page (continued) Document Title: CY7C421, 512 × 9 Asynchronous FIFO Document Number: 38-06001 Rev. ECN No. Orig. of Change Submission Date *K 5436569 NILE 09/14/2016 Document Number: 38-06001 Rev. *K Description of Change Updated Package Diagrams: spec 51-85063 – Changed revision from *D to *E. spec 51-85002 – Changed revision from *D to *E. spec 51-85031 – Changed revision from *E to *F. Updated to new template. Completing Sunset Review. Page 21 of 22 CY7C421 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-06001 Rev. *K Revised September 14, 2016 Page 22 of 22