CY7C4425/4205/4215
CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Features
Functional Description
■
High speed, low power, first-in first-out (FIFO) memories
■
64 x 18 (CY7C4425)
■
256 x 18 (CY7C4205)
■
512 x 18 (CY7C4215)
■
1K x 18 (CY7C4225)
The CY7C42X5 are high speed, low power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All are
18 bits wide and are pin/functionally compatible to IDT722X5.
The CY7C42X5 can be cascaded to increase FIFO depth.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.
■
2K x 18 (CY7C4235)
■
4K x 18 (CY7C4245)
■
High speed 100 MHz operation (10 ns read/write cycle time)
■
Low power (ICC = 45 mA)
■
Fully asynchronous and simultaneous read and write operation
■
Empty, Full, Half Full, and Programmable Almost Empty/Almost
Full status flags
■
TTL compatible
■
Retransmit function
■
Output Enable (OE) pin
■
Independent read and write enable pins
■
Center power and ground for reduced noise
■
Supports free running 50% duty cycle clock inputs
■
Width Expansion Capability
■
Depth Expansion Capability
■
Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and
68-pin PLCC
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN). When WEN is asserted, data is written into the FIFO
on the rising edge of the WCLK signal. While WEN is held active,
data is continually written into the FIFO on each cycle. The
output port is controlled in a similar manner by a free-running
read clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and write
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
applications. Clock frequencies up to 100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
should be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices should be tied to VCC.
The CY7C42X5 provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this pin
provides the expansion out (WXO) information that is used to
signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock
cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
VCC/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65m N-Well CMOS technology. Input ESD
protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
Cypress Semiconductor Corporation
Document Number: 001-45652 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 24, 2010
[+] Feedback
CY7C4425/4205/4215
CY7C4225/4235/4245
Logic Block Diagram
D0–17
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
RAM
ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
WRITE
POINTER
RS
FF
EF
FLAG
LOGIC
PAE
PAF
SMODE
READ
POINTER
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
TRI–STATE
OUTPUT REGISTER
EXPANSION
LOGIC
READ
CONTROL
OE
Q0–17
RCLK
REN
Pin Configuration
Q3
PAF
RXI
FF
WXO/HF
RXO
Q0
Q1
GND
Q2
PAE
FL/RT
WCLK
WEN
WXI
VCC
Document Number: 001-45652 Rev. *A
GND
Q15
Q16
EF
VCC
Q17
GND
RS
VCC
LD
OE
REN
60
59
58
57
56
55
54
53
52
51
50
49
48
VCC/SMODE
Q14
Q13
47
46
45
44
Q6
Q5
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
VCC
GND
Q4
VCC
Q2
Q3
GND
Q0
Q1
2728 2930 3132 33 34 35 36 37 38 3940 4142 43
WXO/HF
RXO
D3
D2
D1
D0
PAE
Q5
GND
Q4
VCC
21
22
23
24
25
26
2 1 68 67 66 65 64 63 62 61
RXI
FF
Q8
Q7
Q6
PAF
GND
3
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
WXI
VCC
VCC
Q10
Q9
4
WEN
Q14
Q13
GND
Q12
Q11
WCLK
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
6 5
10
11
12
13
14
15
16
17
18
19
20
FL/RT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D15
D14
D13
D12
D 11
D 10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
9 8 7
D14
D13
D12
D11
D10
D9
VCC
D8
GND
D7
D6
D5
D4
GND
RCLK
D16
D15
D17
Figure 2. PLCC (Top View)
VCC/SMODE
GND
EF
Q17
Q16
GND
Q15
D16
D17
GND
RCLK
REN
LD
OE
RS
VCC
Figure 1. TQFP (Top View)
Page 2 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Selection Guide
Description
-10
-15
Maximum Frequency (MHz)
100
Maximum Access Time (ns)
8
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (ICC2) (mA) @ 20MHz
Parameter
Density
Packages
-25
-35
66.7
40
28.6
10
15
20
10
15
25
35
3
4
6
7
0.5
1
1
2
20
8
10
15
Commercial
45
45
45
45
Industrial
50
50
50
50
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
(14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10)
68-pin PLCC
68-pin PLCC
68-pin PLCC
68-pin PLCC
68-pin PLCC
68-pin PLCC
(10 x 10)
(10 x 10)
(10 x 10)
(10 x 10)
(10 x 10)
(10 x 10)
Pin Definitions
Signal Name
Description
IO
Function
D0−17
Data Inputs
I
Q0−17
Data Outputs
O
Data outputs for an 18-bit bus.
WEN
Write Enable
I
Enables the WCLK input.
REN
Read Enable
I
Enables the RCLK input.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded – Write
Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC;
it is synchronized to RCLK when VCC/SMODE is tied to V SS.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC;
it is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0−17 (O0−17) are written (read) into (from) the programmable-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to VSS;
all other devices will have FL tied to VCC. In standard mode of width expansion, FL
is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit function is also
available in standalone mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS.
RXI
Read Expansion
Input
I
Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to VSS.
Document Number: 001-45652 Rev. *A
Data inputs for an 18-bit bus.
Page 3 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Pin Definitions (continued)
Description
IO
RXO
Signal Name
Read Expansion
Output
O
Cascaded – Connected to RXI of next device.
Function
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synchronous Almost Empty/Almost Full flags – tied to VSS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Architecture
Programming
The CY7C42X5 consists of an array of 64 to 4K words of 18 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5
also includes the control signals WXI, RXI, WXO, RXO for depth
expansion.
The CY7C42X5 devices contain two 12-bit offset registers. Data
present on D0–11 during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full)
flags become active. If the user elects not to program the FIFO’s
flags, the default offset values are used (see Table 2). When the
Load LD pin is set LOW and WEN is set LOW, data on the inputs
D0–11 is written into the Empty offset register on the first
LOW-to-HIGH transition of the write clock (WCLK). When the LD
pin and WEN are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the Write
Clock (WCLK). The third transition of the Write Clock (WCLK)
again writes to the Empty offset register (see Table 1). Writing all
offset registers does not have to occur at one time. One or two
offset registers can be written and then, by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When
the LD pin is set LOW, and WEN is LOW, the next offset register
in sequence is written.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. In order for the FIFO to reset to its
default state, a falling edge must occur on RS and the user must
not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D0-17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory will be presented on the Q0−17 outputs. New data
will be presented on each rising edge of RCLK while REN is
active LOW and OE is LOW. REN must set up tENS before RCLK
for it to be a valid read function. WEN must occur tENS before
WCLK for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q0−17 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0−17 outputs even
after additional reads occur.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 1. Write Offset Register
WCLK[1]
LD
WEN
0
0
Writing to offset registers:
Empty Offset
Full Offset
Selection
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
Note:
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document Number: 001-45652 Rev. *A
Page 4 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Flag Operation
that the FIFO is either Almost Full or Almost Empty. See Table 2
for a description of programmable flags.
The CY7C42X5 devices provide five flag pins to indicate the
condition of the FIFO contents. Empty and Full are synchronous.
PAE and PAF are synchronous if VCC/SMODE is tied to VSS.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
Full Flag
Retransmit
The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state
of WEN. FF is synchronized to WCLK, i.e., it is exclusively
updated by each rising edge of WCLK.
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless
of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C42X5 features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described in
the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last RS cycle. A HIGH pulse on
RT resets the internal read pointer to the first physical location of
the FIFO. WCLK and RCLK may be free running but must be
disabled during and tRTR after the retransmit pulse. With every
valid read cycle after retransmit, previously accessed data is
read and the read pointer is incremented until it is equal to the
write pointer. Flags are governed by the relative locations of the
read and write pointers and are updated during a retransmit
cycle. Data written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Table 2. Flag Truth Table
Number of Words in FIFO
CY7C4425 - 64 x 18
CY7C4205 - 256 x 18
CY7C4215 - 512 x 18
FF
PAF
HF
PAE
EF
0
0
0
H
H
H
L
L
1 to n[2]
1 to n[2]
1 to n[2]
H
H
H
L
H
(n + 1) to 32
(n + 1) to 128
(n + 1) to 256
H
H
H
H
H
33 to (64 − (m + 1))
129 to (256 − (m + 1))
257 to (512 − (m + 1))
H
H
L
H
H
(64 − m)[] to 63
(256 − m)[] to 255
(512 − m)[] to 511
H
L
L
H
H
64
256
512
L
L
L
H
H
FF
PAF
HF
PAE
EF
Number of Words in FIFO
CY7C4225 - 1K x 18
CY7C4235 - 2K x 18
CY7C4245 - 4K x 18
0
0
0
H
H
H
L
L
1 to n[2]
1 to n[2]
1 to n[2]
H
H
H
L
H
(n + 1) to 512
(n + 1) to 1024
(n + 1) to 2048
H
H
H
H
H
513 to (1024 − (m + 1))
1025 to (2048 − (m + 1))
2049 to (4096 − (m + 1))
H
H
L
H
H
(1024 − m)[3] to 1023
(2048 − m)[3] to 2047
(4096 − m)[3] to 4095
H
L
L
H
H
1024
2048
4096
L
L
L
H
H
Note
2. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127).
3. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127).
Document Number: 001-45652 Rev. *A
Page 5 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Width Expansion Configuration
The CY7C42X5 can be expanded in width to provide word widths
greater than 18 in increments of 18. During width expansion
mode all control line inputs are common and all flags are
available. Empty (Full) flags should be created by ANDing the
Empty (Full) flags of every FIFO. This technique will avoid ready
data from the FIFO that is “staggered” by one clock cycle due to
the variations in skew between RCLK and WCLK. Figure 3
demonstrates a 36-word width by using two CY7C42X5.
Figure 3. Block Diagram of Synchronous FIFO Memories Used in a Width Expansion Configuration
RESET (RS)
DATAIN (D) 36
RESET (RS)
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE(OE)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
FF
7C4425
7C4205
7C4215
7C4225
7C4235
7C4245
7C4425
7C4205
7C4215
7C4225
7C4235
7C4245
FF
EF
PROGRAMMABLE(PAF)
EMPTYFLAG (EF)
EF
18
FULL FLAG (FF)
DATAOUT (Q)
36
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
Depth Expansion Configuration (with Programmable Flags)
The CY7C42X5 can easily be adapted to applications requiring
more than 64/256/512/1024/2048/4096 words of buffering.
Figure 4 shows Depth Expansion using three CY7C42X5s.
Maximum depth is limited only by signal loading. Follow these
steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be
tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth
Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
Document Number: 001-45652 Rev. *A
Page 6 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Figure 4. Block Diagram of Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4245
VCC
FIRSTLOAD (FL)
FF
EF
PAE
PAF
WXI RXI
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4245
DATAIN (D)
VCC
FIRSTLOAD (FL)
DATAOUT (Q)
FF
EF
PAE
PAF
WXI RXI
WRITECLOCK (WCLK)
WXO RXO
WRITE ENABLE (WEN)
READ ENABLE (REN)
7C4425
7C4205
7C4215
7C4225
7C4235
7C4245
RESET(RS)
LOAD (LD)
FF
FF
PAF
READ CLOCK (RCLK)
OUTPUT ENABLE (OE)
EF
EF
PAFWXI RXIPAE
PAE
42X5–23
FIRSTLOAD (FL)
Document Number: 001-45652 Rev. *A
Page 7 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
DC Input Voltage ................................................. −3.0V to +7.0V
Maximum Ratings[6]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ....................................−65° C to +150 °C
Ambient Temperature with
Power Applied.................................................−55° C to +125 °C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ..................................................... >200mA
Operating Range
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High-Z State .....................................................−0.5V to +7.0V
Commercial
Electrical Characteristics Over the Operating
Industrial
Description
VCC
0° C to +70° C
5V ± 10%
-40° C to +85 °C
5V ± 10%
[4]
Range[6]
-10
Parameter
Ambient Temperature
Test Conditions
Min.
-15
Max.
Max.
2.4
Min.
-35
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = −2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH[7]
Input HIGH Voltage
2.2
VCC
2.2
VCC
2.2
VCC
[7]
Input LOW Voltage
−3.0
0.8
−3.0
0.8
−3.0
+10
−10
+10
−10
VIL
2.4
Min.
-25
0.4
2.4
0.4
Input Leakage Current
VCC = Max.
−10
Output Short Circuit
Current
VCC = Max.,
VOUT = GND
−90
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
−10
ICC[9]
Operating Current
VCC = Max.,
IOUT = 0 mA
Com’l
45
45
Ind’l
50
VCC = Max.,
IOUT = 0 mA
Com’l
Ind’l
IIX
IOS
ISB
[8]
[10]
Standby Current
−90
2.4
0.4
Unit
V
0.4
V
2.2
VCC
V
0.8
−3.0
0.8
V
+10
−10
+10
μA
−90
−90
45
45
mA
50
50
50
mA
10
10
10
10
mA
15
15
15
15
mA
+10
−10
μA
μA
+10
−10
Max.
+10
+10
−10
Min.
Capacitance[11]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25° C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
5
pF
7
pF
Notes
4. TA is the “instant on” case temperature.
5. See the last page of this specification for Group A subgroup testing information.
6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up
7. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device
or VSS.
8. Test no more than one output at a time for not more than one second.
9. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs
are unloaded.
10. All input signals are connected to VCC. All outputs are unloaded.
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-45652 Rev. *A
Page 8 of 22
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Figure 5. AC Test Loads and Waveforms[13, 14]
R1 = 1.1KΩ
ALL INPUT PULSES
5V
OUTPUT
3.0V
CL
R2 =680Ω
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
Rth = 410Ω
OUTPUT
90%
10%
90%
10%
≤ 3 ns
Vth = 1.91V
Switching Characteristics Over the Operating Range
Parameter
tS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSR
tRSF
tPRT
tRTR
tOLZ
tOE
tOHZ
tWFF
tREF
tPAFasynch
tPAFsynch
tPAEasynch
tPAEsynch
Description
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time.
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width[15]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z[16]
Output Enable to Output Valid
Output Enable to Output in High Z[16]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag[17]
(Asynchronous mode, VCC/SMODE tied to VCC)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
Clock to Programmable Almost-Empty Flag[17]
(Asynchronous mode, VCC/SMODE tied to VCC)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
-10
Min. Max.
100
2
8
10
4.5
4.5
3
0.5
3
0.5
10
8
10
12
12
0
3
7
3
7
8
8
12
-15
Min. Max.
66.7
2
10
15
6
6
4
1
4
1
15
10
15
15
15
0
3
8
3
8
10
10
16
-25
Min. Max.
40
2
15
25
10
10
6
1
6
1
25
15
25
25
25
0
3
12
3
12
15
15
20
-35
Min. Max.
28.6
2
20
35
14
14
7
2
7
2
35
20
35
35
35
0
3
15
3
15
20
20
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
15
20
ns
12
16
20
25
ns
8
10
15
20
ns
Notes
13. CL = 30 pF for all AC parameters except for tOHZ.
14. CL = 5 pF for t OHZ.
15. Pulse widths less than minimum values are not allowed.
16. Values guaranteed by design, not currently tested.
17. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
Document Number: 001-45652 Rev. *A
Page 9 of 22
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Switching Characteristics Over the Operating Range (continued)
Parameter
tHF
tXO
tXI
tXIS
tSKEW1
tSKEW2
tSKEW3
Description
Clock to Half-Full Flag
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-up Time
Skew Time between Read Clock and Write Clock
for Full Flag
Skew Time between Read Clock and Write Clock
for Empty Flag
Skew Time between Read Clock and Write Clock
for Programmable Almost Empty and Programmable Almost Full Flags.
-10
Min. Max.
12
7
3
4.5
5
-15
Min. Max.
16
10
6.5
5
6
-25
Min. Max.
20
15
10
10
10
-35
Min. Max.
25
20
14
15
12
Unit
ns
ns
ns
ns
ns
5
6
10
12
ns
10
15
18
20
ns
Switching Waveforms
Figure 6. Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
–D17
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1[18]
RCLK
REN
Note
18. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Document Number: 001-45652 Rev. *A
Page 10 of 22
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Switching Waveforms (continued)
Figure 7. Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0–Q17
tOLZ
tOHZ
tOE
OE
tSKEW2 [19]
WCLK
WEN
Figure 8. Reset Timing[20]
tRS
RS
tRSR
REN, WEN,
LD
tRSF
EF,PAE
tRSF
FF,PAF,
HF
tRSF
OE = 1
[21]
Q0–Q17
OE = 0
Notes:
19. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
20. The clocks (RCLK, WCLK) can be free-running during reset.
21. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
Document Number: 001-45652 Rev. *A
Page 11 of 22
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Switching Waveforms (continued)
Figure 9. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0–D17
D0 (FIRSTVALID WRITE)
D1
D2
D3
D4
tENS
[22]
tFRL
WEN
tSKEW2
RCLK
tREF
EF
REN
tA [23]
tA
Q0–Q17
D0
D1
tOLZ
tOE
OE
Figure 10. Empty Flag Timing
WCLK
tDS
tDS
D0
D0–D17
tENS
D1
tENH
tENS
tENH
WEN
tFRL[22]
tFRL[22]
RCLK
tSKEW2
tREF
tREF
tREF
tSKEW2
EF
REN
OE
tA
Q0–Q17
D0
Notes:
22. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK +
tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
23. The first word is available the cycle after EF goes HIGH, always.
Document Number: 001-45652 Rev. *A
Page 12 of 22
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Switching Waveforms (continued)
Figure 11. Full Flag Timing
NO WRITE
NO WRITE
WCLK
tSKEW1 [18]
tSKEW1 [18]
tDS
DATA WRITE
DATA WRITE
D0–D17
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
LOW
tA
Q0–q17
tA
DATAREAD
DATA IN OUTPUT REGISTER
NEXT DATA READ
Figure 12. Half-Full Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tHF
HF
HALF FULL+1
OR MORE
HALF FULL OR LESS
HALF FULL OR LESS
tHF
RCLK
tENS
REN
Document Number: 001-45652 Rev. *A
Page 13 of 22
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Switching Waveforms (continued)
Figure 13. Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLK
tENS tENH
WEN
tPAE
PAE
[24]
n+1 WORDS
IN FIFO
tPAE
n WORDS IN FIFO
RCLK
tENS
REN
Figure 14. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
tCLKL
tCLKH
WCLK
tENS tENH
WEN
Note 25
PAE
tSKEW3 [26]
N + 1 WORDS
INFIFO
tPAEsynch
Note 27
tPAEsynch
RCLK
tENS
tENS tENH
REN
Notes:
24. PAE offset − n. Number of data words into FIFO already = n.
25. PAE offset − n.
26. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
27. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
Document Number: 001-45652 Rev. *A
Page 14 of 22
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Switching Waveforms (continued)
Figure 15. Programmable Almost Full Flag Timing
tCLKL
tCLKH
Note 28
WCLK
tENS tENH
WEN
tPAF
FULL − M WORDS
IN FIFO [30]
[29]
PAF
FULL − M + 1 WORDS
IN FIFO [31]
tPAF
RCLK
tENS
REN
Figure 16. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))
tCLKL
tCLKH
Note 32
WCLK
tENS tENH
WEN
Note 33
PAF
tPAF
FULL − M WORDS
IN FIFO [30]
FULL – M + 1 WORDS
IN FIFO
tSKEW3 [34]
tPAFsynch
RCLK
tENS
tENS tENH
REN
Notes:
28. PAF offset = m. Number of data words written into FIFO already = 64 − m + 1 for the CY7C4425, 256 − m + 1 for the CY7C4205, 512 − m + 1 for the CY7C4215. 1024
− m + 1 for the CY7C4225, 2048 − m + 1 for the CY7C4235, and 4096 − m + 1 for the CY7C4245.
29. PAF is offset = m.
30. 64 − m words in CY7C4425, 256 – m words in CY7C4205, 512 − m words in CY7C4215. 1024 – m words in CY7C4225, 2048 − m words in CY7C4235, and 4096 – m
words in CY7C4245.
31. 64 − m + 1 words in CY7C4425, 256 − m + 1 words in CY7C4205, 512 − m + 1 words in CY7C4215, 1024 − m + 1 CY7C4225, 2048 − m + 1 in CY7C4235, and 4096
− m + 1 words in CY7C4245.
32. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.
33. PAF offset = m.
34. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK
and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
Document Number: 001-45652 Rev. *A
Page 15 of 22
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Switching Waveforms (continued)
Figure 17. Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0–D17
PAE OFFSET
PAF OFFSET
D0–D11
Figure 18. Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
LD
tENS
REN
tA
Q0–Q17
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
Figure 19. Write Expansion Out Timing
tCLKH
WCLK
Note 35
tXO
WXO
tENS
tXO
WEN
Note:
35. Write to Last Physical Location.
Document Number: 001-45652 Rev. *A
Page 16 of 22
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Switching Waveforms (continued)
Figure 20. Read Expansion Out Timing
tCLKH
RCLK
Note 36
tXO
RXO
tXO
tENS
REN
Figure 21. Write Expansion In Timing
tXI
WXI
WCLK
tXIS
Figure 22. Read Expansion In Timing
tXI
RXI
tXIS
RCLK
Figure 23. Retransmit Timing[37, 38, 39]
FL/RT
tPRT
tRTR
REN/WEN
EF/FF
and/all
async flags
HF/PAE/PAF
Notes:
36. Read from Last Physical Location.
37. Clocks are free running in this case.
38. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
39. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
Document Number: 001-45652 Rev. *A
Page 17 of 22
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Figure 24. Typical AC and DC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.2
1.0
VIN =3.0V
TA =25°C
f=100 MHz
0.6
4
1.0
VIN =3.0V
VCC =5.0V
f=100 MHz
0.9
0.8
5
4.5
1.1
5.5
−55
6
SUPPLY VOLTAGE (V)
NORMALIZED tA
NORMALIZED tA
1.1
1.0
0.9
5.5
3
4
OUTPUT VOLTAGE (V)
Document Number: 001-45652 Rev. *A
5
OUTPUT SINK CURENT (mA)
OUTPUTS OURCE CURRENT (mA)
35
2
50
75
100
1.0
VCC =5.0V
.75
25
125
25
10
−5.0
.50
VCC =5.0V
TA =25°C
275
550
825
1000
CAPACITANCE (pF)
OUTPUT SINK CURRENT vs.
OUTPUT VOLTAGE
TA =25°C
VCC =5.0V
1
25
TYPICAL tA CHANGE vs.
OUTPUT LOADING
AMBIENT TEMPERATURE (°C)
55
0
0.7
FREQUENCY (MHz)
1.25
OUTPUT SOURCECURRENT
vs. OUTPUT VOLTAGE
25
0.8
40
0.5
−55
6
SUPPLY VOLTAGE (V)
45
0.9
0.6
0
125
1.50
TA =25°C
5
1.0
NORMALIZED tA vs.
AMBIENT TEMPERATURE
1.2
4.5
VCC =5.0V
TA =25°C
VIN =3.0V
AMBIENT TEMPERATURE (°C)
NORMALIZED tA vs.SUPPLY
VOLTAGE
4
25
NORMALIZED tA
0.8
1.1
NORMALIZED ICC
NORMALIZED ICC
NORMALIZED ICC
1.4
0.8
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
120
140
120
100
80
TA =25°C
VCC =5.0V
60
40
20
0
0
1
2
3
4
OUTPUT VOLTAGE (V)
Page 18 of 22
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Ordering Information
256 x 18 Synchronous FIFO
Speed
(ns)
10
Package
Name
Ordering Code
CY7C4205-10AXC
51-85046
Package
Type
64-Pin (14 x 14) Thin Quad Flatpack (Pb-Free)
Operating
Range
Commercial
512 x 18 Synchronous FIFO
Speed
(ns)
15
Package
Name
Ordering Code
CY7C4215-15AXI
51-85046
Package
Type
64-Pin (14 x 14) Thin Quad Flatpack (Pb-Free)
Operating
Range
Industrial
1K x 18 Synchronous FIFO
Speed
(ns)
Package
Name
Ordering Code
Package
Type
Operating
Range
10
CY7C4225-10AXI
51-85046
64-Pin (14 x 14) Thin Quad Flatpack (Pb-Free)
Industrial
15
CY7C4225-15AXC
51-85046
64-Pin (14 x 14) Thin Quad Flatpack (Pb-Free)
Commercial
CY7C4225-15ASXC
51-85051
64-Pin (10 x 10) Thin Quad Flatpack (Pb-Free)
4K x 18 Synchronous FIFO
Speed
(ns)
Package
Name
Ordering Code
Package
Type
Operating
Range
10
CY7C4245-10AXI
51-85046
64-Pin (14 x 14) Thin Quad Flatpack (Pb-Free)
Industrial
15
CY7C4245-15AXC
51-85046
64-Pin (14 x 14) Thin Quad Flatpack (Pb-Free)
Commercial
CY7C4245-15ASXC
51-85051
64-Pin (10 x 10) Thin Quad Flatpack (Pb-Free)
Ordering Code Definitions
CY
7
C
4
2X
5
XX
X
X
C, I
Temperature Grade:
C = Commercial, I = Industrial
Pb-free (RoHS Compliant)
Package:
A = TQFP, AS = STQFP, J = PLCC
Speed grade: 10 ns or 15 ns
x18
Depth:
20 = 256 b; 21 = 512 b;
22 = 1 K; 23 = 2 K; 24 = 4 K
FIFO
Technology: CMOS
Family: Dual-port SRAM
Company ID: CY = Cypress
Document Number: 001-45652 Rev. *A
Page 19 of 22
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Package Diagrams
Figure 25. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm), 51-85046
51-85046 *D
Document Number: 001-45652 Rev. *A
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Package Diagrams (continued)
Figure 26. 64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm), 51-85051
51-85051 *B
Figure 27. 68-Pin Plastic Leaded Chip Carrier, 51-85005
51-85005 *B
Document Number: 001-45652 Rev. *A
Page 21 of 22
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Document History Page
Document Title:
CY7C4425/CY7C4205/CY7C4215/CY7C4225/CY7C4235/CY7C4245, 64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Document Number: 001-45652
REV.
ECN NO.
Issue Date
Orig. of
Change
**
2489087
See ECN
VKN
*A
3094407
11/24/10
ADMU
Description of Change
This document is recreated from the existing pdf file on web. This is provided a
new spec number.
Removed following invalid parts from the ordering information table.
CY7C4205-15AC
CY7C4205-15AXC
CY7C4215-15AI
CY7C4225-10AI
CY7C4225-15ASC
CY7C4235-15AXC
CY7C4245-10AI
CY7C4245-10AXC
CY7C4245-10ASXC
CY7C4245-15JXC
Added ordering code definitions.
Updated package diagrams to latest revision.
© Cypress Semiconductor Corporation, 2008-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-45652 Rev. *A
Revised November 24, 2010
Page 22 of 22
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