CY7C4421V/4201V/4211V/4221VCY7C4231V/4241V/4251VLow-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Featuresb
• Space saving 32-pin 7 mm × 7 mm TQFP
• 32-pin PLCC
• High-speed, low-power, first-in, first-out (FIFO)
memories
• Available in Pb-Free Packages
• 64 x 9 (CY7C4421V)
Functional Description
• 256 x 9 (CY7C4201V)
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty
flags. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
• High-speed 66-MHz operation (15-ns read/write cycle
time)
• Low power (ICC = 20 mA)
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• 5V-tolerant inputs VIH max = 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a Free-Running Read Clock (RCLK) and
two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock
frequencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
• Width expansion capability
Logic Block Diagram
Pin Configuration
D0 − 8
D2
D3
D4
D5
D6
D7
D8
PLCC
Top View
INPUT
REGISTER
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
WRITE
POINTER
RS
EF
PAE
PAF
FF
4 3 2 1 32 3130
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
14151617181920
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
EF
FF
Q0
Q1
Q2
Q3
Q4
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
READ
POINTER
8Kx 9
RESET
LOGIC
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
OE
Q0 − 8
Cypress Semiconductor Corporation
Document #: 38-06010 Rev. *B
•
RCLK REN1 REN2
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 14, 2005
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Selection Guide
CY7C42X1V-15
Maximum Frequency
CY7C42X1V-25
CY7C42X1V-35
Unit
66.7
40
28.6
MHz
Maximum Access Time
11
15
20
ns
Minimum Cycle Time
15
25
35
ns
Minimum Data or Enable Set-up
4
6
7
ns
Minimum Data or Enable Hold
1
1
2
ns
Maximum Flag Delay
10
15
20
ns
20
20
20
mA
Active Power Supply Current
Commercial
CY7C4421V
CY7C4201V
CY7C4211V
CY7C4221V
CY7C4231V
CY7C4241V
CY7C4251V
64 x 9
256 x 9
512 x 9
1K x 9
2K x 9
4K x 9
8K x 9
Density
Pin Definitions
Signal Name
Description
I/O
Description
D0−8
Data Inputs
I
Data Inputs for 9-bit bus.
Q0−8
Data Outputs
O
Data Outputs for 9-bit bus.
WEN1
Write Enable 1
I
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
I
Load
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
REN1, REN2
Read Enable
Inputs
I
Enables the device for Read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag
offset register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Functional Description (continued)
The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are
programmable to single word granularity. The programmable flags
default to Empty-7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK).
Document #: 38-06010 Rev. *B
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65µ
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Page 2 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Architecture
The CY7C42X1V consists of an array of 64 to 8K words of nine
bits each (implemented by a dual-port array of SRAM cells),
a read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,
FF.)
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q0-8) go LOW
tRSF after the rising edge of RS. In order for the FIFO to reset
to its default state, a falling edge must occur on RS and the
user must not read or write while RS is LOW. All flags are
guaranteed to be valid tRSF after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D0-8 pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will
be presented on the Q0-8 outputs. New data will be presented
on each rising edge of RCLK while REN1 and REN2 are
active. REN1 and REN2 must set up tENS before RCLK for it
to be a valid read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q0-8
outputs when OE is asserted. When OE is enabled (LOW), data
in the output register will be available to the Q0-8 outputs after tOE.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0-8 outputs
even after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Document #: 38-06010 Rev. *B
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS=LOW), this pin operates as a second write
enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)
is HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK.) Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1V for writing or reading data to
these registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset Least Significant Bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset Most Significant Bit (MSB) register, full
offset LSB register, and full offset MSB register, respectively,
when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again. Figure 1 shows
the register sizes and default values for the various device
types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW,
a write operation stores data in the next offset register in
sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Page 3 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
64 x 9
8
256 x 9
0
6
Empty Offset (LSB) Reg.
Default Value = 007h
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
1K x 9
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
512 x 9
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
0
7
(MSB)
0
8
0
6
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
8
Full Offset (LSB) Reg
Default Value = 007h
0
8
Full Offset (LSB) Reg
Default Value = 007h
0
8
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
0
8
(MSB)
00
0
7
8
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
7
0
8
Full Offset (LSB) Reg
Default Value = 007h
(MSB)
00000
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
0
2
8
(MSB)
000
0
7
Full Offset (LSB) Reg
Default Value = 007h
0
3
0
4
8
(MSB)
0000
7
8
0
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
3
8
(MSB)
000
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
2
8
(MSB)
00
8K x 9
4K x 9
0
0
1
8
(MSB)
0
2K x 9
0
1
8
8
(MSB)
0000
0
4
(MSB)
00000
Figure 1. Offset Register Location and Default Values
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable Almost Empty Flag (PAE) and programmable
Almost Full Flag (PAF) states are determined by their corresponding offset registers and the difference between the read
and write pointers.
Table 1. Writing the Offset Registers
WCLK[1]
LD
WEN
Selection
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of PAE. PAE is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK
when the FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421V (64 – m), CY7C4201V
(256 – m), CY7C4211V (512 – m), CY7C4221V (1K – m),
CY7C4231V (2K – m), CY7C4241V (4K – m), and
CY7C4251V (8K – m). PAF is set HIGH by the LOW-to-HIGH
transition of WCLK when the number of available memory
locations is greater than m.
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06010 Rev. *B
Page 4 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Table 2. Status Flags
Number of Words in FIFO
CY7C4421V
CY7C4201V
CY7C4211V
FF
PAF
PAE
EF
0
0
0
H
H
L
L
1 to n[2]
1 to n[2]
1 to n[2]
H
H
L
H
(n+1) to 32
(n+1) to 128
(n+1) to 256
H
H
H
H
33 to (64−(m+1))
129 to (256−(m+1))
257 to (512−(m+1))
H
H
H
H
(64−m)[3] to 63
(256−m)[3] to 255
(512−m)[3] to 511
H
L
H
H
64
256
512
L
L
H
H
Number of Words in FIFO
CY7C4221V
0
1 to
CY7C4231V
0
n[2]
CY7C4241V
0
[2]
CY7C4251V
0
[2]
[2]
FF
PAF
PAE
EF
H
H
L
L
1 to n
1 to n
1 to n
H
H
L
H
(n+1) to 1024
(n+1) to 2048
(n+1) to 4096
H
H
H
H
513 to (1024 −(m+1))
1025 to (2048 −(m+1))
2049 to (4096 −(m+1))
4097 to (8192 −(m+1))
H
H
H
H
(1024−m)[3] to 1023
(2048−m)[3] to 2047
(4096−m)[3] to 4095
(8192−m)[3] to 8191
H
L
H
H
1024
2048
4096
8192
L
L
H
H
(n+1) to 512
Width Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C42X1Vs. Any
word width can be attained by adding additional
CY7C42X1Vs.
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
When the CY7C42X1V is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write operations are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it
is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
Notes:
2. n = Empty Offset (n=7 default value).
3. m = Full Offset (m=7 default value).
Document #: 38-06010 Rev. *B
Page 5 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
RESET (RS)
DATA IN (D) 18
RESET (RS)
9
9
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE 1 (REN1)
WRITE ENABLE 1 (WEN1)
OUTPUT ENABLE (OE)
WRITE ENABLE 2/LOAD
(WEN2/LD)
CY7C42X1V
PROGRAMMABLE (PAF)
FULL FLAG (FF) # 1
CY7C42X1V
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EF EMPTY FLAG (EF) #2
EF
FF
FF
9
FULL FLAG (FF) # 2
DATA OUT (Q)
18
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Low-Voltage Synchronous FIFO
Memory Used in a Width-Expansion Configuration
Document #: 38-06010 Rev. *B
Page 6 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –-55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +5.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +5.0V
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
3.3V ± 300 mV
–40° to +85°C
3.3V ± 300 mV
Commercial
Industrial
DC Input Voltage............................................ –0.5V to +5.0V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C42X1V-15
7C42X1V-25
7C42X1V-35
Min.
Min.
Min.
Max.
2.4
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = −2.0 mA
2.4
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
5.0
2.0
5.0
VIL
Input LOW Voltage
−0.5
0.8
−0.5
IIX
Input Leakage Current
VCC = Max.
−10
+10
IOZL
IOZH
Output OFF, High Z
Current
OE > VIH,
VSS < VO < VCC
−10
+10
ICC[4]
Active Power Supply
Current
Com’l
20
ISB[5]
Average Standby
Current
Com’l
6
0.4
Max.
2.4
Unit
V
0.4
0.4
V
2.0
5.0
V
0.8
−0.5
0.8
V
−10
+10
−10
+10
µA
−10
+10
−10
+10
µA
20
20
mA
6
6
mA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Unit
5
pF
7
pF
AC Test Loads and Waveforms[7, 8]
R1 = 330Ω
ALL INPUT PULSES
3.3V
OUTPUT
3.0V
CL
R2 = 510Ω
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
Rth = 200Ω
OUTPUT
GND
≤ 3 ns
90%
10%
90%
10%
≤ 3 ns
Vth = 2.0V
Notes:
4. Outputs open. Tested at Frequency = 20 MHz.
5. All inputs = VCC – 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
6. Tested initially and after any design or process changes that may affect these parameters.
7. CL = 30 pF for all AC parameters except for tOHZ.
8. CL = 5 pF for tOHZ.
Document #: 38-06010 Rev. *B
Page 7 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Characteristics Over the Operating Range
Parameter
Description
7C42X1V-15
7C42X1V-25
7C42X1V-35
Min.
Min.
Min.
Max.
66.7
Max.
Unit
28.6
MHz
20
ns
Clock Cycle Frequency
tA
Data Access Time
2
tCLK
Clock Cycle Time
15
tCLKH
Clock HIGH Time
6
10
14
ns
tCLKL
Clock LOW Time
6
10
14
ns
tDS
Data Set-Up Time
4
6
7
ns
tDH
Data Hold Time
1
2
2
ns
tENS
Enable Set-Up Time
4
6
7
ns
tENH
Enable Hold Time
1
2
2
ns
tRS
Reset Pulse Width[9]
15
25
35
ns
tRSS
Reset Set-Up Time
10
15
20
ns
tRSR
Reset Recovery Time
10
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low Z[10]
0
tOE
Output Enable to Output Valid
3
tOHZ
Output Enable to Output in High Z[10]
3
tWFF
Write Clock to Full Flag
tREF
tPAF
tPAE
Clock to Programmable Almost-Full Flag
tSKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
15
18
20
ns
11
40
Max.
tS
2
15
25
15
18
2
35
20
25
0
8
3
8
3
ns
ns
35
ns
15
ns
0
12
3
12
3
ns
15
ns
11
15
20
ns
Read Clock to Empty Flag
11
15
20
ns
Clock to Programmable Almost-Full Flag
16
22
25
ns
25
ns
16
22
Notes:
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
Document #: 38-06010 Rev. *B
Page 8 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D8
tENS
tENH
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
tWFF
tWFF
FF
tSKEW1
[11]
RCLK
REN1,REN2
Read Cycle Timing
tCKL
tCLKH
tCLKL
RCLK
tENS
tENH
REN1,REN2
NO OPERATION
tREF
tREF
EF
tA
Q0 –Q8
VALID DATA
tOLZ
tOHZ
tOE
OE
tSKEW1
[12]
WCLK
WEN1
WEN2
Notes:
11. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
12. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
Document #: 38-06010 Rev. *B
Page 9 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Reset Timing[13]
RS
tRS
REN1,
REN2
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
WEN1
WEN2/LD
[15]
tRSF
EF,PAE
tRSF
FF,PAF,
tRSF
Q0 − Q8
OE=1 [14]
OE=0
Notes:
13. The clocks (RCLK, WCLK) can be free-running during reset.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
Document #: 38-06010 Rev. *B
Page 10 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0 –D8
D0 (FIRSTVALID WRITE)
D1
D2
D3
[17]
tA
D4
tENS
tFRL
WEN1
[16]
WEN2
(if applicable)
tSKEW1
RCLK
tREF
EF
tA
REN1,
REN2
Q0 –Q8
D0
tOLZ
D1
tOE
OE
Notes:
16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK
+ tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
17. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06010 Rev. *B
Page 11 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Empty Flag Timing
WCLK
tDS
tDS
DATAWRITE2
DATAWRITE1
D0 –D8
tENH
WEN1
tENH
tENS
tENS
tENS
tENH
tENS
tENH
WEN2
(if applicable)
tFRL
[16]
tFRL
[16]
RCLK
tSKEW1
tREF
tREF
tREF
tSKEW1
EF
REN1,
REN2
LOW
OE
tA
Q0 –Q8
DATA IN OUTPUT REGISTER
Document #: 38-06010 Rev. *B
DATA READ
Page 12 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Full Flag Timing
NO WRITE
NO WRITE
NO WRITE
WCLK
tSKEW1
[11]
tSKEW1 [11]
tDS
DATA WRITE
DATA WRITE
D0 –D8
tWFF
tWFF
tWFF
FF
WEN1
WEN2
(if applicable)
RCLK
tENS
REN1,
REN2
OE
tENH
tENS
LOW
tA
Q0 –Q8
tENH
tA
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLK
tENS tENH
WEN1
WEN2
(if applicable)
tENS tENH
Note 19
PAE
N + 1 WORDS
INFIFO
tSKEW2 [18]
tPAE
Note 20
tPAE
RCLK
tENS
tENS tENH
REN1,
REN2
Notes:
18. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
19. PAE offset = n.
20. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
Document #: 38-06010 Rev. *B
Page 13 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Programmable Almost Full Flag Timing
Note 21
tCLKL
tCLKH
WCLK
tENS tENH
WEN1
[22]
WEN2
(if applicable)
tPAF
tENS tENH
PAF
FULL − M WORDS
IN FIFO [23]
FULL − (M+1) WORDS
IN FIFO
tSKEW2 [24]
tPAF
RCLK
tENS
tENS tENH
REN1,
REN2
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
WEN2/LD
tENS
WEN1
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
21. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.
22. PAF offset = m.
23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for
CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V.
24. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06010 Rev. *B
Page 14 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
WEN2/LD
tENS
PAF OFFSET
MSB
REN1,
REN2
tA
UNKNOWN
Q0 –Q8
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
Ordering Information
256 x 9 Low Voltage Synchronous FIFO
Speed (ns)
15
25
Ordering Code
Package Name
Package Type
CY7C4201V-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4201V-15AXC
A32
32-Lead Pb-Free Thin Quad Flatpack
CY7C4201V-25AC
A32
32-Lead Thin Quad Flatpack
Operating Range
Commercial
Commercial
512 x 9 Low Voltage Synchronous FIFO
Speed (ns)
15
25
Ordering Code
Package Name
CY7C4211V-15AC
Package Type
A32
32-Lead Thin Quad Flatpack
CY7C4211V-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4211V-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4211V-15AXI
A32
32-Lead Pb-Free Thin Quad Flatpack
CY7C4211V-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4211V-25JC
J65
32-Lead Plastic Leaded Chip Carrier
Operating Range
Commercial
Industrial
Commercial
1K x 9 Low Voltage Synchronous FIFO
Speed (ns)
15
25
Ordering Code
Package Name
CY7C4221V-15AC
Package Type
A32
32-Lead Thin Quad Flatpack
CY7C4221V-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4221V-25AC
A32
32-Lead Thin Quad Flatpack
Operating Range
Commercial
Commercial
2K x 9 Low Voltage Synchronous FIFO
Speed (ns)
15
25
Ordering Code
Package Name
Package Type
CY7C4231V-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4231V-15JXC
J65
32-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C4231V-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4231V-25AXC
A32
32-Lead Pb-Free Thin Quad Flatpack
CY7C4231V-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4231V-25JC
J65
32-Lead Plastic Leaded Chip Carrier
Document #: 38-06010 Rev. *B
Operating Range
Commercial
Commercial
Page 15 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Ordering Information (continued)
4K x 9 Low Voltage Synchronous FIFO
Speed (ns)
15
25
Ordering Code
Package Name
Package Type
CY7C4241V-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4241V-15AXC
A32
32-Lead Pb-Free Thin Quad Flatpack
CY7C4241V-15JXC
J65
32-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C4241V-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4241V-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4241V-25AXC
A32
32-Lead Pb-Free Thin Quad Flatpack
CY7C4241V-25JC
J65
32-Lead Plastic Leaded Chip Carrier
Operating Range
Commercial
Commercial
8K x 9 Low Voltage Synchronous FIFO
Speed (ns)
15
25
Ordering Code
Package Name
Package Type
CY7C4251V-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4251V-15AXC
A32
32-Lead Pb-Free Thin Quad Flatpack
CY7C4251V-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4251V-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4251V-25AXC
A32
32-Lead Pb-Free Thin Quad Flatpack
Operating Range
Commercial
Commercial
Package Diagrams
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
32-Lead Pb-Free Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
Document #: 38-06010 Rev. *B
Page 16 of 18
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Package Diagrams (continued)
32-Lead Plastic Leaded Chip Carrier J65
32-Lead Pb-Free Plastic Leaded Chip Carrier J65
51-85002-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06010 Rev. *B
Page 17 of 18
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Document History Page
Document Title: CY7C4421V/4201V/4211V/4221V/CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9
Synchronous FIFOs
Document Number: 38-06010
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
106471
09/10/01
SZV
Change from Spec number: 38-00622 to 38-06010
*A
127857
08/25/03
FSG
Fixed empty flag timing diagram
Fixed switching waveform diagram typo
*B
384573
See ECN
ESH
Added Pb-Free logo to top of front page
Inserted industrial temperature range into operating range
Added parts CY7C4251V-25AXC, CY7C4251V-15AXC,
CY7C4241V-15AXC, CY7C4241V-15JXC, CY7C4241V-25XC,
CY7C4231V-25AXC, CY7C4221V-15AI, CY7C4211V-15AXI,
CY7C4201V-15AXC to ordering information.
Document #: 38-06010 Rev. *B
Page 18 of 18
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