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CY7C4245-25JC

CY7C4245-25JC

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    LCC68

  • 描述:

    FIFO, 4KX18, 15NS, SYNCHRONOUS

  • 数据手册
  • 价格&库存
CY7C4245-25JC 数据手册
fax id: 5410 1CY 7C42 25 CY7C4425/4205/4215 CY7C4225/4235/4245 64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • 64 x 18 (CY7C4425) • 256 x 18 (CY7C4205) • 512 x 18 (CY7C4215) • 1K x 18 (CY7C4225) • 2K x 18 (CY7C4235) • 4K x 18 (CY7C4245) • High-speed 100-MHz operation (10 ns read/write cycle time) • Low power (ICC =45 mA) • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and Programmable Almost Empty/Almost Full status flags • TTL-compatible • Retransmit function • Output Enable (OE) pin • Independent read and write enable pins • Center power and ground for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • Space saving 64-pin 10x10 TQFP, and 14x14 TQFP • 68-pin PLCC Functional Description The CY7C42X5 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722x5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is Cypress Semiconductor Corporation • controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C42X5 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. The CY7C42X5 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it will be activated. The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.65µ N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 3901 North First Street • San Jose • CA 95134 • 408-943-2600 April 1995 - Revised August 18, 1997 CY7C4425/4205/4215 CY7C4225/4235/4245 D0 Logic Block Diagram – 17 INPUT REGISTER WCLK WEN FLAG PROGRAM REGISTER WRITE CONTROL DUAL PORT RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18 WRITE POINTER RS FF EF FLAG LOGIC PAE PAF SMODE READ POINTER RESET LOGIC FL/RT WXI WXO/HF RXI RXO THREE–STATE OUTPUT REGISTER EXPANSION LOGIC READ CONTROL OE 42X5–1 Q0 – 17 RCLK REN Pin Configurations 21 22 23 24 25 26 REN LD OE RS VCC GND EF Q17 Q16 GND Q15 VCC/SMODE D16 D17 GND RCLK GND Q15 Q16 VCC Q17 EF GND 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 VCC/SMODE Q14 Q13 47 46 45 44 Q6 Q5 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC GND Q4 D15 D14 D13 D12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 3 VCC RCLK REN LD OE RS 4 CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245 CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC 2 Q3 Q0 Q1 GND Q2 PAE 42x5–2 FL/RT WCLK WEN WXI VCC PAF RXI FF WXO/HF RXO VCC Q2 Q3 GND Q0 Q1 WXO/HF RXO RXI FF PAF VCC WEN WXI WCLK 2728 2930 3132 33 34 35 36 37 38 3940 4142 43 PAE FL/RT D3 D2 D1 D0 6 5 10 11 12 13 14 15 16 17 18 19 20 TQFP Top View 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 8 7 D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 GND D17 D16 D15 PLCC Top View 42X5–3 CY7C4425/4205/4215 CY7C4225/4235/4245 Selection Guide 7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35 100 66.7 40 28.6 Maximum Access Time (ns) 8 10 15 20 Minimum Cycle Time (ns) 10 15 25 35 Maximum Frequency (MHz) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Operating Current (ICC2) (mA) @ freq=20MHz Packages 4 6 7 1 1 2 8 10 15 20 Commercial 45 45 45 45 Industrial 50 50 50 50 CY7C4425 Density 3 0.5 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18 68-pin PLCC 64-pin TQFP (10x10/14x14) 68-pin PLCC 64-pin TQFP (10x10/14x14) 68-pin PLCC 64-pin TQFP (10x10/14x14) 68-pin PLCC 64-pin TQFP (10x10/14x14) 68-pin PLCC 64-pin TQFP (10x10/14x14) 68-pin PLCC 64-pin TQFP (10x10/14x14) Pin Definitions Signal Name Description I/O Function D0–17 Data Inputs I Data inputs for an 18-bit bus Q 0–17 Data Outputs O Data outputs for an 18-bit bus WEN Write Enable I Enables the WCLK input REN Read Enable I Enables the RCLK input WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register. WXO/HF Write Expansion Out/Half Full Flag O Dual-Mode Pin: Single device or width expansion - Half Full status flag. Cascaded - Write Expansion Out signal, connected to WXI of next device. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable Almost Empty O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE is asynchronous when V CC/SMODE is tied to V CC; it is synchronized to RCLK when V CC/SMODE is tied to V SS. PAF Programmable Almost Full O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is asynchronous when V CC/SMODE is tied to V CC; it is synchronized to WCLK when V CC/SMODE is tied to VSS. LD Load I When LD is LOW, D 0 - 17 (O 0 - 17) are written (read) into (from) the programmable-flag-offset register. FL/RT First Load/ Retransmit I Dual-Mode Pin: Cascaded - The first device in the daisy chain will have FL tied to V SS; all other devices will have FL tied to V CC. In standard mode of width expansion, FL is tied to V SS on all devices. Not Cascaded - Tied to VSS. Retransmit function is also available in standalone mode by strobing RT. WXI Write Expansion Input I Cascaded - Connected to WXO of previous device. Not Cascaded - Tied to VSS. 3 CY7C4425/4205/4215 CY7C4225/4235/4245 Pin Definitions (continued) Signal Name Description I/O Function RXI Read Expansion Input I Cascaded - Connected to RXO of previous device. Not Cascaded - Tied to VSS. RXO Read Expansion Output O Cascaded - Connected to RXI of next device. RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. VCC/SMODE Synchronous Almost Empty/ Almost Full Flags I Dual-Mode Pin Asynchronous Almost Empty/Almost Full flags - tied to VCC. Synchronous Almost Empty/Almost Full flags - tied to V SS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................−65°C to +150° C Latch-Up Current ..................................................... >200 mA Operating Range Ambient Temperature with Power Applied.................................................−55°C to +125° C Supply Voltage to Ground Potential .................−0.5V to +7.0V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V Commercial 0° C to +70° C 5V ± 10% Industrial[1] −40° C to +85 ° C 5V ± 10% DC Input Voltage .................................................−3.0V to +7.0V Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = −2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH [3] Input HIGH Voltage [3] Input LOW Voltage 7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35 Min. Min. Min. Min. Max. 2.4 0.4 2.2 Max. 2.4 0.4 VCC 2.2 Max. 2.4 0.4 VCC 2.2 Max. 2.4 VCC 2.2 Unit V 0.4 V VCC V −3.0 0.8 −3.0 0.8 −3.0 0.8 −3.0 0.8 V IIX Input Leakage Current VCC = Max. −10 +10 −10 +10 −10 +10 −10 +10 µA IOS[4] Output Short Circuit Current VCC = Max., V OUT = GND −90 IOZL I OZH Output OFF, High Z Current OE > VIH, VSS < VO < VCC −10 ICC2[5] Operating Current VCC = Max., IOUT = 0 mA Com’l 45 45 Ind 50 VCC = Max., IOUT = 0 mA Com’l Ind VIL [6] ISB Standby Current −90 45 45 mA 50 50 50 mA 10 10 10 10 mA 15 15 15 15 mA +10 −10 mA µA +10 −10 −90 +10 +10 −10 −90 Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. The V IH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or V SS. 4. Test no more than one output at a time for not more than one second. 5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 6. All input signals are connected to VCC . All outputs are unloaded. 4 CY7C4425/4205/4215 CY7C4225/4235/4245 Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0V Max. Unit 5 pF 7 pF AC Test Loads and Waveforms[8, 9] R11.1K Ω ALL INPUT PULSES 5V OUTPUT 3.0V R2 680Ω CL INCLUDING JIG AND SCOPE Equivalent to: THÉ EVENIN 90% 10% 90% 10% GND < 3 ns < 3 ns 42X5–4 42X5–5 EQUIVALENT 410Ω OUTPUT 1.91V Notes: 7. Tested initially and after any design or process changes that may affect these parameters. 8. CL = 30 pF for all AC parameters except for tOHZ. 9. CL = 5 pF for t OHZ . Switching Characteristics Over the Operating Range Parameter Description 7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35 Min. Min. Min. Min. Max. 100 Max. tA Data Access Time tCLK Clock Cycle Time 10 15 25 35 ns tCLKH Clock HIGH Time 4.5 6 10 14 ns tCLKL Clock LOW Time 4.5 6 10 14 ns tDS Data Set-Up Time 3 4 6 7 ns tDH Data Hold Time 0.5 1 1 2 ns tENS Enable Set-Up Time tENH Enable Hold Time 8 2 10 40 Max. Unit Clock Cycle Frequency 2 66.7 Max. tS 2 15 2 28.6 MHz 20 ns 3 4 6 7 ns 0.5 1 1 2 ns tRS Reset Pulse Width[10] 10 15 25 35 ns tRSR Reset Recovery Time 8 tRSF Reset to Flag and Output Time tPRT Retransmit Pulse Width 12 15 25 35 ns tRTR Retransmit Recovery Time 12 15 25 35 ns 0 0 0 0 ns 10 10 Z[11] 15 15 20 25 ns 35 ns tOLZ Output Enable to Output in Low tOE Output Enable to Output Valid 3 7 3 8 3 12 3 15 ns tOHZ Output Enable to Output in High Z[12] 3 7 3 8 3 12 3 15 ns tWFF Write Clock to Full Flag tREF tPAFasynch 8 10 15 20 ns Read Clock to Empty Flag 8 10 15 20 ns Clock to Programmable Almost-Full Flag[12] (Asynchronous mode, VCC/SMODE tied to VCC) 12 16 20 25 ns 5 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Characteristics Over the Operating Range (continued) Parameter Description 7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35 Min. Min. Min. Min. Max. Max. Max. Max. Unit tPAFsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 8 10 15 20 ns tPAEasynch Clock to Programmable Almost-Empty Flag[12] (Asynchronous mode, VCC/SMODE tied to VCC) 12 16 20 25 ns tPAEsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 8 10 15 20 ns tHF Clock to Half-Full Flag 12 16 20 25 ns tXO Clock to Expansion Out 20 ns tXI Expansion in Pulse Width 3 6.5 10 14 ns tXIS Expansion in Set-Up Time 4.5 5 10 15 ns tSKEW1 Skew Time between Read Clock and Write Clock for Full Flag 5 6 10 12 ns tSKEW2 Skew Time between Read Clock and Write Clock for Empty Flag 5 6 10 12 ns tSKEW3 Skew Time between Read Clock and Write Clock for Programmable Almost Empty and Programmable Almost Full Flags. 10 15 18 20 ns 7 10 15 Switching Waveforms Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0 –D17 tENS tENH WEN NO OPERATION tWFF tWFF FF tSKEW1[13] RCLK REN 42X5–6 Notes: 10. Pulse widths less than minimum values are not allowed. 11. Values guaranteed by design, not currently tested. 12. PAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E). 13. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. 6 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Waveforms (continued) Read Cycle Timing tCLK tCLKH tCLKL RCLK tENS tENH REN NO OPERATION tREF tREF EF tA VALID DATA Q0 –Q17 tOLZ tOHZ tOE OE tSKEW2[14] WCLK WEN 42X5–7 Reset Timing[15] tRS RS tRSR REN, WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF OE=1[16] Q0 - Q17 OE=0 42X5–8 Notes: 14. .tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge. 15. The clocks (RCLK, WCLK) can be free-running during reset. 16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 7 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK tDS D0 –D17 D0 (FIRSTVALID WRITE) D1 D2 D3 D4 tENS [17] tFRL WEN tSKEW2 RCLK tREF EF REN tA tA Q0 –Q17 [18] D0 D1 tOLZ tOE OE 42X5–9 Empty Flag Timing WCLK tDS tDS D0 D0 –D17 tENS D1 tENH tENS tENH WEN tFRL[17] tFRL[17] RCLK tSKEW2 tREF tREF tREF tSKEW2 EF REN OE tA D0 Q0 –Q17 42X5–10 Notes: 17. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 18. The first word is available the cycle after EF goes HIGH, always. 8 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Waveforms (continued) Full Flag Timing NO WRITE NO WRITE WCLK tSKEW1 [13] tDS tSKEW1 [13] DATA WRITE DATA WRITE D0 –D17 tWFF tWFF tWFF FF WEN RCLK tENH tENH tENS tENS REN OE LOW tA Q0 –Q17 tA DATAREAD DATA IN OUTPUT REGISTER NEXT DATA READ 42X5–11 Half-Full Flag Timing tCLKL tCLKH WCLK tENS tENH WEN tHF HF HALF FULL+1 OR MORE HALF FULL OR LESS HALF FULL OR LESS tHF RCLK tENS REN 42X5–12 9 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Waveforms (continued) Programmable Almost Empty Flag Timing tCLKL tCLKH WCLK tENS tENH WEN tPAE PAE] [19] n+1 WORDS IN FIFO tPAE n WORDS IN FIFO RCLK tENS REN 42X5–13 Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW) tCLKL tCLKH WCLK tENS tENH WEN WEN2 tENS tENH PAE Note 20 N + 1 WORDS INFIFO tSKEW3 [21] tPAEsynch Note 22 tPAEsynch RCLK tENS tENS tENH REN 42X5–14 Notes: 19. PAE offset – n. Number of data words into FIFO already = n. 20. PAE offset – n. 21. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW. 10 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Waveforms (continued) Programmable Almost Full Flag Timing tCLKL tCLKH Note 23 WCLK tENS tENH WEN tPAF PAF FULL − M WORDS IN FIFO [25] [24] FULL − M + 1 WORDS IN FIFO [26] tPAF RCLK tENS REN 42X5–15 Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW)) tCLKH tCLKL Note 27 WCLK tENS tENH WEN Note 28 WEN2 tPAF tENS tENH PAF FULL − M WORDS [29] IN FIFO FULL- M+1Ω ORDS INFIFO tSKEW3[30] tPAFsynch RCLK tENS tENS tENH REN 42X5–16 Notes: 23. PAF offset = m. Number of data words written into FIFO already = 64 – m + 1 for the CY7C4425, 256 – m + 1 for the CY7C4205, 512 – m + 1 for the CY7C4215. 1024 – m + 1 for the CY7C4225, 2048 – m + 1 for the CY7C4235, and 4096 – m + 1 for the CY7C4245. 24. PAF is offset = m. 25. 64 – m words in CY7C4425, 256 – m words inCY7C4205, 512 – m word in CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235, and 4096 – m words in CY7C4245. 26. 64 – m + 1 words in CY7C4425, 256 – m + 1 words in CY7C4205, 512 – m +1 words in CY7C4215, 1024 – m + 1 CY7C4225, 2048 – m + 1 in CY74235, and 4096 – m + 1 words in CY7C4245. 27. If a write is performed on this rising edge of the write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW. 28. PAF offset = m. 29. 64 – m words in CY7C4425, 256 – m words in FIFO for CY7C4205, 512 – m word in CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235, and 4096 – m words in CY7C4245. 30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge. 11 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Waveforms (continued) Write Programmable Registers tCLK tCLKL tCLKH WCLK tENS tENH LD tENS WEN tDS tDH PAE OFFSET D0 –D17 PAE OFFSET PAF OFFSET D0 –D11 42X5–17 Read Programmable Registers tCLK tCLKL tCLKH RCLK tENS tENH LD tENS WEN tA UNKNOWN Q0 –Q17 PAE OFFSET PAF OFFSET PAE OFFSET 42X5–18 Write Expansion Out Timing tCLKH WCLK Note 31 tXO WXO tENS tXO WEN 42X5–19 Note: 31. Write to Last Physical Location. 12 CY7C4425/4205/4215 CY7C4225/4235/4245 Switching Waveforms (continued) Read Expansion Out Timing tCLKH WCLK Note 32 tXO RXO tXO tENS REN 42X5–20 Write Expansion In Timing tXI WXI WCLK tXIS 42X5–21 Read Expansion In Timing tXI RXI tXIS RCLK 42X5–22 Retransmit Timing[33, 34, 35] FL/RT tPRT tRTR REN/WEN EF/FF and all async flags HF/PAE/PAF 42X5–23 Notes: 32. Read from Last Physical Location. 33. Clocks are free running in this case. 34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. 13 CY7C4425/4205/4215 CY7C4225/4235/4245 Architecture Table 1. Write Offset Register The CY7C42X5 consists of an array of 64 to 4K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5 also includes the control signals WXI, RXI, WXO, RXO for depth expansion. WCLK[36] LD WEN 0 0 Writing to offset registers: Empty Offset Full Offset 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation Selection Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only if OE is asserted. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. Note: 36. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. FIFO Operation Flag Operation When the WEN signal is active (LOW), data present on the D0–17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the FIFO memory will be presented on the Q0–17 outputs. New data will be presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. The CY7C42X5 devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to VSS. Full Flag The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. An output enable (OE) pin is provided to three-state the Q0–17 outputs when OE is deasserted. When OE is enabled (LOW), data in the output register will be available to the Q0–17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. Empty Flag The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0–17 outputs even after additional reads occur. The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Programming The CY7C42X5 features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. Programmable Almost Empty/Almost Full Flag The CY7C42X5 devices contain two 12-bit offset registers. Data present on D0–11 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO’s flags, the default offset values are used (see Table 2). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs D0–11 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset register (see Table 1). Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the LD pin HIGH, the FIFO is returned to normal read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK). 14 CY7C4425/4205/4215 CY7C4225/4235/4245 every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Table 2. Flag Truth Table. Number of Words in FIFO 7C4425 - 64 x 18 0 7C4205 - 256 x 18 7C4215 - 512 x 18 0 [37 0 [37] [37] FF PAF HF PAE EF H H H L L 1 to n 1 to n 1 to n H H H L H (n+1) to 32 (n+1) to 128 (n+1) to 256 H H H H H 33 to (64 – (m+1)) 129 to (256 – (m+1)) 257 to (512 – (m+1)) H H L H H (64 – m)[38] to 63 (256 – m)[38] to 255 (512 – m)[38] to 511 H L L H H 64 256 512 L L L H H FF PAF HF PAE EF Number of Words in FIFO 7C4225 - 1K x 18 7C4235 - 2K x 18 7C4245 - 4K x 18 0 0 0 H H H L L 1 to n[37] 1 to n[37] 1 to n[37] H H H L H (n+1) to 512 (n+1) to 1024 (n+1) to 2048 H H H H H 513 to (1024 – (m+1)) 1025 to (2048 – (m+1)) 2049 to (4096 – (m+1)) H H L H H (1024 – m)[38] to 1023 (2048 – m)[38] to 2047 (4096 – m)[38] to 4095 H L L H H 1024 2048 4096 L L L H H Notes: 37. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127). 38. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127). are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags of every FIFO. This technique will avoid ready data from the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C42X5. Width Expansion Configuration The CY7C42X5 can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags RESET (RS) DATA IN (D) 36 RESET (RS) 18 18 READ CLOCK (RCLK) WRITECLOCK (WCLK) READ ENABLE (REN) WRITEENABLE (WEN) OUTPUTENABLE (OE) LOAD (LD) PROGRAMMABLE(PAE) HALF FULL FLAG (HF) FF 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 FF EF PROGRAMMABLE(PAF) EMPTYFLAG (EF) EF 18 FULL FLAG (FF) DATA OUT (Q) 36 18 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) 42X5–24 Figure 1. Block Diagram of 64x36/256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a Width Expansion Configuration. 15 CY7C4425/4205/4215 CY7C4225/4235/4245 Depth Expansion Configuration (with Programmable Flags) 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. The CY7C42X5 can easily be adapted to applications requiring more than 64/256/512/1024/2048/4096 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 1. The first device must be designated by grounding the First Load (FL) control input. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. 2. All other devices must have FL in the HIGH state. WXO RXO 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 VCC FIRSTLOAD (FL) FF EF PAE PAF WXI RXI WXO RXO 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 DATAIN (D) VCC FIRSTLOAD (FL) DATAOUT (Q) FF EF PAE PAF WXI RXI WRITECLOCK (WCLK) WXO RXO WRITE ENABLE (WEN) READ ENABLE (REN) 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 RESET(RS) LOAD (LD) FF FF PAF READ CLOCK (RCLK) OUTPUT ENABLE (OE) EF EF PAFWXI RXIPAE PAE 42X5–23 FIRSTLOAD (FL) Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration. 16 CY7C4425/4205/4215 CY7C4225/4235/4245 Typical AC and DC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 1.2 1.0 VIN =3.0V TA =25°C f=100 MHz 0.8 0.6 1.1 1.1 1.0 VIN =3.0V VCC =5.0V f=100 MHz 0.9 0.8 4 5 4.5 5.5 −55 6 SUPPLY VOLTAGE (V) 25 1.0 0.9 0.8 5.5 1.0 VCC =5.0V .75 25 3 4 OUTPUT VOLTAGE (V) 5 OUTPUT SINK CURENT (mA) 35 2 125 75 100 120 140 120 100 80 TA =25°C VCC =5.0V 60 40 20 0 0 1 2 3 OUTPUT VOLTAGE (V) 17 25 10 −5.0 .50 VCC =5.0V TA =25°C 275 550 825 CAPACITANCE (pF) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE TA =25°C VCC =5.0V 1 25 AMBIENT TEMPERATURE (°C) 55 50 TYPICAL tA CHANGE vs. OUTPUT LOADING 1.25 OUTPUT SOURCECURRENT vs. OUTPUT VOLTAGE 0 25 40 0.5 −55 6 SUPPLY VOLTAGE (V) 45 0.7 FREQUENCY (MHz) NORMALIZED tA NORMALIZED tA 1.1 5 0.8 0.6 0 125 1.50 TA =25°C 4.5 0.9 NORMALIZED tA vs. AMBIENT TEMPERATURE 1.2 4 VCC =5.0V TA =25°C VIN =3.0V 1.0 AMBIENT TEMPERATURE (°C) NORMALIZED tA vs.SUPPLY VOLTAGE NORMALIZED tA NORMALIZED ICC NORMALIZED ICC NORMALIZED ICC 1.4 OUTPUTS OURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. FREQUENCY NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 4 1000 CY7C4425/4205/4215 CY7C4225/4235/4245 Ordering Information 64 x 18 Synchronous FIFO Speed (ns) 10 15 25 35 Ordering Code Package Name Package Type CY7C4425-10AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-10ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4425-10AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-10ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4425-15AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-15ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4425-15AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-15ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4425-25AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-25ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4425-25AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-25ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4425-35AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-35ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4425-35AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4425-35ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4425-35JI J81 68-Lead Plastic Leaded Chip Carrier 18 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial CY7C4425/4205/4215 CY7C4225/4235/4245 256 x 18 Synchronous FIFO Speed (ns) 10 15 25 35 Ordering Code Package Name Package Type CY7C4205-10AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-10ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4205-10AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-10ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4205-15AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-15ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4205-15AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-15ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4205-25AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-25ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4205-25AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-25ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4205-35AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-35ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4205-35AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205-35ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4205-35JI J81 68-Lead Plastic Leaded Chip Carrier 19 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial CY7C4425/4205/4215 CY7C4225/4235/4245 512 x 18 Synchronous FIFO Speed (ns) 10 15 25 35 Ordering Code Package Name Package Type CY7C4215-10AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-10ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4215-10AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-10ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4215-15AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-15ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4215-15AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-15ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4215-25AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-25ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4215-25AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-25ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4215-35AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-35ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4215-35AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4215-35ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4215-35JI J81 68-Lead Plastic Leaded Chip Carrier 20 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial CY7C4425/4205/4215 CY7C4225/4235/4245 1K x 18 Synchronous FIFO Speed (ns) 10 15 25 35 Ordering Code Package Name Package Type CY7C4225-10AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-10ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4225-10AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-10ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4225-15AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-15ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4225-15AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-15ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4225-25AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-25ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4225-25AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-25ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4225-35AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-35ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4225-35AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4225-35ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4225-35JI J81 68-Lead Plastic Leaded Chip Carrier 21 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial CY7C4425/4205/4215 CY7C4225/4235/4245 2K x 18 Synchronous FIFO Speed (ns) 10 15 25 35 Ordering Code Package Name Package Type CY7C4235-10AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-10ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4235-10AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-10ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4235-15AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-15ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4235-15AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-15ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4235-25AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-25ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4235-25AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-25ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4235-35AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-35ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4235-35AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4235-35ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4235-35JI J81 68-Lead Plastic Leaded Chip Carrier 22 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial CY7C4425/4205/4215 CY7C4225/4235/4245 4K x 18 Synchronous FIFO Speed (ns) 10 15 25 35 Ordering Code Package Name Package Type CY7C4245-10AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-10ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4245-10AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-10ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4245-15AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-15ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4245-15AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-15ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4245-25AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-25ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4245-25AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-25ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4245-35AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-35ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4245-35AI A65 64-Lead 14x14 Thin Quad Flatpack CY7C4245-35ASI A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245-35JI J81 68-Lead Plastic Leaded Chip Carrier 23 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial CY7C4425/4205/4215 CY7C4225/4235/4245 Package Diagrams 64-Lead Thin Plastic Quad Flat Pack A65 64-Pin Thin Quad Flat Pack A64 24 CY7C4425/4205/4215 CY7C4225/4235/4245 Package Diagrams (continued) 68-Lead Plastic Leaded Chip Carrier J81 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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