CY7C4261-15JXCT

CY7C4261, CY7C4271 16K/32K x 9 Deep Sync FIFOs Features Functional Description ■ High speed, low power, first-in first-out (FIFO) memories ■ 16K × 9 (CY7C4261) ■ 32K × 9 (CY7C4271) ■ 0.5 micron CMOS for optimum speed and power ■ High speed 100 MHz operation (10 ns read/write cycle times) ■ Low power — ICC = 35 mA The CY7C4261/71 are high speed, low power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71 are pin compatible to the CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can be cascaded to increase FIFO width. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering. ■ Fully asynchronous and simultaneous read and write operation ■ Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags ■ TTL compatible ■ Output Enable (OE) pins ■ Independent read and write enable pins ■ Center power and ground pins for reduced noise ■ Supports free running 50% duty cycle clock inputs ■ Width Expansion Capability ■ Military temp SMD Offering – CY7C4271-15LMB ■ 32-pin PLCC/LCC and 32-pin TQFP ■ Pin compatible density upgrade to CY7C42X1 family ■ Pin compatible density upgrade to IDT72201/11/21/31/41/51 ■ Pb-Free Packages Available These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free running read clock (RCLK) and two read enable pins (REN1, REN2). In addition, the CY7C4261/71 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. Selection Guide Parameter 7C4261/71-10 7C4261/71-15 7C4261/71-25 7C4261/71-35 Unit 100 66.7 40 28.6 MHz Maximum Access Time 8 10 15 20 ns Minimum Cycle Time 10 15 25 35 ns Maximum Frequency Minimum Data or Enable Setup 3 4 6 7 ns Minimum Data or Enable Hold 0.5 1 1 2 ns Maximum Flag Delay 8 10 15 20 ns Active Power Supply Commercial Current (ICC1) Industrial/ Military 35 35 35 35 mA 40 40 40 40 Parameter CY7C4261 CY7C4271 Density 16K × 9 32K × 9 Package 32-pin PLCC, TQFP 32-pin LCC, PLCC, TQFP Cypress Semiconductor Corporation Document #: 38-06015 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 22, 2008 [+] Feedback CY7C4261, CY7C4261 Logic Block Diagram D0–8 INPUT REGISTER WCLK WEN1 WEN2/LD FLAG PROGRAM REGISTER WRITE CONTROL FLAG LOGIC WRITE POINTER RS RAM ARRAY 16K x 9 32K x 9 EF PAE PAF FF READ POINTER RESET LOGIC THREE-STATE OUTPUT REGISTER READ CONTROL OE Q0–8 Document #: 38-06015 Rev. *D RCLK REN1 REN2 Page 2 of 19 [+] Feedback CY7C4261, CY7C4261 Pinouts D8 RS D7 D6 D5 32 31 30 29 28 27 26 25 RS WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 D1 1 24 WEN1 D0 2 23 WCLK PAF 3 22 WEN2/LD PAE 4 21 GND 5 REN1 6 19 VCC Q8 Q7 RCLK 7 18 Q6 REN2 8 17 Q5 CY7C4261 CY7C4271 20 9 10 11 12 13 14 15 16 Q3 Q4 Q2 Q1 Q0 FF EF OE Q3 Q4 EF FF Q0 Q1 Q2 REN1 RCLK REN2 OE 4 3 2 1 32 31 30 29 5 28 6 27 7 8 CY7C4261 26 9 25 CY7C4271 24 10 11 23 22 12 21 13 14 15 16 17 18 19 20 D4 D2 D3 D4 D5 D6 D7 D8 D1 D0 PAF PAE GND D3 Figure 2. Pin Diagram - 32-Pin TQFP (Top View) D2 Figure 1. Pin Diagram - 32-Pin PLCC/LCC (Top View) Table 1. Pin Definitions - 32-Pin Device Signal Name Description IO Description D0−8 Data Inputs I Data Inputs for 9-bit bus. Q0−8 Data Outputs O Data Outputs for 9-bit bus. WEN1 Write Enable 1 I The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. Write Enable 2 WEN2/LD Dual Mode Pin Load I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data is not written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. REN1, REN2 Read Enable Inputs I Enables the device for Read operation. Both REN1 and REN2 must be asserted to allow a read operation. WCLK Write Clock I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable Almost Empty O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAE is synchronized to RCLK. PAF Programmable Almost Full O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is synchronized to WCLK. RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power up. OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high impedance) state. Document #: 38-06015 Rev. *D Page 3 of 19 [+] Feedback CY7C4261, CY7C4261 Functional Description The CY7C4261/71 provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty + 7 and Full – 7. The flags are synchronous, that is, they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. All configurations are fabricated using an advanced 0.5μ CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Architecture The CY7C4261/71 consists of an array of 16K to 32K words of nine bits each (implemented by a dual port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF). Resetting the FIFO Upon power up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0−8) go LOW tRSF after the rising edge of RS. For the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW. FIFO Operation When the WEN1 signal is active LOW, WEN2 is active HIGH, and FF is active HIGH, data present on the D0−8 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN1 and REN2 signals are active LOW and EF is active HIGH, data in the FIFO memory is presented on the Q0−8 outputs. New data is presented on each rising edge of RCLK while REN1 and REN2 are active. REN1 and REN2 must set up tENS before RCLK for it to be a valid read function. WEN1 and WEN2 must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0−8 outputs when OE is asserted. When OE is enabled (LOW), data in the output register is available to the Q0−8 outputs after tOE. If devices are cascaded, the OE function only outputs data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0−8 outputs even after additional reads occur. Document #: 38-06015 Rev. *D Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable control pin. In this configuration, when Write Enable 1 (WEN1) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored is the RAM array sequentially and independently of any on-going read operation. Write Enable 2/Load (WEN2/LD). This is a dual purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows for depth expansion. If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS = LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any ongoing read operation. Programming When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C4261/71 for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WEN1 are LOW writes data to the empty LSB register again. Figure 3 shows the register sizes and default values for the various device types. Figure 3. Offset Register Location and Default Values 16K × 9 8 32K × 9 0 7 8 Empty Offset (LSB) Reg. Default Value = 007h Empty Offset (LSB) Reg. Default Value = 007h 0 5 8 0 7 (MSB) 000000 8 (MSB) 0000000 0 7 8 Full Offset (LSB) Reg Default Value = 007h 8 (MSB) 000000 0 7 Full Offset (LSB) Reg Default Value = 007h 0 5 0 6 8 8 0 6 (MSB) 0000000 Page 4 of 19 [+] Feedback CY7C4261, CY7C4261 It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written, and then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads must not be performed simultaneously on the offset registers. Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as described in Table 2 or the default values are used, the programmable almost-empty flag (PAE) (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. Table 2. Writing the Offset Registers LD WEN 0 0 WCLK[1] Selection Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation Table 3. Status Flags Number of Words in FIFO CY7C4261 0 CY7C4271 FF PAF PAE EF H H L L H H L H H H H H (16384 − m)[3] to 16383 (32768 − m)[3] to 32767 H L H H 16384 L H H 1 to n 0 [2] (n + 1) to (16384 − (m + 1)) 1 to n [2] (n + 1) to (32768 − (m + 1)) 32768 L Width Expansion Configuration Word width may be increased by simply connecting the corresponding input controls signals of multiple devices. A composite flag must be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 4 on page 6 demonstrates a 18-bit word width by using two CY7C4261/71s. Any word width can be attained by adding additional CY7C4261/71s. When the CY7C4261/71 is in a Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (see Figure 4 on page 6). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. Flag Operation The CY7C4261/71 devices provide four flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The number formed by the empty offset least significant bit register and empty offset most significant bit register is referred to as n and determines the operation of PAE. PAF is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n+1) or greater unread words. The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4261 (16K-m) and CY7C4271 (32K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. The Full Flag (FF) goes LOW when the device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN1 and WEN2/LD. FF is synchronized to WCLK, that is, it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) goes LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2. EF is synchronized to RCLK, that is, it is exclusively updated by each rising edge of RCLK. Notes 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK. 2. n = Empty Offset (n = 7 default value). 3. m = Full Offset (m = 7 default value). Document #: 38-06015 Rev. *D Page 5 of 19 [+] Feedback CY7C4261, CY7C4261 Figure 4. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width Expansion Configuration RESET (RS) DATAIN (D) 18 RESET (RS) 9 9 READ CLOCK (RCLK) WRITECLOCK (WCLK) READ ENABLE 1 (REN1) WRITE ENABLE 1(WEN1) OUTPUT ENABLE (OE) WRITE ENABLE 2/LOAD (WEN2/LD) PROGRAMMABLE(PAF) CY7C4261/71 CY7C4261/71 EMPTY FLAG (EF) #2 FULL FLAG (FF) # 1 FF FF EF EF 9 FULL FLAG (FF) # 2 DATA OUT (Q) 18 9 Read Enable 2 (REN2) Document #: 38-06015 Rev. *D PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 Read Enable 2 (REN2) Page 6 of 19 [+] Feedback CY7C4261, CY7C4261 Maximum Ratings Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Exceeding maximum ratings[4] may impair the useful life of the device. These user guidelines are not tested. Latch-up Current...................................................... >200 mA Operating Range Storage Temperature .......................................−65°C to +150°C Ambient Temperature with Power Applied....................................................−55°C to +125°C Ambient Temperature VCC Commercial Range 0°C to +70°C 5V ± 10% Supply Voltage to Ground Potential .................−0.5V to +7.0V Industrial[5] −40°C to +85°C 5V ± 10% DC Voltage Applied to Outputs in High-Z State ........................................... −0.5V to VCC + 0.5V Military −55°C to +125°C 5V ± 10% DC Input Voltage ....................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW) ............................. 20 mA Electrical Characteristics Over the Operating Range [6] Parameter Description Test Conditions 7C4261/71-10 7C4261/71-15 7C4261/71-25 7C4261/71-35 Min Max 2.4 Min Max 2.4 Min Max 2.4 Min Max VOH Output HIGH Voltage VCC = Min, IOH = −2.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage (Commercial/Industrial) 2.0 VCC 2.0 VCC 2.0 VCC VIH Input HIGH Voltage (Military) 2.2 VCC 2.2 VCC 2.2 VIL Input LOW Voltage −0.5 0.8 −0.5 0.8 IIX Input Leakage Current VCC = Max. −10 +10 −10 +10 IOZL IOZH Output OFF, High Z Current OE > VIH, VSS < VO< VCC −10 +10 −10 +10 ICC1[7] Active Power Supply Current Com’l Ind/Mil 40 40 40 40 mA ISB[8] Average Standby Current Com’l 10 10 10 10 mA Ind/Mil 15 15 15 15 mA 0.4 0.4 35 2.4 Unit 0.4 V 0.4 V 2.0 VCC V VCC 2.2 VCC V −0.5 0.8 −0.5 0.8 V −10 +10 −10 +10 μA −10 +10 −10 +10 μA 35 mA 35 35 Capacitance Parameter[9] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max Unit 5 pF 7 pF Notes 4. The voltage on any input or IO pin cannot exceed the power pin during power up. 5. TA is the “instant on” case temperature. 6. See the last page of this specification for Group A subgroup testing information. 7. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. ICC1(typical) = (20 mA + (freq – 20 MHz) * (0.7 mA/MHz)). 8. All inputs = VCC – 0.2V, except WCLK and RCLK (which are switching at frequency = 20 MHz). All outputs are unloaded. 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06015 Rev. *D Page 7 of 19 [+] Feedback CY7C4261, CY7C4261 Figure 5. AC Test Loads and Waveforms [10, 11] R1 1.1KΩ ALL INPUT PULSES 5V OUTPUT 3.0V GND ≤3 ns R2 680Ω INCLUDING CL JIG AND SCOPE 90% 10% 90% 10% ≤ 3 ns Equivalent to: THÉVENIN EQUIVALENT 420Ω OUTPUT 1.91V Switching Characteristics Over the Operating Range Parameter Description 7C4261/71-10 7C4261/71-15 7C4261/71-25 Min Min Min Max Max Max 7C4261/71- 35 Min Max Unit tS Clock Cycle Frequency tA Data Access Time 2 tCLK Clock Cycle Time 10 15 25 35 ns tCLKH Clock HIGH Time 4.5 6 10 14 ns tCLKL Clock LOW Time 4.5 6 10 14 ns tDS Data Setup Time 3 4 6 7 ns tDH Data Hold Time 0.5 1 1 2 ns tENS Enable Setup Time 3 4 6 7 ns tENH Enable Hold Time 0.5 1 1 2 ns 10 15 25 35 ns 100 Width[12] 8 66.7 2 10 40 2 15 28.6 2 20 MHz ns tRS Reset Pulse tRSS Reset Setup Time 8 10 15 20 ns tRSR Reset Recovery Time 8 10 15 20 ns tRSF Reset to Flag and Output Time tOLZ Output Enable to Output in Low tOE Output Enable to Output Valid 10 Z[13] Z[13] 0 15 0 25 0 35 0 ns ns 3 7 3 8 3 12 3 15 ns 3 7 3 8 3 12 3 15 ns tOHZ Output Enable to Output in High tWFF Write Clock to Full Flag 8 10 15 20 ns tREF Read Clock to Empty Flag 8 10 15 20 ns tPAF Clock to Programmable Almost Full Flag 8 10 15 20 ns tPAE Clock to Programmable Almost Full Flag 8 10 15 20 ns tSKEW1 Skew Time between Read Clock and Write Clock for Empty Flag and Full Flag 5 6 10 12 ns tSKEW2 Skew Time between Read Clock and Write Clock for Almost Empty Flag and Almost Full Flag 10 15 18 20 ns Notes 10. 5CL = 30 pF for all AC parameters except for tOHZ. 11. 5CL = 5 pF for tOHZ. 12. Pulse widths less than minimum values are not allowed. 13. Values guaranteed by design, not currently tested. Document #: 38-06015 Rev. *D Page 8 of 19 [+] Feedback CY7C4261, CY7C4261 Switching Waveforms Figure 6. Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0 –D17 tENS tENH WEN1 NO OPERATION NO OPERATION WEN2 (if applicable) tWFF tWFF FF tSKEW1 [14] RCLK REN1, REN2 Figure 7. Read Cycle Timing tCKL tCLKH tCLKL RCLK tENS tENH REN1, REN2 NO OPERATION tREF tREF EF tA Q0 –Q17 VALID DATA tOLZ tOHZ tOE OE tSKEW1[15] WCLK WEN1 WEN2 Notes 14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge. Document #: 38-06015 Rev. *D Page 9 of 19 [+] Feedback CY7C4261, CY7C4261 Switching Waveforms (continued) Figure 8. Reset Timing [16] tRS RS tRSS tRSR tRSS tRSR tRSS tRSR REN1, REN2 WEN1 WEN2/LD [18] tRSF EF,PAE tRSF FF,PAF tRSF OE = 1[17] Q0 - Q8 OE = 0 Figure 9. First Data Word Latency after Reset with Read and Write WCLK tDS D0 –D8 D0(FIRST VALID WRITE) D1 D2 D3 D4 tENS tFRL [19] WEN1 WEN2 (if applicable) tSKEW1 RCLK tREF EF tA [20] tA REN1, REN2 Q0 –Q8 D0 D1 tOLZ tOE OE Notes 16. The clocks (RCLK, WCLK) can be free running during reset. 17. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1. 18. Holding WEN2/LD HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the programmable flag offset registers. 19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 20. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06015 Rev. *D Page 10 of 19 [+] Feedback CY7C4261, CY7C4261 Switching Waveforms (continued) Figure 10. Empty Flag Timing WCLK tDS tDS DATA WRITE 2 DATA WRITE 1 D0 –D8 tENH tENS tENH tENS WEN1 tENS tENH tENH tENS WEN2 (if applicable) tFRL [19] tFRL [19] RCLK tREF tREF tSKEW1 tREF tSKEW1 EF REN1, REN2 LOW OE tA DATA IN OUTPUT REGISTER Q0 –Q8 DATA READ Figure 11. Full Flag Timing NO WRITE NO WRITE WCLK tSKEW1[14] [14] tDS DATA WRITE tSKEW1 DATA WRITE D0 –D8 tWFF tWFF tWFF FF WEN1 WEN2 (if applicable) RCLK tENH OE tENH tENS REN1, REN2 tENS LOW tA tA Q0 –Q8 DATA IN OUTPUT REGISTER Document #: 38-06015 Rev. *D DATA READ NEXT DATA READ Page 11 of 19 [+] Feedback CY7C4261, CY7C4261 Switching Waveforms (continued) Figure 12. Programmable Almost Empty Flag Timing tCLKL tCLKH WCLK tENS tENH WEN1 WEN2 (if applicable) tENS tENH 22 PAE tESKEW2[21] N + 1 WORDS IN FIFO 23 t PAE tPAE RCLK tENS tENS tENH REN1, REN2 Figure 13. Programmable Almost Full Flag Timing tCLKH tCLKL Note 24 WCLK tENS tENH WEN1 WEN2 (if applicable) 25 tENS tENH PAF tPAF FULL − M WORDS IN FIFO [26] FULL − (M + 1) WORDS IN FIFO tSKEW2 [27] tPAF RCLK tENS tENS tENH REN1, REN2 Notes 21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK. 22. PAE offset= n. 23. If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW 24. If a write is performed on this rising edge of the write clock, there are Full − (m−1) words of the FIFO when PAF goes LOW. 25. PAF offset = m. 26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271. 27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK. Document #: 38-06015 Rev. *D Page 12 of 19 [+] Feedback CY7C4261, CY7C4261 Switching Waveforms (continued) Figure 14. Write Programmable Registers tCLK tCLKL tCLKH WCLK tENS tENH WEN2/LD tENS WEN1 tDS tDH D0 –D8 PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB PAF OFFSET MSB Figure 15. Read Programmable Registers tCLK tCLKL tCLKH RCLK tENS tENH WEN2/LD tENS PAF OFFSET MSB REN1, REN2 tA Q0 –Q15 Document #: 38-06015 Rev. *D UNKNOWN PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB Page 13 of 19 [+] Feedback CY7C4261, CY7C4261 Figure 16. Typical AC and DC Characteristics NORMALIZED tA vs. AMBIENT TEMPERATURE NORMALIZED tA vs. SUPPLY VOLTAGE 1.60 NORMALIZED tA NORMALIZED tA 1.20 1.10 1.00 0.90 TA = 25°C 0.80 4.00 4.50 5.00 6.00 5.50 1.40 1.20 1.00 0.60 −55.00 1.00 VIN = 3.0V TA = 25°C f = 28 MHz 0.80 4.50 5.00 5.50 SUPPLY VOLTAGE (V) Document #: 38-06015 Rev. *D 6.00 125.00 1.75 NORMALIZED ICC NORMALIZED ICC NORMALIZED ICC 1.20 1.20 65.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.40 0.60 4.00 5.00 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE VCC = 5.0V 0.80 1.10 1.00 VIN = 3.0V VCC = 5.0V f = 28 MHz 0.90 0.80 −55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE (°C) 1.50 1.25 1.00 VCC = 5.0V TA = 25°C VIN = 3.0V 0.75 0.50 20.00 30.00 40.00 50.00 60.00 FREQUENCY (MHz) Page 14 of 19 [+] Feedback CY7C4261, CY7C4261 Ordering Information 16Kx9 Deep Sync FIFO Speed (ns) 10 Ordering Code 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4261-10JC 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4261-10AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4261-10JXI CY7C4261-15AC CY7C4261-15JC 25 35 Package Type CY7C4261-10AC CY7C4261-10JI 15 Package Diagram CY7C4261-15JXC 51-85002 51-85063 51-85002 32-Pin Plastic Leaded Chip Carrier Operating Range Commercial Industrial 32-Pin Plastic Leaded Chip Carrier (Pb-Free) 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) 32-Pin Plastic Leaded Chip Carrier Commercial 32-Pin Plastic Leaded Chip Carrier (Pb-Free) CY7C4261-15AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4261-15JI 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4261-25AC 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4261-25JC 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4261-25AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4261-25JI 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4261-35AC 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4261-35JC 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4261-35AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4261-35JI 51-85002 32-Pin Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial 32Kx9 Deep Sync FIFO Speed (ns) 10 15 Ordering Code 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4271-10JC 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4271-10AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4271-10JI 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4271-15AC 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4271-15AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4271-15JI 51-85002 32-Pin Plastic Leaded Chip Carrier 51-80068 32-Pin Rectangular Leadless Chip Carrier CY7C4271-25AC 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4271-25JC 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4271-25AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4271-25JI 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4271-35AC 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4271-35JC 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C4271-35AI 51-85063 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) CY7C4271-35JI 51-85002 32-Pin Plastic Leaded Chip Carrier 5962-9736101QYA Document #: 38-06015 Rev. *D Operating Range Commercial Industrial Commercial 32-Pin Thin Quad Flat Pack (7 x 7 x 1.0 mm) (Pb-Free) CY7C4271-15JC CY7C4271-15LMB 35 Package Type 51-85063 CY7C4271-15AXC 25 Package Diagram CY7C4271-10AC Industrial Military Commercial Industrial Commercial Industrial Page 15 of 19 [+] Feedback CY7C4261, CY7C4261 Table 5. Switching Characteristics (continued) Table 4. DC Characteristics Parameters Subgroups Parameters Subgroups VOH 1, 2, 3 tRFF 9, 10, 11 VOL 1, 2, 3 tWEF 9, 10, 11 VIH 1, 2, 3 tWFF 9, 10, 11 VIL Max. 1, 2, 3 tWHF 9, 10, 11 IIX 1, 2, 3 tRHF 9, 10, 11 ICC 1, 2, 3 tRAE 9, 10, 11 ICC1 1, 2, 3 tRPE 9, 10, 11 ISB1 1, 2, 3 tWAF 9, 10, 11 ISB2 1, 2, 3 tWPF 9, 10, 11 IOS 1, 2, 3 tXOL 9, 10, 11 tXOH 9, 10, 11 Table 5. Switching Characteristics Parameters Subgroups tRC 9, 10, 11 tA 9, 10, 11 tRR 9, 10, 11 tPR 9, 10, 11 tDVR 9, 10, 11 tWC 9, 10, 11 tPW 9, 10, 11 tWR 9, 10, 11 tSD 9, 10, 11 tHD 9, 10, 11 tMRSC 9, 10, 11 tPMR 9, 10, 11 tRMR 9, 10, 11 tRPW 9, 10, 11 tWPW 9, 10, 11 tRTC 9, 10, 11 tPRT 9, 10, 11 tRTR 9, 10, 11 tEFL 9, 10, 11 tHFH 9, 10, 11 tFFH 9, 10, 11 tREF 9, 10, 11 Document #: 38-06015 Rev. *D Page 16 of 19 [+] Feedback CY7C4261, CY7C4261 Package Diagrams Figure 17. 32-Pin Thin Plastic Quad Flatpack (7 × 7 × 1.0 mm) 51-85063 *B Figure 18. 32-Pin Plastic Leaded Chip Carrier 51-85002 *B Document #: 38-06015 Rev. *D Page 17 of 19 [+] Feedback CY7C4261, CY7C4261 Package Diagrams (continued) Figure 19. 32-Pin Rectangular Leadless Chip Carrier MIL-STD-1835 C-12 51-80068-** Document #: 38-06015 Rev. *D Page 18 of 19 [+] Feedback CY7C4261, CY7C4261 Document History Page Document Title: CY7C4261/CY7C4271, 16K/32K x 9 Deep Sync FIFOs Document Number: 38-06015 REV. ECN Orig. of Change Submission Date ** 106476 SZV 09/10/01 Changed from Spec number: 38-00658 to 38-06015 *A 122267 RBI 12/26/02 Added power up requirements Maximum Ratings Information *B 127853 FSG 08/22/03 Switching Waveforms section: fixed misplaced footnote in tA in “First Data Word Latency after Reset with Read and Write” drawing Switching Waveforms section: changed tSKEW2 to tSKEW1 (typo) in “Empty Flag Timing” drawing *C 393437 ESH See ECN Added Pb-Free Logo to top of front page Added CY7C4261-10JXI, CY7C4261-15JXC to ordering information *D 2556036 VKN/AESA 08/22/2008 Description of Change Updated ordering information and data sheet template. Removed Pb-Free Logo. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06015 Rev. *D Revised August 22, 2008 Page 19 of 19 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback