CY7C4265V-25ASC

285V CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • 8K x 18 (CY7C4255V) • 16K x 18 (CY7C4265V) • 32K x 18 (CY7C4275V) • 64K x 18 (CY7C4285V) • 0.35 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — ICC = 30 mA — ISB = 4 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • Retransmit function • Output Enable (OE) pin • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • 64-pin 10x10 STQFP • Pin-compatible density upgrade to CY7C42X5V-ASC families • Pin-compatible 3.3V solutions for CY7C4255/65/75/85 Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5V Synchronous FIFO family. The CY7C4255/65/75/85V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4255/65/75/85V have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 67 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. Logic Block Diagram D0 – 17 INPUT REGISTER WCLK WEN WRITE CONTROL High Density Dual-Port RAM Array 8Kx9 16Kx9 32Kx9 64Kx9 FLAG PROGRAM REGISTER FLAG LOGIC FF EF PAE PAF SMODE WRITE POINTER READ POINTER RS RESET LOGIC FL/RT WXI WXO/HF RXI RXO EXPANSION LOGIC THREE-ST ATE OUTPUT REGISTER OE READ CONTROL 4275V–1 Q0 – 17 RCLK REN Cypress Semiconductor Corporation Document #: 38-06012 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 26, 2002 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Pin Configuration REN LD OE RS VCC GND EF Q17 Q16 GND Q15 VCC/SMODE STQFP Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 D16 D17 GND RCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CY7C4255V CY7C4265V CY7C4275V CY7C4285V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC 4275V–3 FL/RT WCLK WEN WXI VCC PAF RXI FF XO/HF RXO PAE Q0 Q1 GND Q2 Q3 Functional Description (continued) The CY7C4255/65/75/85V provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it will be activated. The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. The Almost Empty/Almost Full flags become synchronous if the VCC/SMODE i s tied to VSS. All configurations are fabricated using an advanced 0.35 µ CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Selection Guide 7C4255/65/75/85V-10 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC1) (mA) Commercial Industrial 100 8 10 3.5 0 8 30 7C4255/65/75/85V-15 66.7 10 15 4 0 10 30 35 7C4255/65/75/85V-25 40 15 25 6 1 15 30 CY7C4255V Density Package 8K x 18 64-pin 10x10 TQFP CY7C4265V 16K x 18 64-pin 10x10 TQFP CY7C4275V 32K x 18 64-pin 10x10 TQFP CY7C4285V 64K x 18 64-pin 10x10 TQFP Document #: 38-06012 Rev. *A Page 2 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Pin Definitions Signal Name D0–17 Q0–17 WEN REN WCLK Description Data Inputs Data Outputs Write Enable Read Enable Write Clock I/O I O I I I Data inputs for an 18-bit bus. Data outputs for an 18-bit bus. Enables the WCLK input. Enables the RCLK input. The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD i s asserted, RCLK reads data out of the programmable flagoffset register. Dual-Mode Pin: Single device or width expansion – Half Full status flag. Cascaded – Write Expansion Out signal, connected to WXI o f next device. When EF i s LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE i s asynchronous when VCC/SMODE is tied to VCC; it is synchronized to RCLK when V CC/SMODE is tied to VSS. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF i s asynchronous when VCC/SMODE is tied to VCC; it is synchronized to WCLK when V CC/SMODE is tied to VSS. When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the programmableflag-offset register. Dual-Mode Pin: Cascaded – The first device in the daisy chain will have FL tied to VSS; all other devices will have FL tied to VCC. In standard mode or width expansion, FL i s tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone mode by strobing RT. Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS. Cascaded – Connected to RXO o f previous device. Not Cascaded – Tied to VSS. Cascaded – Connected to RXI of next device. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to VCC. Synchronous Almost Empty/Almost Full flags – tied to VSS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Function RCLK Read Clock I WXO/HF Write Expansion Out/Half Full Flag Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Load First Load/ Retransmit O EF FF PAE O O O PAF O LD FL/RT I I WXI RXI RXO RS OE VCC/SMODE Write Expansion Input Read Expansion Input Read Expansion Output Reset Output Enable Synchronous Almost Empty/ Almost Full Flags I I O I I I Document #: 38-06012 Rev. *A Page 3 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Maximum Ratings[1] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to +150°C Ambient Temperature with Power Applied............................................ –55°C to +125°C Supply Voltage to Ground Potential ......... –0.5V to VCC+0.5V DC Voltage Applied to Outputs in High Z State ......................................... –0.5V to VCC+0.5V DC Input Voltage ..........................................−0.5V to VCC+0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (per MIL–STD–883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Industrial [2] Ambient Temperature 0°C to +70°C –40°C to +85°C VCC[3] 3.3V ±300 mV 3.3V ±300 mV Electrical Characteristics Over the Operating Range[4] 7C4255/65/75/ 85V-10 Parameter VOH Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output OFF, High Z Current Active Power Supply Current Average Standby Current VCC = Max. OE > VIH, VSS < VO < VCC Com’l Ind Com’l Ind 4 Test Conditions VCC = Min., IOH = – 1.0 mA VCC = 3.0V. IOH = – 2.0 mA VCC = M in.,IOL = 4.0 mA VCC = 3.0V.,IOL = 8 .0 mA 2.0 –0.5 –10 –10 Min. 2.4 Max. 7C4255/65/75/ 85V-15 Min. 2.4 Max. 7C4255/65/75/ 85V-25 Min. 2.4 Max. Unit V VOL VIH[5] VIL[5] IIX IOZL IOZH ICC1[6] ISB [7] 0.4 VCC 0.8 +10 +10 30 2.0 –0.5 –10 –10 0.4 VCC 0.8 +10 +10 30 35 4 4 2.0 –0.5 –10 –10 0.4 VCC 0.8 +10 +10 30 V V V µA µA mA mA 4 mA mA Capacitance[8] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 2 5°C, f = 1 MHz, VCC = 3.3V Max. 5 7 Unit pF pF Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA i s the “instant on ” case temperature. 3. VCC range for commercial -10 ns is 3.3V ±150mV. 4. See the last page of this specification for Group A subgroup testing information. 5. The VIH a nd VIL specifications apply for all inputs except WXI, RXI . The WXI, RXI p in is not a TTL input. It is connected to either RXO, WXO o f the previous device or VSS . 6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. 7. All inputs = VCC – 0 .2V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at VSS. All outputs are unloaded. 8. Tested initially and after any design changes that may affect these parameters. Document #: 38-06012 Rev. *A Page 4 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V AC Test Loads and Waveforms (-15 -25)[9, 10] R1=330Ω 3.3V OUTPUT CL INCLUDING JIG AND SCOPE R2=510Ω 3.0V GND ≤ 3 ns 4275V–4 ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns 4287V–5 Equivalent to: THÉVENIN EQUIVALENT 200 Ω OUTPUT 2.0V AC Test Loads and Waveforms (-10) ALL INPUT PULSES 3.0V GND ≤ 3 ns 4275V–6 VCC/2 50 Ω I/O Z0=50Ω 90% 10% 90% 10% ≤ 3 ns 4275V–7 Switching Characteristics Over the Operating Range 7C4255/65/75/85V -10 Parameter tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSR tRSF tPRT tRTR tOLZ tOE Description Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-Up Time Data Hold Time Enable Set-Up Time Enable Hold Time Reset Pulse Width[11] 2 10 4.5 4.5 3.5 0 3.5 0 10 8 10 60 90 Z[12] 0 3 7 60 90 0 3 10 Min. Max. 100 8 2 15 6 6 4 0 4 0 15 10 15 60 90 0 3 12 7C4255/65/75/85V 7C4255/65/75/85V -15 -25 Min. Max. 66.7 10 2 25 10 10 6 1 6 1 25 15 25 Min. Max. 40 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Reset Recovery Time Reset to Flag and Output Time Retransmit Pulse Width Retransmit Recovery Time Output Enable to Output in Low Output Enable to Output Valid Notes: 9. CL = 30 pF for all AC parameters except for tOHZ . 10. CL = 5 p F for tOHZ . 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. Document #: 38-06012 Rev. *A Page 5 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Characteristics Over the Operating Range (continued) 7C4255/65/75/85V -10 Parameter tOHZ tWFF tREF tPAFasynch Description Output Enable to Output in High Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag[13] (Asynchronous mode, VCC/SMODE tied to VCC) Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) Clock to Programmable Almost-Empty Flag[13] (Asynchronous mode, VCC/SMODE tied to VCC) Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) Clock to Half-Full Flag Clock to Expansion Out Expansion in Pulse Width Expansion in Set-Up Time Skew Time between Read Clock and Write Clock for Full Flag Skew Time between Read Clock and Write Clock for Empty Flag Skew Time between Read Clock and Write Clock for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode only) 4.5 4 5 5 10 Z[12] Min. 3 Max. 7 8 8 15 7C4255/65/75/85V 7C4255/65/75/85V -15 -25 Min. 3 Max. 8 10 10 16 Min. 3 Max. 12 15 15 20 Unit ns ns ns ns tPAFsynch 8 10 15 ns tPAEasynch 15 16 20 ns tPAEsynch 8 10 15 ns tHF tXO tXI tXIS tSKEW1 tSKEW2 tSKEW3 12 6 6.5 5 6 6 15 16 10 10 10 10 10 18 20 15 ns ns ns ns ns ns ns Note: 13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E). Document #: 38-06012 Rev. *A Page 6 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms Write Cycle Timing tCLK tCLKH WCLK tDS D0 –D17 tENS WEN tWFF FF tSKEW1 [14] RCLK tWFF tENH NO OPERATION tCLKL tDH REN 4275V–8 Read Cycle Timing tCLK tCLKH RCLK tENS REN tREF EF tA Q0 –Q17 tOLZ tOE OE tSKEW2[15] WCLK VALID DATA tCLKL tENH NO OPERATION tREF tOHZ WEN 4275V–9 Notes: 14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge. Document #: 38-06012 Rev. *A Page 7 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Reset Timing [16] tRS RS tRSR REN, WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF Q0 – Q17 OE=0 4275V–10 OE=1 [17] First Data Word Latency after Reset with Simultaneous Read and Write WCLK tDS D0 –D17 tENS WEN tSKEW2 RCLK tREF EF tFRL [18] D0 (FIRSTVALID WRITE) D1 D2 D3 D4 REN tA Q0 –Q17 tOLZ tOE OE 4275V–11 tA D0 [19] D1 Notes: 16. The clocks (RCLK, WCLK) can be free-running during reset. 17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 18. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 19. The first word is always available the cycle after EF goes HIGH. Document #: 38-06012 Rev. *A Page 8 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Empty Flag Timing WCLK tDS D0 –D17 tENS WEN tFRL[18] RCLK tSKEW2 EF tREF tREF tSKEW2 tREF tFRL[18] D0 tENH tENS tDS D1 tENH REN OE tA Q0 –Q17 D0 4275V–12 Full Flag Timing NO WRITE WCLK tSKEW1 D0 –D17 tWFF FF [14] NO WRITE tDS tSKEW1 [14] DATA WRITE tWFF tWFF DATA WRITE WEN RCLK tENH tENS REN tENS tENH OE LOW tA tA DATA READ NEXT DATA READ 4275V–13 Q0 –Q17 DATA IN OUTPUT REGISTER Document #: 38-06012 Rev. *A Page 9 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Half-Full Flag Timing tCLKH WCLK tENS tENH WEN tHF HF HALF FULL OR LESS HALF FULL + 1 OR MORE tHF RCLK tENS REN 4275V–14 tCLKL HALF FULL OR LESS Programmable Almost Empty Flag Timing tCLKH WCLK tENS tENH WEN tPAE PAE [20] tCLKL N + 1 WORDS IN FIFO tPAE n WORDS IN FIFO RCLK tENS REN 4275V–15 Note: 20. PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06012 Rev. *A Page 10 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKH WCLK tENS tENH WEN Note 21 PAE tSKEW3 [22] RCLK tENS REN tENS tENH tPAE synch N + 1 WORDS IN FIFO Note 23 tPAE synch tCLKL 4275V–16 Programmable Almost Full Flag Timing tCLKH Note 24 WCLK tENS tENH WEN tPAF FULL– M WORDS IN FIFO [26] tPAF RCLK tENS REN 4275V–17 tCLKL PAF [25] FULL– (M+1) WORDS IN FIFO [27] Notes: 21. PAE offset − n. 22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255V, 16384 − (m + 1) for the CY7C4265V, 32768 − (m + 1) for the CY7C4275V, and 65536 − (m + 1) for the CY7C4285V. 25. PAF is offset = m. 26. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V. 27. 8192 − (m + 1) words in CY7C4255V, 16384 − (m + 1) words in CY7C4265V, 32768 − (m + 1) words in CY7C4275V, and 65536 − (m + 1) words in CY7C4285V. Document #: 38-06012 Rev. *A Page 11 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW)) Note 28 tCLKH WCLK tCLKL tENS tENH WEN tPAF PAF FULL – M + 1 WORDS IN FIFO FULL– M WORDS IN FIFO [26] tSKEW3[29] tPAF synch RCLK tENS REN tENS tENH 4275V–18 Write Programmable Registers tCLK tCLKH WCLK tENS LD tENS WEN tDS D0 –D17 PAE OFFSET PAF OFFSET D0 – D11 4275V–19 tCLKL tENH tDH PAE OFFSET Notes: 28. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW. 29. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge. Document #: 38-06012 Rev. *A Page 12 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Read Programmable Registers tCLK tCLKH RCLK tENS LD tENS WEN tA Q0 –Q17 UNKNOWN PAE OFFSET PAF OFFSET PAE OFFSET 4275V–20 tCLKL tENH Write Expansion Out Timing tCLKH WCLK Note 31 tXO WXO tENS WEN 4275V–21 Note 30 tXO Read Expansion Out Timing tCLKH WCLK Note 31 tXO RXO tENS REN 4275V–22 tXO Write Expansion In Timing tXI WXI WCLK tXIS 4275V–23 Notes: 30. Write to Last Physical Location. 31. Read from Last Physical Location. Document #: 38-06012 Rev. *A Page 13 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Switching Waveforms (continued) Read Expansion In Timing tXI RXI tXIS 4275V–24 RCLK Retransmit Timing FL/RT [32, 33, 34] tPRT tRTR REN/WEN EF/FF and all async flags HF/PAE/PAF Notes: 32. Clocks are free-running in this case. 33. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 34. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. 4275V–25 Document #: 38-06012 Rev. *A Page 14 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Architecture The CY7C4255/65/75/85V consists of an array of 8K/16K/32K/64K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4255/65/75/85V also includes the control signals WXI, RXI, WXO, RXO for depth expansion. normal read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK). Table 1. Write Offset Register LD 0 WEN 0 WCLK[35] Selection Writing to offset registers: Empty Offset Full Offset No Operation Write Into FIFO Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only if OE is asserted. In order for the FIFO to reset to its default state, the user must not read or write while RS is LOW. 0 1 1 0 FIFO Operation When the WEN signal is active (LOW), data present on the D0 – 17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the FIFO memory will be presented on the Q0–17 outputs. New data will be presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0–17 outputs when OE is deasserted. When OE is enabled (LOW), data in the output register will be available to the Q0–17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and under flow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0–17 outputs even after additional reads occur. 1 1 No Operation Flag Operation The CY7C4255/65/75/85V devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to VSS. Full Flag The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Programmable Almost Empty/Almost Full Flag The CY7C4255/65/75/85V features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. Programming The CY7C4255/65/75/85V devices contain two 16-bit offset registers. Data present on D0 – 15 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO’s flags, the default offset values are used (see Table 2). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs D0–15 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full offset register on the second LOWto-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset register (see Table 1). Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the LD pin HIGH, the FIFO is returned to Note: 35. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Document #: 38-06012 Rev. *A Page 15 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Table 2. Flag Truth Table Number of Words in FIFO 7C4255V – 8K x 18 0 1 to n[36] (n+1) to 4096 7C4265V – 16K x 18 7C4275V – 32K x 18 0 1 to n[36] (n+1) to 8192 0 1 to n[36] (n+1) to 16384 16385 to (32768–(m+1)) (32768–m)[37] to 32767 32768 7C4285V – 64K x 18 0 1 to n[36] (n+1) to 32768 32769 to (65536 –(m+1)) (65536–m)[37] to 65535 65536 FF H H H H H L PA F H H H H L L PA E L L H H H H HF H H H L L L EF L H H H H H 4097 to (8192–(m+1)) 8193 to (16384 –(m+1)) (8192–m)[37] to 8192 8192 (16384–m)[37] to 16384 16384 Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the stand-alone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Width Expansion Configuration The CY7C4255/65/75/85V can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique will avoid reading data from, or writing data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C4255/65/75/85Vs. RESET (RS) DATA IN (D) 36 18 18 RESET (RS) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) PROGRAMMABLE(PAE) HALF FULL FLAG (HF) FF FULL FLAG (FF) 18 7C4255V 7C4265V 7C4275V 7C4285V 7C4255V 7C4265V 7C4275V 7C4285V READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF) EMPTY FLAG (EF) EF 18 EF FF DATA OUT (Q) 36 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) 4275V–24 Figure 1. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory Used in a Width Expansion Configuration Notes: 36. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127). 37. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127). Document #: 38-06012 Rev. *A Page 16 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Depth Expansion Configuration (with Programmable Flags) The CY7C4255/65/75/85V can easily be adapted to applications requiring more than 8K/16K/32K/64K words of buffering. Figure 2 shows Depth Expansion using three CY7C4255/65/ 75/85Vs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. WXO RXO 7C4255V 7C4265V 7C4275V 7C4285V VCC FL FF EF PAE PAF WXI RXI WXO RXO 7C4255V 7C4265V 7C4275V 7C4285V FL FF EF PAF PAE WXI RXI DATAIN (D) VCC DATA OUT (Q) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) RESET (RS) WXO RXO 7C4255V 7C4265V 7C4275V 7C4285V READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) LOAD (LD) FF PAF FF EF PAE EF PAFWXI RXI PAE FIRST LOAD (FL) 4275V–25 Figure 2. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration Document #: 38-06012 Rev. *A Page 17 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Ordering Information 8Kx18 Low-Voltage Deep Sync FIFO Speed (ns) 10 15 25 Ordering Code CY7C4255V–10ASC CY7C4255V–15ASC CY7C4255V–25ASC Package Name A64 A64 A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Commercial Commercial 16Kx18 Low-Voltage Deep Sync FIFO Speed (ns) 10 15 25 Ordering Code CY7C4265V–10ASC CY7C4265V–15ASC CY7C4265V–25ASC Package Name A64 A64 A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Commercial Commercial 32Kx18 Low-Voltage Deep Sync FIFO Speed (ns) 10 15 Ordering Code CY7C4275V–10ASC CY7C4275V–15ASC Package Name A64 A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Commercial 64Kx18 Low-Voltage Deep Sync FIFO Speed (ns) 10 15 25 Ordering Code CY7C4285V–10ASC CY7C4285V–15ASI CY7C4285V–25ASC Package Name A64 A64 A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Industrial Commercial Document #: 38-06012 Rev. *A Page 18 of 20 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Package Diagrams 64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64 51-85051-A Document #: 38-06012 Rev. *A Page 19 of 20 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V Document Title: CY7C4255V, CY7C4265V, CY7C4275V, CY7C4285V 32K/64K x 18 Low Voltage Deep Sync FIFOs Document Number: 38-06012 REV. ** *A ECN NO. 106473 122264 Issue Date 09/10/01 12/26/02 Orig. of Change SZV RBI Description of Change Change from Spec number: 38-00654 to 38-06012 Power up requirements added to Maximum Ratings Information Document #: 38-06012 Rev. *A Page 20 of 20