CY7C4281V-10JXC

 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 16 K / 32 K / 64 K / 128 K × 9 Low-Voltage Deep Sync™ FIFOs Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.3 V operation for low-power consumption and easy integration into low-voltage systems High-speed, low-power, first-in first-out (FIFO) memories 16 K × 9 (CY7C4261V) 32 K × 9 (CY7C4271V) 64 K × 9 (CY7C4281V) 128 K × 9 (CY7C4291V) 0.35-micron CMOS for optimum speed or power High-speed 100-MHz operation (10-ns read/write cycle times) Low power ❐ ICC = 25 mA ❐ ISB = 4 mA Fully asynchronous and simultaneous read and write operation Empty, Full, and programmable Almost Empty and Almost Full status flags Output-enable (OE) pin Independent read- and write-enable pins Supports free-running 50% duty cycle clock inputs Width-expansion capability Pin-compatible 3.3 V solutions for CY7C4261/71/81/91 Pin-compatible density upgrade to CY7C42X1V family Pb-free packages available provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1 and WEN2/LD are held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and two read-enable pins (REN1, REN2). In addition, the CY7C4261/71/81/91V has an output-enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. The CY7C4261/71/81/91V provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty +7 and Full –7. The flags are synchronous, that is, they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. All configurations are fabricated using an advanced 0.35  CMOS technology. Input ESD protection is greater than 2001 V, and latch-up is prevented by the use of guard rings. 7C4261/71/81/91V-15 66.7 10 15 4 0 10 25 30 CY7C4281V 64 K x 9 32-pin PLCC 7C4261/71/81/91V-25 40 15 25 6 1 15 25 – CY7C4291V 128 K x 9 32-pin PLCC Unit MHz ns ns ns ns ns mA Functional Description The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs Selection Guide 7C4261/71/81/91V-10 Maximum frequency Maximum access time Minimum cycle time Minimum data or enable setup Minimum data or enable hold Maximum flag delay Active power supply current (ICC1) Commercial Industrial CY7C4261V Density Package 16 K x 9 32-pin PLCC 100 8 10 3.5 0 8 25 – CY7C4271V 32 K x 9 32-pin PLCC Cypress Semiconductor Corporation Document #: 38-06013 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 30, 2011 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Logic Block Diagram D0–8 Input Register WCLK WEN1 WEN2/LD Flag Program Register Write Control Flag Logic Read Pointer EF PAE PAF FF Write Pointer Reset Logic Dual Port RAM Array 16 K/32 K 64 K/128 K x9 RS Tristate Output Register OE Q0–8 Read Control RCLK REN1 REN2 Document #: 38-06013 Rev. *F Page 2 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Contents Pin Configuration ............................................................. 4 Pin Definitions .................................................................. 4 Architecture ...................................................................... 5 Resetting the FIFO ............................................................ 5 FIFO Operation ................................................................. 5 Programming .................................................................... 5 Width-Expansion Configuration ...................................... 7 Flag Operation .................................................................. 7 Maximum Ratings ............................................................. 8 Switching Characteristics .............................................. 10 Switching Waveforms .................................................... 11 Write Cycle Timing .................................................... 11 Read Cycle Timing .................................................... 11 Reset Timing .............................................................. 12 First Data Word Latency after Reset with Read and Write 13 Full Flag Timing ......................................................... 15 Programmable Almost Empty Flag Timing ................ 15 Programmable Almost Full Flag Timing .................... 16 Write Programmable Registers ................................. 16 Read Programmable Registers ................................. 17 Ordering Code Definition ........................................... 18 Ordering Information ...................................................... 18 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC Solutions ......................................................... 22 Document #: 38-06013 Rev. *F Page 3 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Pin Configuration PLCC Top View D2 D1 D0 PAF PAE GND REN1 RCLK REN2 OE D3 D4 D5 D6 D7 D8 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 25 24 23 22 21 14 15 16 17 18 19 20 EF FF Q0 Q1 Q2 Q3 Q4 CY7C4261V CY7C4271V CY7C4281V CY7C4291V 27 26 RS WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 Pin Definitions Pin No. Signal Name Description Data inputs Data outputs Write Enable 1 I/O I O I Data inputs for 9-bit bus. Data outputs for 9-bit bus. The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Enables the device for Read operation. Both REN1 and REN2 must be asserted to allow a read operation. The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH and the FIFO is not full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO are not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register. When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAE is synchronized to RCLK. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is synchronized to WCLK. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Description 1–6, 30–32 D08 1–6, 30–32 Q08 28 WEN1 26 WEN2/LD Write Enable 2 Dual mode pin Load I 10, 12 27 REN1, REN2 WCLK Read Enable  inputs Write Clock I I 11 RCLK Read Clock I 14 15 8 7 29 13 EF FF PAE PAF RS OE Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Reset Output Enable O O O O I I Document #: 38-06013 Rev. *F Page 4 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Architecture The CY7C4261/71/81/91V consists of an array of 16 K, 32 K, 64 K, or 128 K words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF). Programming When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 9-bit offset registers contained in the CY7C4261/71/81/91V for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WEN1 are LOW writes data to the empty LSB register again. Figure 1 shows the registers sizes and default values for the various device types. Figure 1. Offset Register Location and Default Values 16 k x 9 8 7 Empty Offset (LSB) Reg. Default Value = 007h Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0–8) go LOW tRSF after the rising edge of RS. In order for the FIFO to reset to its default state, the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW. FIFO Operation When the WEN1 signal is active LOW, WEN2 is active HIGH, and FF is active HIGH, data present on the D0 –8 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN1 and REN2 signals are active LOW and EF is active HIGH, data in the FIFO memory will be presented on the Q0-8 outputs. New data will be presented on each rising edge of RCLK while REN1 and REN2 are active. REN1 and REN2 must set up tENS before RCLK for it to be a valid read function. WEN1 and WEN2 must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0–8 outputs when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Q0-8 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0-8 outputs even after additional reads occur. Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable control pin. In this configuration, when Write Enable 1 (WEN1) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored is the RAM array sequentially and independently of any on-going read operation. Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows for depth expansion. If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS = LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. 32 k x 9 0 8 7 Empty Offset (LSB) Reg. Default Value = 007h 0 8 5 0 (MSB) Default Value = 000h 8 6 (MSB) Default Value = 000h 0 87 Full Offset (LSB) Reg Default Value = 007h 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 8 5 0 (MSB) Default Value = 000h 8 6 (MSB) Default Value = 000h 0 64k x 9 8 7 Empty Offset (LSB) Reg. Default Value = 007h 128k x 9 0 8 7 Empty Offset (LSB) Reg. Default Value = 007h 0 87 (MSB) Default Value = 000h 0 8 (MSB) Default Value = 000h 0 87 Full Offset (LSB) Reg Default Value = 007h 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 87 (MSB) Default Value = 000h 0 8 (MSB) Default Value = 000h 0 Document #: 38-06013 Rev. *F Page 5 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers. Table 1. Writing the Offset Registers[1] LD 0 WEN 0 WCLK Selection Empty offset (LSB) Empty offset (MSB) Full offset (LSB) Full offset (MSB) No operation Write into FIFO No operation 0 1 1 1 0 1 Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. The number formed by the empty offset least significant bit register and empty offset most significant bit register is referred to as n and determines the operation of PAE. PAE is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n+1) or greater unread words. The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of PAF. PAF is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4261V (16k – m), CY7C4271V (32k – m), CY7C4281V (64k – m) and CY7C4291V (128k – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. Table 2. Status Flags Number of Words in FIFO CY7C4261V 0 1 to n[2] (16384  m)[3] to 16383 16384 0 1 to n[2] (32768  m)[3] to 32767 32768 CY7C4271V 0 1 to n[2] (65536  m)[3] to 65535 65536 CY7C4281V 0 1 to n[2] (131072  m)[3] to 131071 131072 CY7C4291V FF PAF PAE EF H H H H L H H H L L L L H H H L H H H H (n + 1) to (1638  (m + 1)) (n + 1) to (32768  (m + 1)) (n + 1) to (65536  (m + 1)) (n + 1) to (131072  (m + 1)) Notes 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK. 2. n = Empty Offset (n = 7 default value). 3. m = Full Offset (m = 7 default value). Document #: 38-06013 Rev. *F Page 6 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Width-Expansion Configuration Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C42x1Vs. Any word width can be attained by adding additional CY7C42x1Vs. When the CY7C42x1V is in a Width-Expansion Configuration, the Read Enable (REN2) control input can be grounded (see Figure 2). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. Flag Operation The CY7C4261/71/81/91V devices provide five flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The Full Flag (FF) will go LOW when the device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Figure 2. Block Diagram of 16 K / 32 K / 64 K / 128 K × 9 Low-Voltage Deep Sync FIFO Memory Used in a Width-Expansion Configuration Reset (RS) Data In (D) 18 9 9 Reset (RS) Read Clock (RCLK) Write Clock (WLCK) Write Enable (WEN1) Write Enable 2/Load (WEN2/LD) Programmable (PAF) Full Full Flag (FF) # 1 Flag (FF) # 2 Read Enable 1 (REN1) Output Enable (OE) Programmable (PAE) Empty Flag (EF) #1 Empty Flag (EF) #2 9 9 CY7C4261V CY7C4271V CY7C4281V CY7C4291V FF EF CY7C4261V CY7C4271V CY7C4281V CY7C4291V FF EF Data Out (Q) 18 Read Enable 2 (REN2) Read Enable 2 (REN2) Document #: 38-06013 Rev. *F Page 7 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Maximum Ratings (Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.) Storage temperature .................................. –65 °C to +150 °C Ambient temperature with power applied ... –55 °C to +125 °C Supply voltage to ground potential ...............–0.5 V to +3.6 V DC voltage applied to outputs in High-Z state ..................................... –0.5 V to VCC + 0.5 V DC input voltage .................................. –0.5 V to VCC + 0.5 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up current ..................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0 °C to +70 °C 40 °C to +85 °C VCC[4] 3.3 V 300 mV 3.3 V 300 mV Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZL IOZH ICC1[5] ISB[6] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output OFF, High Z current Active power supply current Test Conditions VCC = Min., IOH = 1.0 mA VCC = 3.0 V, IOH = 2.0 mA VCC = Min., IOL = 4.0 mA VCC = 3.0 V, IOL = 8.0 mA – – VCC = Max. OE VIH,  VSS < VO< VCC – Com’l Ind Com’l Ind 7C4261/71/81/91V- 7C4261/71/81/91V- 7C4261/71/81/91V10 15 25 Unit Min Max Min Max Min Max 2.4 – 2.0 0.5 10 10 – – – – – .04 VCC 0.8 +10 +10 25 – 4 – 2.4 – 2.0 0.5 10 10 – – – – – 0.4 VCC 0.8 +10 +10 25 30 4 4 2.4 – 2.0 0.5 10 10 – – – – – 0.4 VCC 0.8 +10 +10 25 – 4 – V V V V A A mA mA mA mA Average – standby current Capacitance Parameter[7] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 5 7 Unit pF pF Notes 4. VCC Range for commercial –10 ns is 3.3 V ±150 mV. 5. Input signals switch from 0 V to 3 V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency of 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. 6. All inputs = VCC – 0.2 V, except WCLK and RCLK (which are at frequency = 0 MHz). All outputs are unloaded. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06013 Rev. *F Page 8 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V AC Test Loads and Waveforms (-15 and -25)[8, 9] R1 = 330  3.3 V Output CL Including JIG and Scope Thé venin Equivalent 200  Output R2=510  3.0 V GND  3 ns All Input Pulses 90% 10% 90% 10%  3 ns Equivalent to: 2.0 V AC Test Loads and Waveforms (-10) VCC/2 50  3.0V All Input Pulses 90% 10%  3 ns 90% 10%  3 ns I/O Z0 = 50 GND Notes 8. CL = 30 pF for all AC parameters except for tOHZ. 9. CL = 5 pF for tOHZ. Document #: 38-06013 Rev. *F Page 9 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Characteristics Over the Operating Range Parameter tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tSKEW1 tSKEW2 Description Clock cycle frequency Data access time Clock cycle time Clock HIGH time Clock LOW time Data set-up time Data hold time Enable set-up time Enable hold time Reset pulse width[10] Reset set-up time Reset recovery time Reset to flag and output time Output enable to output in Low Output enable to output valid Output enable to output in High Write clock to Full flag Read clock to Empty flag Clock to programmable Almost-Full flag Clock to programmable Almost-Full flag Skew time between read clock and write clock for Empty flag and Full flag Skew time between read clock and write clock for Almost-Empty flag and Almost-Full flag Z[11] Z[10] 7C4261/71/81/91V- 7C4261/71/81/91V- 7C4261/71/81/91V10 15 25 Min – 2 10 4.5 4.5 3.5 0 3.5 0 10 8 8 – 0 3 3 – – – – 5 10 Max 100 8 – – – – – – – – – – 10 – 7 7 8 8 8 8 – – Min – 2 15 6 6 4 0 4 0 15 10 10 – 0 3 3 – – – – 6 15 Max 66.7 10 – – – – – – – – – – 15 – 10 8 10 10 10 10 – – Min – 2 25 10 10 6 1 6 1 25 15 15 – 0 3 3 – – – – 10 18 Max 40 15 – – – – – – – – – – 25 – 12 12 15 15 15 15 – – MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Notes 10. Pulse widths less than minimum values are not allowed. 11. Values guaranteed by design, not currently tested. Document #: 38-06013 Rev. *F Page 10 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Waveforms Write Cycle Timing tCLK tCLKH WCLK tCLKL tDS D0 –D17 tENS WEN1 tDH tENH No Operation WEN2 (if applicable) FF No Operation tWFF tWFF tSKEW1 [12] RCLK REN1, REN2 Read Cycle Timing tCLKH RCLK tENS REN1, REN2 tREF EF tA Q0 –Q17 tOLZ OE tSKEW1[13] WCLK tOE Valid Data tCKL tCLKL tENH NO OPERATION tREF tOHZ WEN1 WEN2 Notes 12. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 13. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge. Document #: 38-06013 Rev. *F Page 11 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Waveforms Reset Timing[14] RS tRS tRSS REN1, REN2 tRSS WEN1 tRSS WEN2/LD [16] (continued) tRSR tRSR tRSR tRSF EF,PAE tRSF FF, PAF tRSF Q0  Q8 OE = 1 OE=0 [15] Notes 14. The clocks (RCLK, WCLK) can be free-running during reset. 15. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 16. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06013 Rev. *F Page 12 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Waveforms (continued) First Data Word Latency after Reset with Read and Write WCLK tDS D0 –D8 tENS WEN1 WEN2 (if applicable) tSKEW1 RCLK tREF EF tA REN1, REN2 Q0 –Q8 tOLZ OE tOE D0 tA [18] tFRL [17] D0 (First Valid Write) D1 D2 D3 D4 D1 Notes 17. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK 18. The first word is available the cycle after EF goes HIGH, always. + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). Document #: 38-06013 Rev. *F Page 13 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Waveforms Empty Flag Timing WCLK tDS D0 –D8 tENS WEN1 tENS WEN2 (if applicable) tFRL [19] RCLK tSKEW1 EF REN1, REN2 LOW OE tA Q0 –Q8 Data In Output Register Data Read tREF tREF tSKEW1 tREF tFRL [19] tENH Data Write 1 tENH tENS tENS tENH tDS Data Write 2 tENH (continued) Note 19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). Document #: 38-06013 Rev. *F Page 14 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Waveforms Full Flag Timing No Write WCLK tSKEW1[20] D0 –D8 tWFF FF tDS Data Write tWFF tWFF tSKEW1[20] Data Write No Write (continued) WEN1 WEN2 (if applicable) RCLK tENS tENH tENS tENH REN1, REN2 OE LOW tA tA Data Read Next Data Read Q0 –Q8 Data In Output Register Programmable Almost Empty Flag Timing tCLKH WCLK tENS tENH WEN1 WEN2 (if applicable) tENS tENH PAE tSKEW2 [21] RCLK tENS REN1, REN2 Notes 20. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK. 22. PAE offset = n. 23. If a read is performed on this rising edge of the read clock, there will be Empty + (n1) words in the FIFO when PAE goes LOW. 22 tCLKL N + 1 WORDS IN FIFO tPAE 23 tPAE tENS tENH Document #: 38-06013 Rev. *F Page 15 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Waveforms (continued) Programmable Almost Full Flag Timing tCLKH WCLK tENS tENH WEN1 WEN2 (if applicable) tENS tENH PAF Full (M+1) Words In FIFO Note 25 tPAF (Full - M) Words In FIFO [26] tSKEW2 [27] tPAF tCLKL Note 24 RCLK tENS REN1, REN2 tENS tENH Write Programmable Registers tCLK tCLKH WCLK tENS WEN2/LD tENS WEN1 tDS D0 –D8 PAE Offset LSB PAE Offset MSB PAF Offset LSB PAF Offset MSB tDH tENH tCLKL Notes 24. If a write is performed on this rising edge of the write clock, there will be Full  (m1) words of the FIFO when PAF goes LOW. 25. PAF offset = m. 26. 16 K m words for CY7C4261V, 32 K – m words for CY7C4271V, 64 K  m words for CY7C4281V, and 128 K  m words for CY4291V. 27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK. Document #: 38-06013 Rev. *F Page 16 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Switching Waveforms (continued) Read Programmable Registers tCLK tCLKH RCLK tENS WEN2/LD tENS REN1, REN2 tA Q0 –Q15 Unknown PAE Offset LSB PAE Offset MSB PAF Offset LSB PAF Offset MSB tENH tCLKL Document #: 38-06013 Rev. *F Page 17 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Ordering Information 16 K × 9 Low-Voltage Deep Sync FIFO Speed (ns) 10 15 10 10 10 15 CY 7 C Ordering Code CY7C4261V-10JXC CY7C4261V-15JXC CY7C4271V-10JXC CY7C4281V-10JXC CY7C4291V-10JXC CY7C4291V-15JXC 42xx V xx Package Name J65 J65 J65 J65 J65 J65 JXC Package Type:  J = Package name, X = Pb-free, C = Commercial Speed: 10/15 ns Separator Voltage: 3.3 V Part Identifier Technology: CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Package Type 32-pin Pb-free plastic leaded chip carrier 32-pin Pb-free plastic leaded chip carrier 32-pin Pb-free plastic leaded chip carrier 32-pin Pb-free plastic leaded chip carrier 32-pin Pb-free plastic leaded chip carrier 32-pin Pb-free plastic leaded chip carrier Operating Range Commercial Commercial Commercial Commercial Commercial Commercial 32 K × 9 Low-Voltage Deep Sync FIFO 64 K × 9 Low-Voltage Deep Sync FIFO 128 K × 9 Low-Voltage Deep Sync FIFO Ordering Code Definition Document #: 38-06013 Rev. *F Page 18 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Package Diagram Figure 3. 32-Pin Pb-free Plastic Leaded Chip Carrier J65, 51-85002 51-85002 *C Document #: 38-06013 Rev. *F Page 19 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Acronyms Table 3. Acronyms Used Acronym CMOS CE I/O OE SRAM TSOP WE chip enable input/output output enable static random access memory thin small outline package write enable Description complementary metal oxide semiconductor V µA mA pF °C W Document Conventions Units of Measure Table 4. Units of Measure Symbol ns nano seconds volts micro amperes milli amperes pico Farad degree Celsius watts Unit of Measure Document #: 38-06013 Rev. *F Page 20 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Document History Page Document Title: CY7C4261V/CY7C4271V/CY7C4281V/CY7C4291V 16 K / 32 K / 64 K / 128 K × 9 Low-Voltage Deep Sync™ FIFOs Document Number: 38-06013 REV. ** *A *B ECN NO. 106474 127858 386127 Issue Date 09/15/01 09/04/03 See ECN Orig. of Change SZV FSG ESH Description of Change Changed Spec number from 38-00656 to 38-06013 Changed: tSKEW2 to tSKEW1 in Switching Waveforms “Empty Flag Timing” diagram Fixed flag timing diagram in Switching Waveforms section Added Pb-Free logo to top of front page Added CY7C4291V-15JXC, CY7C91V-10JXC, CY7C4281V-10JXC, CY7C4271V-10JXC, CY7C4261V-10JXC, CY7C4261V-15JXC to ordering information. Removed inactive parts from Ordering information and updated package diagram. Removed inactive part from Ordering Information table. Corrected data in Programmable Flag (PAE, PAF) Operation: a) PAF is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. Changed PAF to PAE. b) PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4261 (16K-m) and CY7C4271 (32K-m). Changed PAE to PAF. Added Acronyms, Document Conventions, and Ordering Code Definition. Removed CY7C4271V-10JC part from Ordering Information table. *C *D *E 2896378 2906525 3069396 03/19/2010 04/07/2010 10/22/2010 RAME RAME ADMU *F 3210221 03/25/2011 ADMU Document #: 38-06013 Rev. *F Page 21 of 22 [+] Feedback CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06013 Rev. *F Revised March 30, 2011 Page 22 of 22 Deep Sync is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback