CY7C4285-10ASC

285 CY7C4275 CY7C4285 32K/64Kx18 Deep Sync FIFOs Features Functional Description • High-speed, low-power, first-in first-out (FIFO) memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — ICC=50 mA • • • • • • • • • • • • • — ISB = 2 mA Fully asynchronous and simultaneous read and write operation Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags TTL compatible Retransmit function Output Enable (OE) pin Independent read and write enable pins Center power and ground pins for reduced noise Supports free-running 50% duty cycle clock inputs Width Expansion Capability Depth Expansion Capability 68-pin PLCC and 64-pin 10x10 TQFP Pin-compatible density upgrade to CY7C42X5 families Pin-compatible density upgrade to IDT72205/15/25/35/45 The CY7C4275/85 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4275/85 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. D0 –17 Logic Block Diagram INPUT REGISTER WCLK WEN FLAG PROGRAM REGISTER WRITE CONTROL FF EF PAE PAF SMODE FLAG LOGIC RAM ARRAY 32Kx18 64Kx18 WRITE POINTER RS FL/RT WXI WXO/HF RXI RXO READ POINTER RESET LOGIC THREE–STATE OUTPUT REGISTER EXPANSION LOGIC Cypress Semiconductor Corporation Document #: 38-06008 Rev. *A Q0 – 17 • READ CONTROL OE 3901 North First Street RCLK • REN San Jose 4275–1 • CA 95134 • 408-943-2600 Revised December 26, 2002 CY7C4275 CY7C4285 Pin Configurations D3 D2 D1 D0 REN LD OE RS VCC GND EF Q17 Q16 GND Q15 VCC/SMODE D16 D17 GND RCLK GND Q15 Q16 VCC Q17 EF GND 3 2 1 68 67 66 65 64 63 62 61 CY7C4275 CY7C4285 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 VCC/SMODE Q14 Q13 47 46 45 44 Q6 Q5 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC GND Q4 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 4 VCC RCLK REN LD OE RS 6 5 10 11 12 13 14 15 16 17 18 19 20 TQFP Top View CY7C4275 CY7C4285 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 8 7 D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 GND D17 D16 D15 PLCC Top View Q14 Q13 GND Q12 Q11 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC Q3 PAE Functional Description (continued) Q0 Q1 GND Q2 4275–3 4275–2 FL/RT WCLK WEN WXI VCC PAF RXI FF WXO/HF RXO VCC Q2 Q3 GND Q0 Q1 WXO/HF RXO RXI FF PAF VCC WEN WXI WCLK PAE FL/RT 2728 2930 3132 33 34 35 36 37 38 3940 4142 43 The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. The Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.5µ CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. The CY7C4275/85 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it will be activated. Selection Guide 7C4275/85-10 7C4275/85-15 7C4275/85-25 100 66.7 40 Maximum Access Time (ns) 8 10 15 Minimum Cycle Time (ns) 10 15 25 Maximum Frequency (MHz) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC1) (mA) Density Packages 3 4 6 0.5 1 1 8 10 15 Commercial 50 50 50 Industrial 55 CY7C4275 CY7C4285 32K x 18 64K x 18 64-pin 10x10 TQFP, 64-pin 10x10 TQFP, 68-pin PLCC 68-pin PLCC Document #: 38-06008 Rev. *A Page 2 of 21 CY7C4275 CY7C4285 Pin Definitions Signal Name Description I/O Function D0–17 Data Inputs I Data inputs for an 18-bit bus Q0–17 Data Outputs O Data outputs for an 18-bit bus WEN Write Enable I Enables the WCLK input REN Read Enable I Enables the RCLK input WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register. WXO/HF Write Expansion Out/Half Full Flag O Dual-Mode Pin: Single device or width expansion – Half Full status flag. Cascaded – Write Expansion Out signal, connected to WXI of next device. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable Almost Empty O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC; it is synchronized to RCLK when V CC/SMODE is tied to VSS. PAF Programmable Almost Full O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC; it is synchronized to WCLK when V CC/SMODE is tied to VSS. LD Load I When LD is LOW, D 0–17 (Q0–17) are written (read) into (from) the programmable-flag-offset register. FL/RT First Load/ Retransmit I Dual-Mode Pin: Cascaded – The first device in the daisy chain will have FL tied to VSS; all other devices will have FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone mode by strobing RT. WXI Write Expansion Input I Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS. RXI Read Expansion Input I Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to VSS. RXO Read Expansion Output O Cascaded – Connected to RXI of next device. RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. VCC/SMODE Synchronous Almost Empty/ Almost Full Flags I Dual-Mode Pin Asynchronous Almost Empty/Almost Full flags – tied to VCC. Synchronous Almost Empty/Almost Full flags – tied to VSS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Document #: 38-06008 Rev. *A Page 3 of 21 CY7C4275 CY7C4285 Maximum Ratings[1] Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............................................ >2001V (per MIL–STD–883, Method 3015) Storage Temperature ................................–65°C to +150 °C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................–55°C to +125 °C Operating Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Commercial 0° C to +70 °C 5V ± 10% DC Input Voltage ..........................................−0.5V to VCC+0.5V Industrial –40°C to +85°C 5V ± 10% [2] Electrical Characteristics Over the Operating Range[3] 7C42X5-10 Parameter Description Test Conditions Min. Max. Min. 7C42X5-25 Max. VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH[4] Input HIGH Voltage 2.0 VCC 2.0 VCC VIL[5] Input LOW Voltage –0.5 0.8 –0.5 0.8 IIX Input Leakage Current VCC = Max. –10 +10 –10 +10 IOZL IOZH Output OFF, High Z Current OE > VIH, VSS < VO < VCC –10 +10 –10 +10 ICC1[6] Active Power Supply Current Com’l 50 Ind 55 Average Standby Current Com’l 2 Ind 2 ISB [7] 2.4 7C42X5-5 2.4 0.4 Min. Max. 2.4 0.4 50 Unit V 0.4 V 2.0 VCC V –0.5 0.8 V –10 +10 µA –10 +10 µA 50 mA mA 2 2 mA mA Capacitance[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25° C, f = 1 MHz, VCC = 5.0V Max. Unit 5 pF 7 pF Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or VSS . 5. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or VSS. 6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. Icc1(typical) = (25 mA+(freq –20MHz)*(1.0 mA/MHz)). 7. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at VSS. All outputs are unloaded. 8. Tested initially and after any design changes that may affect these parameters. Document #: 38-06008 Rev. *A Page 4 of 21 CY7C4275 CY7C4285 AC Test Loads and Waveforms[9, 10] ALL INPUT PULSES R1 1.1KΩ 5V 3.0V OUTPUT CL GND ≤ 3 ns R2 680Ω INCLUDING JIG AND SCOPE 90% 10% 90% 10% ≤ 3 ns 4275–4 4275–5 Equivalent to: THÉVENIN EQUIVALENT 410Ω OUTPUT 1.91V Switching Characteristics Over the Operating Range Parameter Description 7C42X5-10 7C42X5-15 7C42X5-25 Min. Min. Min. Max. 100 Max. Unit 40 MHz 15 ns tS Clock Cycle Frequency tA Data Access Time 2 tCLK Clock Cycle Time 10 15 25 ns tCLKH Clock HIGH Time 4.5 6 10 ns tCLKL Clock LOW Time 4.5 6 10 ns tDS Data Set-Up Time 3 4 6 ns tDH Data Hold Time 0.5 1 1 ns tENS Enable Set-Up Time 3 4 6 ns tENH Enable Hold Time 8 66.7 Max. 2 10 2 0.5 1 1 ns tRS Reset Pulse Width[11] 10 15 25 ns tRSR Reset Recovery Time 8 tRSF Reset to Flag and Output Time tPRT Retransmit Pulse Width tRTR Retransmit Recovery Time tOLZ Output Enable to Output in Low tOE Output Enable to Output Valid tOHZ Output Enable to Output in High tWFF Write Clock to Full Flag tREF Read Clock to Empty Flag 10 10 Z[12] Z[12] Flag[13] 15 15 ns 25 ns 60 60 60 ns 90 90 90 ns 0 0 0 ns 3 7 3 8 3 12 ns 3 7 3 8 3 12 ns 8 10 15 ns 8 10 15 ns tPAFasynch Clock to Programmable Almost-Full (Asynchronous mode, VCC/SMODE tied to VCC) 15 16 20 ns tPAFsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 8 10 15 ns tPAEasynch Clock to Programmable Almost-Empty Flag[13] (Asynchronous mode, VCC/SMODE tied to VCC) 15 16 20 ns Notes: 9. CL = 30 pF for all AC parameters except for tOHZ . 10. CL = 5 pF for tOHZ . 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. 13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E). Document #: 38-06008 Rev. *A Page 5 of 21 CY7C4275 CY7C4285 Switching Characteristics Over the Operating Range (continued) Parameter Description 7C42X5-10 7C42X5-15 7C42X5-25 Min. Min. Min. Max. Max. Max. Unit tPAEsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 8 10 15 ns tHF Clock to Half-Full Flag 12 16 20 ns tXO Clock to Expansion Out 6 10 15 ns tXI Expansion in Pulse Width 4.5 6.5 10 ns tXIS Expansion in Set-Up Time 4 5 10 ns tSKEW1 Skew Time between Read Clock and Write Clock for Full Flag 5 6 10 ns tSKEW2 Skew Time between Read Clock and Write Clock for Empty Flag 5 6 10 ns tSKEW3 Skew Time between Read Clock and Write Clock for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode only) 10 15 18 ns Document #: 38-06008 Rev. *A Page 6 of 21 CY7C4275 CY7C4285 Switching Waveforms Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0 –D17 tENS tENH WEN NO OPERATION tWFF tWFF FF tSKEW1 [14] RCLK REN 4275–6 Read Cycle Timing tCLK tCLKH tCLKL RCLK tENS tENH REN NO OPERATION tREF tREF EF tA VALID DATA Q0 –Q17 tOLZ tOHZ tOE OE tSKEW2[15] WCLK WEN 4275–7 Notes: 14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge. Document #: 38-06008 Rev. *A Page 7 of 21 CY7C4275 CY7C4285 Switching Waveforms (continued) Reset Timing [16] tRS RS tRSR REN, WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF [17] OE=1 Q0 – Q17 OE=0 4275–8 First Data Word Latency after Reset with Simultaneous Read and Write WCLK tDS D0 –D17 D0 (FIRSTVALID WRITE) D1 D2 D3 D4 tENS [18] tFRL WEN tSKEW2 RCLK tREF EF REN tA Q0 –Q17 tA D0 [19] D1 tOLZ tOE OE 4275–9 Notes: 16. The clocks (RCLK, WCLK) can be free-running during reset. 17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 18. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 19. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06008 Rev. *A Page 8 of 21 CY7C4275 CY7C4285 Switching Waveforms (continued) Empty Flag Timing WCLK tDS tDS D0 D0 –D17 D1 tENH tENS tENH tENS WEN tFRL[18] tFRL[18] RCLK tREF tSKEW2 tREF tREF tSKEW2 EF REN OE tA D0 Q0 –Q17 4275–10 Full FlagTiming NO WRITE NO WRITE WCLK tSKEW1 [14] tDS tSKEW1 [14] DATA WRITE DATA WRITE D0 –D17 tWFF tWFF tWFF FF WEN RCLK tENH tENH tENS tENS REN OE LOW tA Q0 –Q17 DATA IN OUTPUT REGISTER tA DATA READ NEXT DATA READ 4275–11 Document #: 38-06008 Rev. *A Page 9 of 21 CY7C4275 CY7C4285 Switching Waveforms (continued) Half-Full Flag Timing tCLKH tCLKL WCLK tENS tENH WEN tHF HF HALF FULL + 1 OR MORE HALF FULL OR LESS HALF FULLOR LESS tHF RCLK tENS REN 4275–12 Programmable Almost Empty Flag Timing tCLKH tCLKL WCLK tENS tENH WEN tPAE PAE [20] N + 1 WORDS IN FIFO tPAE n WORDS IN FIFO RCLK tENS REN 4275–13 Note: 20. PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06008 Rev. *A Page 10 of 21 CY7C4275 CY7C4285 Switching Waveforms (continued) Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKL tCLKH WCLK tENS tENH WEN Note 21 PAE tSKEW3 [22] N + 1 WORDS IN FIFO Note 23 tPAE synch tPAE synch RCLK tENS tENS tENH REN 4275–14 Programmable Almost Full Flag Timing tCLKL tCLKH Note 24 WCLK tENS tENH WEN tPAF PAF FULL– M WORDS IN FIFO[26] [25] FULL– (M+1) WORDS [27] IN FIFO tPAF RCLK tENS REN 4275–15 Notes: 21. PAE offset − n. 22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 32768 − (m + 1) for the CY7C4285 and 65536 − (m + 1) for the CY7C4285. 25. PAF is offset = m. 26. 32768 − m words in CY7C4275 and 65536 – m words in CY7C4285. 27. 32768 − (m + 1) words in CY7C4275 and 65536 – (m + 1) CY7C4285. Document #: 38-06008 Rev. *A Page 11 of 21 CY7C4275 CY7C4285 Switching Waveforms (continued) Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKL tCLKH Note 28 WCLK tENS tENH WEN Note 29 PAF tPAF FULL– M WORDS IN FIFO [26] FULL– M + 1 WORDS IN FIFO tSKEW3[30] tPAF synch RCLK tENS tENS tENH REN 4275–16 Write Programmable Registers tCLK tCLKL tCLKH WCLK tENS tENH LD tENS WEN tDS tDH PAE OFFSET D0 –D17 PAE OFFSET PAF OFFSET D0 – D11 4275–17 Notes: 28. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW. 29. PAF offset = m. 30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge. Document #: 38-06008 Rev. *A Page 12 of 21 CY7C4275 CY7C4285 Switching Waveforms (continued) Read Programmable Registers tCLK tCLKL tCLKH RCLK tENS tENH LD tENS WEN tA UNKNOWN Q0 –Q17 PAE OFFSET PAF OFFSET PAE OFFSET 4275–18 Write Expansion Out Timing tCLKH Note 32 WCLK tXO Note 31 WXO tXO tENS WEN 4275–19 Read Expansion Out Timing tCLKH WCLK Note 32 tXO RXO tXO tENS REN 4275–20 Write Expansion In Timing tXI WXI WCLK tXIS 4275–21 Notes: 31. Write to last physical location. 32. Read from last physical location. Document #: 38-06008 Rev. *A Page 13 of 21 CY7C4275 CY7C4285 Switching Waveforms (continued) Read Expansion In Timing tXI RXI tXIS RCLK 4275–22 Retransmit Timing [33, 34, 35] FL/RT tPRT tRTR REN/WEN EF/FF and all async flags HF/PAE/PAF 4275–23 Notes: 33. Clocks are free running in this case. 34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. Document #: 38-06008 Rev. *A Page 14 of 21 CY7C4275 CY7C4285 Architecture ation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. The CY7C4275/85 consists of an array of 32K/64K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4275/85 also includes the control signals WXI, RXI, WXO, RXO for depth expansion. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK). Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only if OE is asserted. In order for the FIFO to reset to its default state, the user must not read or write while RS is LOW. FIFO Operation When the WEN signal is active (LOW), data present on the D0–17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the FIFO memory will be presented on the Q0–17 outputs. New data will be presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0–17 outputs when OE is deasserted. When OE is enabled (LOW), data in the output register will be available to the Q0–17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and under flow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0–17 outputs even after additional reads occur. Programming The CY7C4275/85 devices contain two 16-bit offset registers. Data present on D0–15 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO’s flags, the default offset values are used (see Table 2). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs D0–15 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset register (see Table 1). Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the LD pin HIGH, the FIFO is returned to normal read/write oper- Table 1. Write Offset Register WCLK[36] LD WEN 0 0 Writing to offset registers: Empty Offset Full Offset Selection 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation Flag Operation The CY7C4275/85 devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to VSS. Full Flag The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Programmable Almost Empty/Almost Full Flag The CY7C4275/85 features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. Note: 36. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Document #: 38-06008 Rev. *A Page 15 of 21 CY7C4275 CY7C4285 Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the stand-alone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last RS cycle. A HIGH pulse on RT resets the inter- nal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incriminated until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Table 2. Flag Truth Table Number of Words in FIFO 7C4275 – 32K x 18 7C4285 – 64K x 18 FF PAF HF PAE EF 0 0 H H H L L 1 to n[37] 1 to n[37] H H H L H (n+1) to 16384 (n+1) to 32768 H H H H H 16385 to (32768–(m+1)) 32769 to (65536 –(m+1)) H H L H H (32768–m)[38] to 32767 (65536–m)[38] to 65535 H L L H H 32768 65536 L L L H H Notes: 37. n = Empty Offset (Default Values: CY7C4275/CY7C4285 n = 127). 38. m = Full Offset (Default Values: CY7C4275/CY7C4285 n = 127). Document #: 38-06008 Rev. *A Page 16 of 21 CY7C4275 CY7C4285 Width Expansion Configuration the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique will avoid reading data from, or writing data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C4275/85s. The CY7C4275/85 can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing RESET (RS) DATA IN (D) 36 RESET (RS) 18 18 READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE (OE) LOAD (LD) PROGRAMMABLE(PAE) 7C4275 7C4285 7C4275 7C4285 HALF FULL FLAG (HF) PROGRAMMABLE (PAF) EMPTY FLAG (EF) FF FF EF EF 18 FULL FLAG (FF) DATA OUT (Q) 36 18 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) 4275–24 Figure 1. Block Diagram of 32K x18/64K x 18 Deep Sync FIFO Memory Used in a Width Expansion Configuration Document #: 38-06008 Rev. *A Page 17 of 21 CY7C4275 CY7C4285 Depth Expansion Configuration (with Programmable Flags) 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. The CY7C4275/85 can easily be adapted to applications requiring more than 32,768/65,536 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. WXO RXO 7C4275 7C4285 VCC FL FF EF PAE PAF WXI RXI WXO RXO 7C4275 7C4285 DATAIN (D) DATA OUT (Q) VCC FL FF EF PAF PAE WXI RXI WRITECLOCK (WCLK) WXO RXO WRITEENABLE (WEN) READ CLOCK (RCLK) READ ENABLE (REN) 7C4275 7C4285 RESET (RS) OUTPUTENABLE (OE) LOAD (LD) FF FF PAF EF EF PAFWXI RXI PAE PAE FIRST LOAD (FL) 4275–25 Figure 2. Block Diagram of 32Kx18/64Kx18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration Document #: 38-06008 Rev. *A Page 18 of 21 CY7C4275 CY7C4285 Ordering Information 32Kx18 Deep Sync FIFO Speed (ns) 10 Ordering Code Package Name Package Type Operating Range CY7C4275–10ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial CY7C4275–10ASI A64 64-Lead 10x10 Thin Quad Flatpack Industrial 15 CY7C4275–15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 25 CY7C4275–25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 64Kx18 Deep Sync FIFO Speed (ns) 10 Ordering Code Package Name Package Type Operating Range CY7C4285–10ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial CY7C4285–10ASI A64 64-Lead 10x10 Thin Quad Flatpack Industrial 15 CY7C4285–15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 25 CY7C4285–25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial Document #: 38-06008 Rev. *A Page 19 of 21 CY7C4275 CY7C4285 Package Diagrams Document #: 38-06008 Rev. *A Page 20 of 21 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4275 CY7C4285 Document Title: CY7C4275, CY7C4285 32K/64K X 18 Deep Sync FIFOs Document Number: 38-06008 REV. ECN NO. Issue Date Orig. of Change ** 106469 07/12/01 SZV Change from Spec Number: 38-00588 to 38-06008 *A 122260 12/26/02 RBI Power up requirements added to Maximum Ratings Information Document #: 38-06008 Rev. *A Description of Change Page 21 of 21