CY7C429-15PC

Datasheet CY7C420, CY7C421 CY7C424, CY7C425 CY7C428, CY7C429 Cascadable 2K x 9 FIFO The CY7C420/CY7C421, CY7C424/CY7C425, and CY7C428/CY7C429 are first-in first-out (FIFO) memories offered in 600-mil wide and 300-mil wide packages. They are, respectively, 512, 1,024, and 2,048 words by 9-bitswide. EachFIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel, thus eliminating the serial addition of propagation delays, so that throughput is not reduced Data is steered in a similar manner. Rochester Electronics Manufactured Components Rochester branded components are manufactured using either die/wafers purchased from the original suppliers or Rochester wafers recreated from the original IP. All re-creations are done with the approval of the Original Component Manufacturer (OCM). Parts are tested using original factory test programs or Rochester developed test solutions to guarantee product meets or exceeds the OCM data sheet. Quality Overview • ISO-9001 • AS9120 certification • Qualified Manufacturers List (QML) MIL-PRF-35835 • Class Q Military • Class V Space Level • Qualified Suppliers List of Distributors (QSLD) • Rochester is a critical supplier to DLA and meets all industry and DLA standards. Rochester Electronics, LLC is committed to supplying products that satisfy customer expectations for quality and are equal to those originally supplied by industry manufacturers. The original manufacturer’s datasheet accompanying this document reflects the performance and specifications of the Rochester manufactured version of this device. Rochester Electronics guarantees the performance of its semiconductor products to the original OCM specifications. ‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. FOR REFERENCE ONLY © 2019 Rochester Electronics, LLC. All Rights Reserved 05032019 To learn more, please visit www.rocelec.com • 2589662 0010631 690 •cYP CY7C420, CY7C421 CY7C424, CY7C425 CYPRESS SEMICONDUCTOR -- 65E D Features Cascadable 512 x 9 FIFO Cascadable 1K x 9 FIFO Cascadable 2K x 9 FIFO 33.3 MHz. The write operation occurs when the write (W) signal is LOW. Read occurswhenread(R) goes LOW. The nine data outputs go to the high-impedance state when R is IDGR • TIL compatible • Three-state outputs • Pin compatible and functional equivalent to IDT7201, IDT7202, and IDT7203 • 512 X 91 11024 X 9, 21048 X 9 FIFO buffer memocy • Dual-port RAM cell • Asynchronous read/write • fflgh-speed 33.3-MHz read/write independent of depth/width • Low operating power -Ice (mBL)= 142 mA (commercial) -Ice (max.)= 147 mA (military) • • • • • CY7C428, CY7C429 CYPRESS SEMICONDUCTOR Functional Description A Half Full (HF) output flag is provided The CY7C420/CY7C421, CY7C424/ that is valid in the standalone andwidth ex­ CY7C425, and CY7C428/CY7C429 are pansion configurations. In the depth ex­ first-in fust-out (FIFO) memories offered pansion configuration, this pin provides in 600-mil wide and 300-mil wide pack­ the expansion out (XO)information that is ages. They are, respectively, 512, 1,024, used to tell the nextFIFO that itwill be ac­ and 2,048words by 9-bitswide.EachFIFO tivated. memory is organized such that the data is read in the same sequential order that it In the standalone and width expansion was written. Full and Empty flags are pro­ configurations, a LOW on the retransmit vided to prevent overrun and underrun. (RI) input causes theFIFOs to retransmit Three additional pins are also provided to the data. Read enable(R) and write enable facilitate unlimited expansion in width, (W) must both be IDGH during retrans­ depth, or both. The depth expansion tech­ mit, and then R is used to access the data. nique steers the control signals from one The CY7C420, CY7C421, CY7C424, device to another in parallel, thus eliminat­ CY7C425, CY7C428, and CY7C429 are ing the serial addition of propagation de­ fabricated using an advanced 0.8-micron lays, so that throughput is not reduced N-wellCMOS technology. JnputESDpro­ Data is steered in a similar manner. tection is greater than 2000V and latch-up The read and write operations may be is prevented by careful layout, guard rings, asynchronous; each can occur at a rate of and a substrate bias generator. Half Full flag in standalone Empty and Full flags Retransmit in standalone Expandable in width and depth Parallel cascade minimizes bubble-through • 5V ± 10% supply • 300-mil DIP packaging • 300-mil SOJ packaging Logic Block Diagram Pin Configurations DATA INPUTS (Do-Da) PLCC/LCC DIP Top View Top View d., d01::: � >'d ov oin w WRITE CONTROL D2 Do 0-, D1 READ POINTER NG "FORT El' a, XO/HF °" a, NC a, DATA OUTPUTS (Oo-Oa) li E�\'c IMI "FORT i---+---+J--r►FI' L___ E' o ::::::::::::.::::.::::.;:LEXrtGs:1h_NJ----XO/RI' -=:: C420-1 5-26 cf' cJ"