CY7C429-30VC

19/21/25/29/ CY7C419/21/25/29/33 256/512/1K/2K/4K x 9 Asynchronous FIFO Features • • • • • • • • • • • • • • • Asynchronous first-in first-out (FIFO) buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421) 1K x 9 (CY7C425) 2K x 9 (CY7C429) 4K x 9 (CY7C433) Dual-ported RAM cell High-speed 50.0-MHz read/write independent of depth/width Low operating power: ICC = 35 mA Empty and Full flags (Half Full flag in standalone) TTL compatible Retransmit in standalone Expandable in width PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP Pin compatible and functionally equivalent to IDT7200, IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204 Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel, thus eliminating the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50.0 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high-impedance state when R is HIGH. A Half Full (HF) output flag is provided that is valid in the standalone and width expansion configurations. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and guard rings. Functional Description The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories offered in 600-mil wide and 300-mil wide packages. They are, respectively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide. Cypress Semiconductor Corporation Document #: 38-06001 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 30, 2002 CY7C419/21/25/29/33 Logic Block Diagram DATA INPUTS (D0–D 8) Pin Configurations PLCC/LCC Top View D 3 D 8 W NC Vcc D 4 D 5 4 3 2 1 323130 5 29 6 28 7 27 8 26 7C419 7C421/5/9 25 9 7C433 10 24 11 23 12 22 13 21 14 15 1617 181920 Q 3 Q 8 GND NC R Q 4 Q 5 W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND DIP Top View 28 1 27 2 26 3 4 25 5 24 7C419 6 7C420/1 23 7 7C424/5 22 8 7C428/9 21 7C432/3 9 20 10 19 11 18 12 17 13 16 15 14 Vcc D4 D5 D6 D7 FL/RT MR EF XO/HF Q7 Q6 Q5 Q4 R C420–3 W WRITE CONTROL WRITE POINTER RAM ARRAY 256 x 9 512 x 9 1024x 9 2048x 9 4096x 9 READ POINTER D2 D1 D0 XI FF Q0 Q1 NC Q2 D6 D7 NC FL/RT MR EF XO/HF Q7 Q6 C420–2 THREESTATE BUFFERS DATA OUTPUTS (Q0–Q 8) R READ CONTROL FLAG LOGIC RESET LOGIC MR FL/RT TQFP Top View D3 D8 W VCC D4 D2 EF FF 32 3130 29 28 27 26 25 D1 D0 NC NC XI FF Q0 Q1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 D5 D6 D7 FL/RT NC NC MR EF XO/HF Q7 XI EXPANSION LOGIC XO/HF C420–1 7C419 7C421/5/9 7C433 9 10 11 12 13 14 15 16 C420–4 Q2 Q3 Q8 GND R Q4 Q5 Q6 Selection Guide 256 x 9 512 x 9 (600-mil only) 512 x 9 1K x 9 (600-mil only) 1K x 9 2K x 9 (600-mil only) 2K x 9 4K x 9 (600-mil only) 4K x 9 Frequency (MHz) Maximum Access Time (ns) ICC1 (mA) 7C433–10 50 10 35 7C433–15 40 15 35 7C433–20 33.3 20 35 7C429–10 7C429–15 7C425–10 7C425–15 7C421–10 7C421–15 7C419–10 7C419–15 7C420–20 7C421–20 7C424–20 7C425–20 7C428–20 7C429–20 7C429–25 7C432–25 7C433–25 28.5 25 35 7C433–30 25 30 35 7C429–30 7C429–40 7C432–40 7C433–40 20 40 35 7C433–65 12.5 65 35 7C420–25 7C421–25 7C424–25 7C425–25 7C421–30 7C424–30 7C425–30 7C419–30 7C419–40 7C420–40 7C421–40 7C424–40 7C425–40 7C420–65 7C421–65 7C424–65 7C425–65 7C428–65 7C429–65 Maximum Rating [1] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State................................................ –0.5V to +7.0V DC Input Voltage ............................................ –0.5V to +7.0V Power Dissipation.......................................................... 1.0W Output Current, into Outputs (LOW)............................ 20 mA Static Discharge Voltage ........................................... >2000V (per MIL–STD–883, Method 3015) Latch-Up Current..................................................... >200 mA Note: 1. Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up. Document #: 38-06001 Rev. *A Page 2 of 22 CY7C419/21/25/29/33 Operating Range Range Commercial Industrial Military Ambient Temperature[2] 0°C to + 70°C –40°C to +85°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[3] 7C419–10, 15, 30, 40 7C420/1–10, 15, 20, 25, 30, 40, 65 7C424/5–10, 15, 20, 25, 30, 40, 65 7C428/9–10, 15, 20, 25, 30, 40, 65 7C432/3–10, 15, 20, 25, 30, 40, 65 Parameter Description VOH Output HIGH Voltage VOL VIH VIL IIX IOZ IOS Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Output Short Circuit Current[5] GND < VI < VCC R > VIH, GND < VO < VCC VCC = Max., VOUT = GND Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA Com’l Mil/Ind Min. 2.4 2.0 2.2 Note 4 –10 –10 Max. 0.4 VCC VCC 0.8 +10 +10 –90 Unit V V V V µA µA mA Electrical Characteristics Over the Operating Range[3] (continued) 7C419–10 7C421–10 7C425–10 7C429–10 7C433–10 Parameter ICC Description Operating Current Test Conditions VCC = Max., IOUT = 0 mA f = fMAX VCC = Max., IOUT = 0 mA F = 20 MHz All Inputs = VIH Min. Com’l Mil/Ind Com’l 35 85 7C419–15 7C421–15 7C425–15 7C429–15 7C433–15 65 100 35 7C420–20 7C421–20 7C424–20 7C425–20 7C428–20 7C429–20 7C433–20 55 90 35 7C420–25 7C421–25 7C424–25 7C425–25 7C429–25 7C432–25 7C433–25 Unit mA 50 80 35 mA Min. Max. Min. Max. Min. Max. Min. Max. ICC1 Operating Current ISB1 ISB2 Standby Current Com’l Mil/Ind Com’l Mil/Ind 10 5 10 15 5 8 10 15 5 8 10 15 5 8 mA mA Power-Down Current All Inputs > VCC – 0.2V Notes: 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. VIL (Min.) = –2.0V for pulse durations of less than 20 ns. 5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document #: 38-06001 Rev. *A Page 3 of 22 CY7C419/21/25/29/33 Electrical Characteristics Over the Operating Range[3] (continued) 7C419–30 7C421–30 7C424–30 7C425–30 7C429–30 7C433–30 Parameter ICC Description Operating Current Test Conditions VCC = Max., IOUT = 0 mA f = fMAX VCC = Max., IOUT = 0 mA F = 20 MHz All Inputs = VIH Min. All Inputs > VCC – 0.2V Com’l Mil/Ind Com’l Min. Max. 40 75 35 7C419–40 7C420–40 7C421–40 7C424–40 7C425–40 7C429–40 7C432–40 7C433–40 Min. Max. 35 70 35 7C420–65 7C421–65 7C424–65 7C425–65 7C428–65 7C429–65 7C433–65 Min. Max. 35 65 35 mA Units mA ICC1 Operating Current ISB1 ISB2 Standby Current Power-Down Current Com’l Mil Com’l Mil 10 15 5 8 10 15 5 8 10 15 5 8 mA mA Capacitance[6] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 4.5V Max. 6 6 Unit pF pF Note: 6. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIGAND SCOPE R2 333 Ω C420–6 R1 500 Ω 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R1 500 Ω 3.0V R2 333 Ω C420–7 ALL INPUT PULSES 90% 10% 90% 10% GND ≤ 3 ns ≤ 3 ns C420–8 (a) (b) Equivalent to: THÉVENIN EQUIVALENT 200 Ω OUTPUT 2V Document #: 38-06001 Rev. *A Page 4 of 22 CY7C419/21/25/29/33 Switching Characteristics Over the Operating Range[7, 8] 7C419–10 7C421–10 7C425–10 7C429–10 7C433–10 Parameter tRC tA tRR tPR tLZR[6,9] tDVR tWC tPW tHWZ[6,9] tWR tSD tHD tMRSC tPMR tRMR tRPW tWPW tRTC tPRT tRTR [9,10] 7C419–15 7C421–15 7C425–15 7C429–15 7C433–15 Min. 25 Max. 15 10 15 3 5 10 20 3 5 15 25 15 5 10 8 0 25 15 10 15 15 25 15 10 30 20 5 10 12 0 30 20 10 20 20 30 20 10 15 35 25 5 10 15 0 35 25 10 25 25 35 25 10 7C420–20 7C421–20 7C424–20 7C425–20 7C428–20 7C429–20 7C433–20 Min. 30 20 10 25 3 5 18 Max. 7C420–25 7C421–25 7C424–25 7C425–25 7C429–25 7C432–25 7C433–25 Min. 35 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Read Cycle Time Access Time Read Recovery Time Read Pulse Width Read LOW to Low Z Data Valid After Read HIGH Read HIGH to High Z Write Cycle Time Write Pulse Width Write HIGH to Low Z Write Recovery Time Data Set-Up Time Data Hold Time MR Cycle Time MR Pulse Width MR Recovery Time Read HIGH to MR HIGH Write HIGH to MR HIGH Retransmit Cycle Time Retransmit Pulse Width Retransmit Recovery Time Min. 20 Max. 10 10 10 3 5 15 20 10 5 10 6 0 20 10 10 10 10 20 10 10 tHZR[6,9,10] Notes: 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30 pF load capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified. 8. See the last page of this specification for Group A subgroup testing information. 9. tHZR transition is measured at +200 mV from VOL and –200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured at ±100 mV from the steady state. 10. tHZR and tDVR use capacitance loading as in part (b) of AC Test Load and Waveforms. Document #: 38-06001 Rev. *A Page 5 of 22 CY7C419/21/25/29/33 Switching Characteristics Over the Operating Range[7, 8] (continued) 7C419–10 7C421–10 7C425–10 7C429–10 7C433–10 Parameter tEFL tHFH tFFH tREF tRFF tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tXOL tXOH MR to EF LOW MR to HF HIGH MR to FF HIGH Read LOW to EF LOW Read HIGH to FF HIGH Write HIGH to EF HIGH Write LOW to FF LOW Write LOW to HF LOW Read HIGH to HF HIGH Effective Read from Write HIGH Effective Read Pulse Width After EF HIGH Effective Write from Read HIGH Effective Write Pulse Width After FF HIGH Expansion Out LOW Delay from Clock Expansion Out HIGH Delay from Clock 10 10 10 10 10 15 15 15 Description Min. Max. 20 20 20 10 10 10 10 10 10 10 15 15 20 20 20 7C419–15 7C421–15 7C425–15 7C429–15 7C433–15 Min. Max. 25 25 25 15 15 15 15 15 15 15 20 20 25 25 25 7C420–20 7C421–20 7C424–20 7C425–20 7C428–20 7C429–20 7C433–20 Min. Max. 30 30 30 20 20 20 20 20 20 20 25 25 7C420–25 7C421–25 7C424–25 7C425–25 7C429–25 7C432–25 7C433–25 Min. Max. 35 35 35 25 25 25 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Document #: 38-06001 Rev. *A Page 6 of 22 CY7C419/21/25/29/33 Switching Characteristics Over the Operating Range[7, 8] (continued) 7C419–30 7C421–30 7C424–30 7C425–30 7C429–30 7C433–30 Parameter tRC tA tRR tPR tLZR[6,9] tDVR[9,10] tHZR[6,9,10] tWC tPW tHWZ[6,9] tWR tSD tHD tMRSC tPMR tRMR tRPW tWPW tRTC tPRT tRTR tEFL tHFH tFFH tREF tRFF tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tXOL tXOH Access Time Read Recovery Time Read Pulse Width Read LOW to Low Z Data Valid After Read HIGH Read HIGH to High Z Write Cycle Time Write Pulse Width Write HIGH to Low Z Write Recovery Time Data Set-Up Time Data Hold Time MR Cycle Time MR Pulse Width MR Recovery Time Read HIGH to MR HIGH Write HIGH to MR HIGH Retransmit Cycle Time Retransmit Pulse Width Retransmit Recovery Time MR to EF LOW MR to HF HIGH MR to FF HIGH Read LOW to EF LOW Read HIGH to FF HIGH Write HIGH to EF HIGH Write LOW to FF LOW Write LOW to HF LOW Read HIGH to HF HIGH Effective Read from Write HIGH Effective Read Pulse Width After EF HIGH Effective Write from Read HIGH Effective Write Pulse Width After FF HIGH Expansion Out LOW Delay from Clock Expansion Out HIGH Delay from Clock 30 30 30 30 30 40 40 40 40 30 5 10 18 0 40 30 10 30 30 40 30 10 40 40 40 30 30 30 30 30 30 30 40 35 65 65 65 10 30 3 5 20 50 40 5 10 20 0 50 40 10 40 40 50 40 10 50 50 50 35 35 35 35 35 35 35 65 60 Description Read Cycle Time Min. 40 30 10 40 3 5 20 80 65 5 15 30 0 80 65 15 65 65 80 65 15 80 80 80 60 60 60 60 60 60 60 Max. 7C419–40 7C420–40 7C421–40 7C424–40 7C425–40 7C429–40 7C432–40 7C433–40 Min. 50 40 15 65 3 5 20 Max. 7C420–65 7C421–65 7C424–65 7C425–65 7C428–65 7C429–65 7C433–65 Min. 80 65 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Document #: 38-06001 Rev. *A Page 7 of 22 CY7C419/21/25/29/33 Switching Waveforms Asynchronous Read and Write tRC tA R tLZR Q0–Q 8 tPW W tSD D0–D 8 tHD DATA VALID C420–9 tRR tPR tA tDVR DATA VALID tWC tWR tHZR DATA VALID DATA VALID Master Reset tMRSC MR R, W [11] [12] tPMR tRPW tWPW tEFL EF tHFH HF tFFH FF C420–10 tRMR Half-Full Flag HALF FULL W tRHF R tWHF HF HALF FULL+1 HALF FULL C420–11 Notes: 11. W and R ≥ VIH around the rising edge of MR. 12. tMRSC = tPMR + tRMR. Document #: 38-06001 Rev. *A Page 8 of 22 CY7C419/21/25/29/33 Switching Waveforms (continued) Last Write to First Read Full Flag ADDITIONAL READS LAST WRITE R FIRST READ FIRST WRITE W tWFF FF tRFF C420–12 Last Read to First Write Empty Flag LAST READ W FIRST WRITE ADDITIONAL WRITES FIRST READ R tREF EF tA VALID VALID tWEF DATA OUT C420–13 Retransmit [13] tRTC[14] tPRT FL/RT R,W tRTR C420–14 Notes: 13. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC. 14. tRTC = tPRT + tRTR. Document #: 38-06001 Rev. *A Page 9 of 22 CY7C419/21/25/29/33 Switching Waveforms (continued) Empty Flag and Read Data Flow-Through Mode DATA IN W tRAE R tREF EF tRPE tWEF tHWZ tA DATA VALID C420–15 DATA OUT Full Flag and Write Data Flow-Through Mode R tWAF W tRFF tWFF tWPF FF tHD DATA IN tA DATA OUT DATA VALID C420–16 DATA VALID tSD Document #: 38-06001 Rev. *A Page 10 of 22 CY7C419/21/25/29/33 Switching Waveforms (continued) Expansion Timing Diagrams WRITE TO LAST PHYSICAL LOCATION OF DEVICE 1 W tWR [15] WRITE TO FIRST PHYSICAL LOCATION OF DEVICE 2 tXOL tXOH XO1(XI2) tSD D0–D 8 tHD tSD tHD DATA VALID DATA VALID C420–17 READ FROM LAST PHYSICAL LOCATION OF DEVICE 1 R tRR tXOL tXOH READ FROM FIRST PHYSICAL LOCATION OF DEVICE 2 XO1(XI2) [15] tHZR tLZR Q0–Q 8 tA tDVR DATA VALID tA tDVR DATA VALID C420–18 Note: 15. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2). Architecture The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048, 4096 words of 9 bits each (implemented by an array of dual-port RAM cells), a read pointer, a write pointer, control signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags. Dual-Port RAM The dual-port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment the read and write pointers is much less than the time that would be required for data propagation through the memory, which would be the case if the memory were implemented using the conventional register array architecture. Resetting the FIFO Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W) must be HIGH tRPW/tWPW before and tRMR after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state. Document #: 38-06001 Rev. *A Page 11 of 22 CY7C419/21/25/29/33 Writing Data to the FIFO The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (D0–D8) tSD before and tHD after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs tWEF after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW tWHF after the falling edge of W following the FIFO actually being Half Full. Therefore, the HF is active once the FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tRHF after the rising edge of R when the FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. FF goes LOW tWFF after the falling edge of W, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tRFF after a read from a full FIFO. Reading Data from the FIFO The falling edge of R initiates a read cycle if the EF is not LOW. Data outputs (Q0–Q8) are in a high-impedance condition between read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. The rising edge of R causes the data outputs to go to the high-impedance state and remain such until a write is performed. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read tWEF after a valid write. The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and tRTR after retransmit is LOW. With every read cycle after retransmit, previously accessed data as well as not previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. Up to the full depth of the FIFO can be repeatedly retransmitted. Standalone/Width Expansion Modes Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. Depth Expansion Mode (see Figure 1) Depth expansion mode is entered when, during a MR cycle, Expansion Out (XO) of one device is connected to Expansion In (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and pulsed LOW again when the last physical location is read. Only one FIFO is enabled for read and one for write at any given time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created of word widths in increments of 9. When expanding in depth, a composite FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode. Use of the Empty and Full Flags In order to achieve the maximum frequency, the flags must be valid at the beginning of the next cycle. However, because they can be updated by either edge of the read of write signal, they must be valid by one-half of a cycle. Cypress FIFOs meet this requirement; some competitors’ FIFOs do not. The reason why the flags are required to be valid by the next cycle is fairly complex. It has to do with the “effective pulse width violation” phenomenon, which can occur at the full and empty boundary conditions, if the flags are not properly used. The empty flag must be used to prevent reading from an empty FIFO and the full flag must be used to prevent writing into a full FIFO. For example, consider an empty FIFO that is receiving read pulses. Because the FIFO is empty, the read pulses are ignored by the FIFO, and nothing happens. Next, a single word is written into the FIFO, with a signal that is asynchronous to the read signal. The (internal) state machine in the FIFO goes from empty to empty+1. However, it does this asynchronously with respect to the read signal, so that it cannot be determined what the effective pulse width of the read signal is, because the state machine does not look at the read signal until it goes to the empty+1 state. In a similar manner, the minimum write pulse width may be violated by attempting to write into a full FIFO, and asynchronously performing a read. The empty and full flags are used to avoid these effective pulse width violations, but in order to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next cycle. Document #: 38-06001 Rev. *A Page 12 of 22 CY7C419/21/25/29/33 XO W FF 9 D 9 EF 9 Q R CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 FL VCC XI XO FULL 9 FF EF EMPTY CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 FL XI XO * FF 9 MR CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 EF FL XI * FIRST DEVICE C420–19 Figure 1. Depth Expansion Document #: 38-06001 Rev. *A Page 13 of 22 CY7C419/21/25/29/33 Ordering Information Speed (ns) 10 Ordering Code CY7C419–10AC CY7C419–10JC CY7C419–10PC CY7C419–10VC 15 CY7C419–15AC CY7C419–15JC CY7C419–15VC CY7C419–15JI 30 40 CY7C419–30JC CY7C419–40AC CY7C419–40JC Package Type A32 J65 P21 V21 A32 J65 V21 J65 J65 A32 J65 Package Type 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier Industrial Commercial Commercial Operating Range Commercial Ordering Information (continued) Speed (ns) 25 40 65 Ordering Code CY7C420–25PC CY7C420–40PC CY7C420–65PC Package Type P15 P15 P15 Package Type 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) Molded DIP Operating Range Commercial Ordering Information (continued) Speed (ns) 10 Ordering Code CY7C421–10AC CY7C421–10JC CY7C421–10PC CY7C421–10VC 15 CY7C421–15AC CY7C421–15JC CY7C421–15JI CY7C421–15VI CY7C421–15DMB CY7C421–15LMB 20 CY7C421–20JC CY7C421–20PC CY7C421–20VC CY7C421–20JI 25 CY7C421–25JC CY7C421–25PC CY7C421–25VC CY7C421–25JI CY7C421–25PI CY7C421–25DMB 30 CY7C421–30JC CY7C421–30PC Document #: 38-06001 Rev. *A Package Type A32 J65 P21 V21 A32 J65 J65 V21 D22 L55 J65 P21 V21 J65 J65 P21 V21 J65 P21 D22 J65 P21 Package Type 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) CerDIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP Page 14 of 22 Military Commercial Industrial Industrial Commercial Commercial Military Industrial Commercial Operating Range Commercial CY7C419/21/25/29/33 Ordering Information (continued) Speed (ns) 30 Ordering Code CY7C421–30JI CY7C421–30DMB CY7C421–30LMB 40 CY7C421–40JC CY7C421–40PC CY7C421–40VC CY7C421–40JI 65 CY7C421–65JC CY7C421–65PC CY7C421–65VC CY7C421–65JI CY7C421–65DMB Package Type J65 D22 L55 J65 P21 V21 J65 J65 P21 V21 J65 D22 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) CerDIP Industrial Military Industrial Commercial Commercial Operating Range Industrial Military Ordering Information (continued) Speed (ns) 40 65 Ordering Code CY7C424–40PC CY7C424–65PC Package Type P15 P15 Package Type 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) Molded DIP Operating Range Commercial Commercial Ordering Information (continued) Speed (ns) 10 Ordering Code CY7C425–10AC CY7C425–10JC CY7C425–10PC CY7C425–10VC 15 CY7C425–15JC CY7C425–15PC CY7C425–15DMB CY7C425–15LMB 20 CY7C425–20JC CY7C425–20PC CY7C425–20VC 25 CY7C425–25JC CY7C425–25PC CY7C425–25JI CY7C425–25VI CY7C425–25DMB CY7C425–25LMB 30 CY7C425–30JC CY7C425–30PC CY7C425–30VC CY7C425–30VI Package Type A32 J65 P21 V21 J65 P21 D22 L55 J65 P21 V21 J65 P21 J65 V21 D22 L55 J65 P21 V21 V21 Package Type 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ Industrial Commercial Military Industrial Commercial Commercial Military Commercial Operating Range Commercial Document #: 38-06001 Rev. *A Page 15 of 22 CY7C419/21/25/29/33 Ordering Information (continued) Speed (ns) 40 Ordering Code CY7C425–40JC CY7C425–40PC CY7C425–40VC CY7C425–40JI 65 CY7C425–65JC CY7C425–65PC Package Type J65 P21 V21 J65 J65 P21 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP Industrial Commercial Operating Range Commercial Ordering Information (continued) Speed (ns) 20 25 65 Ordering Code CY7C428–20PC CY7C428–25DMB CY7C428–65PC Package Type P15 D16 P15 Package Type 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) CerDIP 28-Lead (600-Mil) Molded DIP Operating Range Commercial Military Commercial Ordering Information (continued) Speed (ns) 10 Ordering Code CY7C429–10AC CY7C429–10JC CY7C429–10PC 15 CY7C429–15JC CY7C429–15JI CY7C429–15DMB CY7C429–15LMB 20 CY7C429–20JC CY7C429–20PC CY7C429–20VC CY7C429–20DMB 25 CY7C429–25JC CY7C429–25PC CY7C429–25VC CY7C429–25JI CY7C429–25DMB CY7C429–25LMB 30 CY7C429–30JC CY7C429–30PC CY7C429–30VC CY7C429–30DMB 40 CY7C429–40AC CY7C429–40JC CY7C429–40PC 65 CY7C429–65JC CY7C429–65PC CY7C429–65JI Package Type A32 J65 P21 J65 J65 D22 L55 J65 P21 V21 D22 J65 P21 V21 J65 D22 L55 J65 P21 V21 D22 A32 J65 P21 J65 P21 J65 Package Type 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier Industrial Commercial Military Commercial Commercial Industrial Military Military Commercial Commercial Commercial Industrial Military Operating Range Commercial Document #: 38-06001 Rev. *A Page 16 of 22 CY7C419/21/25/29/33 Ordering Information (continued) Speed (ns) 25 40 Ordering Code CY7C432–25PC CY7C432–40PC Package Name P15 P15 Package Type 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) Molded DIP Operating Range Commercial Commercial Ordering Information (continued) Speed (ns) 10 Ordering Code CY7C433–10AC CY7C433–10JC CY7C433–10PC CY7C433–10VC 15 CY7C433–15AC CY7C433–15JC CY7C433–15JI CY7C433–15PI CY7C433–15DMB CY7C433–15LMB 20 CY7C433–20AC CY7C433–20JC CY7C433–20PC 25 CY7C433–25JC CY7C433–25PC CY7C433–25VC CY7C433–25JI 30 CY7C433–30JC CY7C433–30PC CY7C433–30JI CY7C433–30PI CY7C433–30DMB CY7C433–30LMB 40 CY7C433–40JC CY7C433–40PC CY7C433–40VC CY7C433–40JI 65 CY7C433–65JC CY7C433–65PC Package Name A32 J65 P21 V21 A32 J65 J65 P21 D22 L55 A32 J65 P21 J65 P21 V21 J65 J65 P21 J65 P21 D22 L55 J65 P21 V21 J65 J65 P21 Package Type 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Pin Thin Plastic Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP Industrial Commercial Commercial Military Industrial Industrial Commercial Commercial Commercial Military Industrial Commercial Operating Range Commercial Document #: 38-06001 Rev. *A Page 17 of 22 CY7C419/21/25/29/33 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters VOH VOL VIH VIL Max. IIX ICC ICC1 ISB1 ISB2 IOS Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tA tRR tPR tDVR tWC tPW tWR tSD tHD tMRSC tPMR tRMR tRPW tWPW tRTC tPRT tRTR tEFL tHFH tFFH tREF tRFF tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tXOL tXOH Switching Characteristics Parameters tRC Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Document #: 38-06001 Rev. *A Page 18 of 22 CY7C419/21/25/29/33 Package Diagrams 32-Lead Thin Plastic Quad Flat Pack A32 28-Lead (600-Mil) CerDIP D16 MIL-STD-1835 D- 10Config.A 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D- 15 Config.A Document #: 38-06001 Rev. *A Page 19 of 22 CY7C419/21/25/29/33 Package Diagrams (continued) 32-Lead Plastic Leaded Chip Carrier J65 32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 28-Lead (600-Mil) Molded DIP P15 Document #: 38-06001 Rev. *A Page 20 of 22 CY7C419/21/25/29/33 Package Diagrams (continued) 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Molded SOJ V21 Document #: 38-06001 Rev. *A Page 21 of 22 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C419/21/25/29/33 Document Title: CY7C419, CY7C421, CY7C425, CY7C429, CY7C433 256/512/1K/2K/4Kx9 Asynchronous FIFO Document Number: 38-06001 REV. ** *A ECN NO. 106462 122332 Issue Date 07/11/01 12/30/02 Orig. of Change SZV RBI Description of Change Change from Spec Number: 38-00079 to 38-06001 Added power up requirements to maximum ratings information. Document #: 38-06001 Rev. *A Page 22 of 22