CY7C43684AV-7AC

CY7C43644AV CY7C43664AV CY7C43684AV 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching Features • 3.3V high-speed, low-power, bidirectional, First-In First-Out (FIFO) memories w/ bus matching capabilities • 1K × 36 × 2 (CY7C43644AV) • 4K × 36 × 2 (CY7C43664AV) • 16K × 36 × 2 (CY7C43684AV) • 0.25-micron CMOS for optimum speed/power • High-speed 133-MHz operation (7.5-ns Read/Write cycle times) • Low power — ICC= 60 mA — ISB= 10 mA Table 1. • Fully asynchronous and simultaneous Read and Write operation permitted • Mailbox bypass register for each FIFO • Parallel and Serial Programmable Almost Full and Almost Empty flags • Retransmit function • Standard or FWFT user selectable mode • Partial Reset • Big or Little Endian format for word or byte bus sizes • 128-pin TQFP packaging • Easily expandable in width and depth Logic Block Diagram MBF1 CLKA CSA W/RA ENA MBA RT2 1K/4K/16K × 36 Dual Ported Memory (FIFO 1) Bus Matching Port A Control Logic Input Register Mail1 Register CLKB CSB W/RB ENB MBB RTI BM SIZE Register MRS1 PRS1 FIFO1, Mail1 Reset Logic Write Pointer Read Pointer FFA/IRA AFA Status Flag Logic Output Port B Control Logic EFB /ORB AEB SPM FS0/SD FS1/SEN A0–35 EFA/ORA AEA 36 Programmable Flag Offset Registers Timing Mode 36 B0–35 BE/FWFT Status Flag Logic Write Pointer Read Pointer FFB/IRB AFB 1K/4K/16K × 36 Dual Ported Memory (FIFO 2) Mail2 Register MBF2 Cypress Semiconductor Corporation Document #: 38-06025 Rev. *C Output Register • 3901 North First Street • San Jose Input Register FIFO1, Mail1 Reset Logic MRS2 PRS2 • CA 95134 • 408-943-2600 Revised December 26, 2002 CY7C43644AV CY7C43664AV CY7C43684AV Table 1. Pin Configuration[1] TQFP Top View CSA FFA/IRA EFA/ORA PRS1 VCC AFA AEA MBF2 MBA MRS1 FS0/SD NC GND FS1/SEN MRS2 MBB EFB/ORB FFB/IRB GND CSB W/RB ENB 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 W/RA ENA CLKA GND A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/FWFT GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 RT2 A12 GND A11 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 MBF1 VCC AEB AFB CY7C43644AV CY7C43664AV CY7C43684AV CLKB PRS2 VCC B35 B34 B33 B32 GND NC B31 B30 B29 B28 B27 B26 RT1 B25 B24 BM GND B23 B22 B21 B20 B19 B18 GND B17 B16 SIZE VCC B15 B14 B13 B12 GND B11 B10 A9 A8 A7 A6 GND A5 A4 A3 SPM VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 Note: 1. Pin-compatible to IDT7236X4 family. Document #: 38-06025 Rev. *C GND B6 VCC B7 B8 B9 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Page 2 of 37 CY7C43644AV CY7C43664AV CY7C43684AV Functional Description The CY7C436X4AV is a monolithic, high-speed, low-power, CMOS Bidirectional Synchronous FIFO memory which supports clock frequencies up to 133 MHz and has Read access times as fast as 6 ns. Two independent 1K/4K/16K × 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or Little Endian configurations. The CY7C436X4AV is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers’ width matches the selected Port B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on the CY7C436X4AV: Master Reset and Partial Reset. Master Reset initializes the Read and Write pointers to the first location of the memory array, configures the FIFO for Big or Little Endian byte arrangement and selects serial flag programming, parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or 64. Each FIFO has its own independent Master Reset pin, MRS1 and MRS2. Partial Reset also sets the Read and Write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1 and PRS2. The CY7C436X4AV have two modes of operation: In the CY Standard mode, the first word written to an empty FIFO is deposited into the memory array. A Read operation is required to access that word (along with all other words residing in memory). In the First-Word Fall-Through mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no Read operation required (nevertheless, accessing subsequent words does necessitate a formal Read request). The state of the BE/FWFT pin during FIFO operation determines the mode in use. Each FIFO has a combined Empty/Output Ready flag (EFA/ ORA and EFB/ORB) and a combined Full/Input Ready flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the CY Standard mode. EF indicates whether the memory is empty and FF indicates whether the FIFO memory is full. The IR and OR functions are selected in the First-Word FallThrough mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost Empty flag (AEA and AEB) and a programmable Almost Full flag (AFA and AFB). AEA and AEB are asserted when a selected number of words written to FIFO memory achieve a predetermined “almost empty state.” AFA and AFB are asserted when a selected number of words written to the memory achieve a predetermined “almost full state.” [2] IRA, IRB, AFA, and AFB are synchronized to the port clock that writes data into its array. ORA, ORB, AEA, and AEB are synchronized to the port clock that reads data from its array. Programmable offset for AEA, AEB, AFA, and AFB are loaded in parallel using Port A or in serial via the SD input. Three default offset settings are also provided. The AEA and AEB threshold can be set at 8, 16, or 64 locations from the empty boundary and AFA and AFB threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Two or more devices may be used in parallel to create wider data paths. A Retransmit feature is available on these devices. The CY7C436X4AV FIFOs are characterized for operation from 0°C to 70°C commercial, and from –40°C to 85°C industrial. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Selection Guide CY7C43644/64/84AV –7 Maximum Frequency Maximum Access Time Minimum Cycle Time Minimum Data or Enable Set-Up Minimum Data or Enable Hold Maximum Flag Delay Active Power Supply Current (ICC1) Commercial Industrial 133 6 7.5 3 0 6 60 CY7C43644/64/84AV –10 100 8 10 4 0 8 60 CY7C43644/64/84AV –15 66.7 10 15 5 0 10 60 60 Unit MHz ns ns ns ns ns mA Note: 2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to two clock cycles for flag deassertion, but the flag will always be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to Cypress’s application note entitled “Designing with CY7C436xx Synchronous FIFOs” for more details on flag uncertainties. Document #: 38-06025 Rev. *C Page 3 of 37 CY7C43644AV CY7C43664AV CY7C43684AV CY7C43644AV Density Package 1K × 36 × 2 128 TQFP CY7C43664AV 4K × 36 × 2 128 TQFP CY7C43684AV 16K × 36 × 2 128 TQFP Pin Definitions Signal Name A0–35 AEA Description Port A Data Port A Almost Empty Flag Port B Almost Empty Flag Port A Almost Full Flag Port B Almost Full Flag Port B Data Big Endian/ First-Word FallThrough Select I/O O Function Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register, X2.[2] Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register, X1.[2] Programmable Almost Full flag synchronized to CLKA (MHz). It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset register, Y1.[2] Programmable Almost Full flag synchronized to CLKB. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset register, Y2.[2] This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case, depending on the bus size, the most significant byte or word on Port A is transferred to Port B first for A-to-B data flow. For data flowing from port B to Port A, the first word/byte written to Port B will come out as the most significant word/ byte on port A. On the other hand, a LOW on BE will select Little Endian operation. In this case, the least significant byte or word on Port A is transferred to Port B first for Ato-B data flow. Similarly, the first word/byte written into port B will come out as the least significant word/byte on Port A for B-to-A data flow. After Master Reset, this pin selects the timing mode. A HIGH on BE/FWFT selects CY Standard mode, a LOW selects First-Word Fall-Through mode. Once the timing mode has been selected, the level on this pin must be static throughout device operation. A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation. CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all synchronized to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to HIGH transition of CLKA to Read or Write on Port A. The A0–35 are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to HIGH transition of CLKB to Read or Write on Port B. The B0–35 are in the high-impedance state when CSB is HIGH. This is a dual-function pin. In the CY Standard mode, the EFA function is selected. EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A0–35 outputs available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. I/O 36-bit bidirectional data port for side A. AEB O AFA O AFB O B0–35 BE/FWFT I/O 36-bit bidirectional data port for side B. I BM Bus Match Select (Port A) I CLKA Port A Clock I CLKB Port B Clock I CSA CSB EFA/ORA Port A Chip Select Port B Chip Select Port A Empty/ Output Ready Flag I I O Document #: 38-06025 Rev. *C Page 4 of 37 CY7C43644AV CY7C43664AV CY7C43684AV Pin Definitions (continued) Signal Name EFB/ORB Description Port B Empty/ Output Ready Flag I/O O Function This is a dual-function pin. In the CY Standard mode, the EFB function is selected. EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on B0–35 outputs available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to Read or Write data on Port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read or Write data on Port B. This is a dual-function pin. In the CY Standard mode, the FFA function is selected. FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA. This is a dual-function pin. In the CY Standard mode, the FFB function is selected. FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB. FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from Port A, and serial load. When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The number of bit Writes required to program the offset registers is 40 for the CY7C43644AV, 48 for the CY7C43664AV, and 56 for the CY7C43684AV. The first bit Write stores the Y-register MSB and the last bit Write stores the X-register LSB. A HIGH level on MBA chooses a mailbox register for a Port A Read or Write operation. When a Read operation is performed on Port A, a HIGH level on MBA selects data from the Mail2 register for output and a LOW level selects FIFO2 output register data for output. When a Write operation is performed on port A, a HIGH level on MBA will write the data into Mail1 register, while a LOW level will write the data into FIFO1. A HIGH level on MBB chooses a mailbox register for a Port B Read or Write operation. When a Read operation is performed on Port B, a HIGH level on MBB selects data from the Mail1 register for output and a LOW level selects FIFO1 output register data for output. When a Write operation is performed on port B, a HIGH level on MBB will write the data into Mail2 register, while a LOW level will write the data into FIFO2. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2 register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2. A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects the programming method (serial or parallel) and one of three programmable flag default offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW. ENA ENB FFA/IRA Port A Enable Port B Enable Port A Full/Input Ready Flag I I O FFB/IRB Port B Full/Input Ready Flag O FS1/SEN Flag Offset Select 1/Serial Enable Flag Offset Select 0/Serial Data I FS0/SD I MBA Port A Mailbox Select I MBB Port B Mailbox Select I MBF1 Mail1 Register Flag O MBF2 Mail2 Register Flag O MRS1 FIFO1 Master Reset I Document #: 38-06025 Rev. *C Page 5 of 37 CY7C43644AV CY7C43664AV CY7C43684AV Pin Definitions (continued) Signal Name MRS2 Description FIFO2 Master Reset I/O I Function A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW. A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location of memory and sets the Port A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by bringing the Read pointer back to location zero. The user will still need to perform Read operations to retransmit the data. Retransmit function applies to CY standard mode only. A LOW strobe on this pin will retransmit the data on FIFO2. This is achieved by bringing the Read pointer back to location zero. The user will still need to perform Read operations to retransmit the data. Retransmit function applies to CY standard mode only. A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation. A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming or default offsets (8, 16, or 64). A HIGH selects a Write operation and a LOW selects a Read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance state when W/RA is HIGH. A LOW selects a Write operation and a HIGH selects a Read operation on Port B for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance state when W/RB is LOW. PRS1 FIFO1 Partial Reset I PRS2 FIFO2 Partial Reset I RT1 Retransmit FIFO1 I RT2 Retransmit FIFO2 I SIZE Bus Size Select I SPM W/RA Serial Programming Port A Write/ Read Select Port B Write/ Read Select I I W/RB I Document #: 38-06025 Rev. *C Page 6 of 37 CY7C43644AV CY7C43664AV CY7C43684AV Signal Description Master Reset (MRS1, MRS2) Each of the two FIFO memories of the CY7C436X4AV undergoes a complete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can switch asynchronously to the clocks. A Master Reset initializes the internal Read and Write pointers and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master Reset must be performed on the FIFO after power up, before data is written to its memory. A LOW-to-HIGH transition on a FIFO Master Reset (MRS1, MRS2) input latches the value of the Big Endian (BE) input or determining the order by which bytes are transferred through Port B. A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2) input latches the values of the Flag select (FS0, FS1) and Serial Programming Mode (SPM) inputs for choosing the Almost Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset programming below). Partial Reset (PRS1, PRS2) Each of the two FIFO memories of the CY7C436X4AV undergoes a limited reset by taking its associated Partial Reset (PRS1, PRS2) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset initializes the internal Read and Write pointers and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA, AFB) HIGH. A Partial Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or CY Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient. Big Endian/First Word Fall Through (BE/FWFT) This is a dual-purpose pin. At the time of Master Reset, the BE select function is active, permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data are transferred through this port. For the following illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is configured for a long word size, the Big Endian function has no application and the BE input is a “Don’t Care.”) Document #: 38-06025 Rev. *C A HIGH on the BE/FWFT input when the Master Reset (MRS1 and MRS2) inputs go from LOW to HIGH will select a Big Endian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long-word written to Port A will be transferred to Port B first; the least significant byte (word) of the long word written to Port A will be transferred to Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be transferred to Port A as the most significant byte (word) of the long-word; the byte (word) written to Port B last will be transferred to Port A as the least significant byte (word) of the long-word. A LOW on the BE/FWFT input when the Master Reset (MRS1 and MRS2) inputs go from LOW to HIGH will select a Little Endian arrangement. When data is moving in the direction from Port A to Port B, the least significant byte (word) of the long word written to Port A will be transferred to Port B first; the most significant byte (word) of the long-word written to Port A will be transferred to Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be transferred to port A as the least significant byte (word) of the long-word; the byte (word) written to Port B last will be transferred to Port A as the most significant byte (word) of the long-word. After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: CY Standard mode or First-Word Fall-Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the BE/FWFT input at the second LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Standard mode. This mode uses the Empty Flag function (EFA, EFB) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function (FFA, FFB) to indicate whether or not the FIFO memory has any free space for writing. In CY Standard mode, every word read from the FIFO, including the first, must be requested using a formal Read operation. Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/FWFT input at the second LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A0–35 or B0–35). It also uses the Input Ready function (IRA, IRB) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no Read request necessary. Subsequent words must be accessed by performing a formal Read operation. Following Master Reset, the level applied to the BE/FWFT input to choose the desired timing mode must remain static throughout the FIFO operation. Programming the Almost Empty and Almost Full Flags Four registers in the CY7C436X4AV are used to hold the offset values for the Almost Empty and Almost Full flags. The Port B Almost Empty flag (AEB) offset register is labeled X1 and the Port A Almost Empty flag (AEA) offset register is labeled X2. The Port A Almost Full flag (AFA) offset register is labeled Y1 and the Port B Almost Full flag (AFB) offset register is labeled Y2. The index of each register name corresponds with preset values during the reset of a FIFO, programmed in parallel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 3). To load a FIFO’s Page 7 of 37 CY7C43644AV CY7C43664AV CY7C43684AV Almost Empty flag and Almost Full flag offset registers with one of the three preset values listed in Table 3, the Serial Program Mode (SPM) and at least one of the flag-select inputs must be HIGH during the LOW-to-HIGH transition of its Master Reset input (MRS1 and MRS2). For example, to load the preset value of 64 into X1 and Y1, SPM, FS0, and FS1 must be HIGH when FIFO1 reset (MRS1) returns HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with Master Reset (MRS2). When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at different times. To program the X1, X2, Y1, and Y2 registers in parallel from Port A, perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FS0 and FS1 LOW during the LOW-toHIGH transition of MRS1 and MRS2. After this reset is complete, the first four Writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the offset registers are (A0–9), (A0–11), or (A0–13), for the CY7C436X4AV, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 0 to 1023 for the CY7C43644AV; 0 to 4095 for the CY7C43664AV; 0 to 16383 for the CY7C43684AV.[2] After all the offset registers are programmed from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH and both FIFOs begin normal operation. To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-toHIGH transition of CLKA that the FS1/SEN input is LOW. Forty, forty-eight, or fifty-six bit Writes are needed to complete the programming for the CY7C436X4AV, respectively. The four registers are written in the order Y1, X1, Y2, and, finally, X2. The first-bit Write stores the most significant bit of the Y1 register and the last-bit Write stores the least significant bit of the X2 register. When the option to program the offset registers serially is chosen, the Port A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written. FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO1 operation. The Port B Full/Input ready (FFB/IRB) flag also remains LOW throughout the serial programming process, until all register bits are written. FFB/ IRB is set HIGH by the LOW-to-HIGH transition of CLKB after the last bit is loaded to allow normal FIFO2 operation. SPM, FS0/SD, and FS1/SEN function the same way in both CY Standard and FWFT modes. FIFO Write/Read Operation The state of the Port A data (A0–35) lines is controlled by Port A Chip Select (CSA) and Port A Write/Read Select (W/RA). The A0–35 lines are in the high-impedance state when either CSA or W/RA is HIGH. The A0–35 lines are active outputs when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0–35 inputs on a LOW-toHIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 4). FIFO Reads and Document #: 38-06025 Rev. *C Writes on Port A are independent of any concurrent Port B operation. The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read select (W/RA). The state of the Port B data (B0–35) lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0–35 lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0–35 lines are active outputs when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0–35 inputs on a LOW-toHIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 5). FIFO Reads and Writes on Port B are independent of any concurrent Port A operation. The set-up and hold time constraints to the port clocks for the port Chip Selects and Write/Read selects are only for enabling Write and Read operations and are not related to highimpedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the set-up and hold time window of the cycle. When operating the FIFO in FWFT mode and the Output Ready flag is LOW, the next word written is automatically sent to the FIFO’s output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the FIFO’s memory array is clocked to the output register only when a Read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in CY Standard mode, data residing in the FIFO’s memory array is clocked to the output register only when a Read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. Synchronized FIFO Flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/ ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Table 6 and Table 7 show the relationship of each port flag to FIFO1 and FIFO2. Empty/Output Ready Flags (EFA/ORA, EFB/ORB) These are dual-purpose flags. In the FWFT mode, the Output Ready (ORA, ORB) function is selected. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word remains in the FIFO output register and any FIFO reads are ignored. In the CY Standard mode, the Empty Flag (EFA, EFB) function is selected. When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for reading to the output register. When Empty Flag is LOW, the previous data word remains in the FIFO output register and any FIFO reads are ignored. The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT Page 8 of 37 CY7C43644AV CY7C43664AV CY7C43684AV and CY Standard modes, the FIFO Read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a Write pointer and Read pointer comparator that indicates when the FIFO SRAM status is empty, empty + 1, or empty + 2. In FWFT Mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. In the CY Standard mode, from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then will data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a Write if the clock transition occurs at time tSKEW1 or greater after the Write. Otherwise, the subsequent clock cycle can be the first synchronization cycle. Full/Input Ready Flags (FFA/IRA, FFB/IRB) This is a dual-purpose flag. In FWFT mode, the Input Ready (IRA and IRB) function is selected. In CY Standard mode, the Full Flag (FFA and FFB) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and any Writes to the FIFO are ignored. The Full/Input Ready flag of a FIFO is synchronized to the port clock that writes data to its array. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its Write pointer is incremented. The state machine that controls a Full/Input Ready flag monitors a Write pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full – 1, or full – 2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory Write location has been read. The second LOW-to-HIGH transition on the Full/ Input Ready flag synchronizing clock after the Read sets the Full/Input Ready flag HIGH. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a Read if the clock transition occurs at time tSKEW1 or greater after the Read. Otherwise, the subsequent clock cycle will be the first synchronization cycle. Almost Empty Flags (AEA, AEB) The Almost Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost Empty flag monitors a Write pointer and Read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty + 1, or almost empty + 2. The Almost Empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X + 2) or more words.[2] The Almost Empty flag is set HIGH by the first LOW-to-HIGH transition of its synchronizing clock after two FIFO Writes that fills memory to the (X + 2) level. A LOW-to-HIGH transition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the Write that fills the FIFO to (X + 2) words. Otherwise, the subsequent synchronizing clock cycle will be the first synchronization cycle. Almost Full Flags (AFA, AFB) The Almost Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost Full flag monitors a Write pointer and Read pointer comparator that indicates when the FIFO SRAM status is almost full, almost full – 1, or almost full – 2. The Almost Full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024 – Y), (4096 – Y), or (16384 – Y) for the CY7C436X4AV respectively. An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to [1024 – (Y + 2)], [4096 – (Y + 2)], or [16384 – (Y + 2)], for the CY7C436X4AV respectively.[2] The Almost Full flag is set HIGH by the first LOW-to-HIGH transition of its synchronizing clock after two FIFO reads that reduces the number of words in memory to [1024/4096/16384 – (Y + 2)]. A LOW-to-HIGH transition of an Almost Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the Read that reduces the number of words in memory to [1024/4096/16384 – (Y + 2)]. Otherwise, the subsequent synchronizing clock cycle will be the first synchronization cycle. Mailbox Registers Each FIFO has a 36-bit bypass register to pass command and control information between Port A and Port B without putting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port B. A LOW-to-HIGH transition on CLKA writes A0