CY7C472-25JI

1CY 7C47 4 CY7C470 CY7C472 CY7C474 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags Features • 8K x 9, 16K x 9, and 32K x 9 FIFO buffer memory • Asynchronous read/write • High-speed 33.3-MHz read/write independent of depth/width • Low operating power — ICC (max.) = 70 mA • Programmable Almost Full/Empty flag • Empty, Almost Empty, Half Full, Almost Full, and Full status flags • Programmable retransmit • Expandable in width • 5V ± 10% supply • TTL compatible • Three-state outputs • Proprietary 0.8-micron CMOS technology offered in 600-mil DIP, PLCC, and LCC packages. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Three status pins—Empty/Full (E/F), Programmable Almost Full/Empty (PAFE), and Half Full (HF)—are provided to the user. These pins are decoded to determine one of six states: Empty, Almost Empty, Less than Half Full, Greater than Half Full, Almost Full, and Full. The read and write operations may be asynchronous; each can occur at a rate of 33.3 MHz. The write operation occurs when the write (W) signal goes LOW. Read occurs when read (R) goes LOW. The nine data outputs go into a high-impedance state when R is HIGH. The user can store the value of the read pointer for retransmit by using the MARK pin. A LOW on the retransmit (RT) input causes the FIFO to resend data by resetting the read pointer to the value stored in the mark pointer. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFO to resend the data. With the mark feature, retransmit can start from any word in the FIFO. The CYC47X series is fabricated using a proprietary 0.8-micron N-well CMOS technology. Input ESD protection is greater than 2001V and latch-up is prevented by the use of reliable layout techniques, guard rings, and a substrate bias generator. Functional Description The CYC47X FIFO series consists of high-speed, low-power, first-in first-out (FIFO) memories with programmable flags and retransmit mark. The CY7C470, CY7C472, and CY7C474 are 8K, 16K, and 32K words by 9 bits wide, respectively. They are Logic Block Diagram DATAINPUTS (D0 –D8 ) Pin Configurations PLCC/LCC Top View W 4 PROGRAMMABLE FLAG REGISTER D2 D1 D0 MARK FLAG LOGIC HF E/F PAFE R RT MARK PAFE Q0 Q1 NC Q2 5 6 7 8 9 10 11 12 7C470 7C472 7C474 3 2 1 32 31 30 29 28 27 26 25 24 23 22 D8 D6 D7 NC RT MR E/F HF Q7 Q6 D3 D2 D1 D0 MARK PAFE Q0 Q1 Q2 Q3 Q8 GND MARK POINTER 7C470–2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 7C470 7C472 7C474 DIP Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc D4 D5 D6 D7 RT MR E/F HF Q7 Q6 Q5 Q4 R W WRITE POINTER RAM ARRAY 8K x 9 16K x 9 32K x 9 READ POINTER 13 21 14 15 16 17 18 19 20 7C470–3 THREE– STATE BUFFERS DATAOUTPUTS (Q0 –Q8 ) RESET LOGIC MR 7C470–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 1990 – Revised April 1995 CY7C470 CY7C472 CY7C474 Selection Guide 7C470–15 7C472–15 7C474–15 Frequency (MHz) Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military/Industrial 33.3 15 105 7C470–20 7C472–20 7C474–20 33.3 20 7C470–25 7C472–25 7C474–25 28.5 25 7C470–40 7C472–40 7C474–40 20 40 Maximum Ratings Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –3.0V to +7.0V Power Dissipation ..........................................................1.0W Output Current, into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Military[1] Ambient Temperature 0°C to +70°C –40°C to +85°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[2] 7C470–15 7C472–15 7C474–15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 IOS[3] Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current Power-Down Current Output Short Circuit Current GND ≤ VI ≤ VCC R ≥ VIH, GND ≤ VO ≤ VCC VCC = Max., Com’l IOUT = 0 mA Mil/Ind All Inputs = VIH Min. All Inputs = VCC – 0.2V Com’l Mil/Ind Com’l Mil/Ind –90 20 25 –90 –10 –10 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA Com’l Mil/Ind 0.8 +10 +10 105 110 25 30 –10 –10 2.2 2.2 0.8 +10 +10 –10 –10 Min. 2.4 0.4 Max. 7C470–20 7C472–20 7C474–20 Min. 2.4 0.4 2.2 2.2 0.8 +10 +10 90 95 25 30 20 25 –90 mA mA mA V µA µA mA Max. 7C470–25 7C472–25 7C474–25 Min. 2.4 0.4 Max. Unit V V V VCC = Max., VOUT = GND Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. 2 CY7C470 CY7C472 CY7C474 Electrical Characteristics Over the Operating Range[2] (continued) 7C470–40 7C472–40 7C474–40 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 IOS[3] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current Power-Down Current Output Short Circuit Current GND ≤ VI ≤ VCC R ≥ VIH, GND ≤ VO ≤ VCC VCC = Max., IOUT = 0 mA All Inputs = VIH Min. All Inputs = VCC – 0.2V VCC = Max., VOUT = GND Com’l Mil/Ind Com’l Mil/Ind Com’l Mil/Ind –10 –10 Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA Com’l Mil/Ind 2.2 2.2 0.8 +10 +10 70 75 25 30 20 25 –90 mA mA mA V µA µA mA Min. 2.4 0.4 Max. Unit V V V Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 4.5V Max. 10 12 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIGAND SCOPE Equivalent to: R2 333Ω 7C470–4 R1 500 Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R1 500 Ω 3.0V R2 333Ω 7C470–5 ALL INPUT PULSES 10% 90% 90% 10% ≤ 5 ns 7C470–6 GND ≤ 5 ns (a) (b) THÉVENIN EQUIVALENT 200Ω OUTPUT 2V Note: 4. Tested initially and after any design or process changes that may affect these parameters. 3 CY7C470 CY7C472 CY7C474 Switching Characteristics Over the Operating Range[5, 6] 7C470–15 7C472–15 7C474–15 Parameter tCY tA tRV tPW tLZR tDV[7] tHZ[7] tHWZ tSD tHD tEFD tEFL tHFD tAFED tRAE tWAF Description Cycle Time Access Time Recovery Time Pulse Width Read LOW to Low Z Valid Data from Read HIGH Read HIGH to High Z Write HIGH to Low Z Data Set-Up Time Data Hold Time E/F Delay MR to E/F LOW HF Delay PAFE Delay Effective Read from Write HIGH Effective Write from Read HIGH 15 15 5 11 0 15 25 25 25 20 20 15 15 3 3 15 5 12 0 20 30 30 30 25 25 Min. 30 15 10 20 3 3 15 5 15 0 25 35 35 35 40 40 Max. 7C470–20 7C472–20 7C474–20 Min. 30 20 10 25 3 3 18 5 20 0 40 50 50 50 Max. 7C470–25 7C472–25 7C474–25 Min. 35 25 10 40 3 3 25 Max. 7C470–40 7C472–40 7C474–40 Min. 50 40 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified. 6. See the last page of this specification for Group A subgroup testing information. 7. tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads. tHZR transition is measured at +500 mV from VOL and –500 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured at ±100 mV from the steady state. 4 CY7C470 CY7C472 CY7C474 Switching Waveforms Asynchronous Read and Write tCY tPW tA tA R tLZR Q0–Q 8 tPW W tRV tDVR DATA VALID tCY tRV tHZR DATA VALID tPW tSD D0–D 8 tHD tSD tHD 7C470–7 DATA VALID DATA VALID MasterReset (No Write to Programmable Flag Register) tCY MR R, W tHFD HF E/F tEFL PAFE tAFED 7C470–8 tPW tRV tRV Master Reset (Write to Programmable Flag tCY tPW MR Register)[8,9] tCY tRV tRV tPW W(R) tCY D0–D8 (Q0–Q8) VALID tRV tRV tHD 7C470–9 Notes: 8. Waveform labels in parentheses pertain to writing the programmable flag register from the output port (Q0 – Q8). 9. Master Reset (MR) must be pulsed LOW once prior to programming. 5 CY7C470 CY7C472 CY7C474 Switching Waveforms (Continued) E/F Flag (Last Write to First Read Full Flag) W FULL–1 FULL FULL–1 R tEFD E/F tEFD HF LOW 7C470–10 E/F Flag (Last Read to First Write Empty Flag) R EMPTY+1 EMPTY EMPTY+1 W tEFD E/F tEFD HF HIGH 7C470–11 Half Full Flag W HALF–FULL HALF–FULL +1 HALF–FULL R tHFD HF tHFD 7C470–12 6 CY7C470 CY7C472 CY7C474 Switching Waveforms (Continued) PAFE Flag (Almost Full) W R tAFED PAFE tAFED HF LOW 7C470–13 PAFE Flag (Almost Empty) R W tAFED PAFE tAFED HF HIGH 7C470–14 Retransmit[10] tCY W, R tCY RT tA tRV tPW tCY Q 0–Q 8 DATA VALID tRV tLZR FLAGS[10] FLAGS V ALID 7C470–15 Note: 10. The flags may change state during retransmit, but they will be valid a tCY later, except for the CY7C47X–20 (Military), whose flags will be valid after tCY + 10 ns. 7 CY7C470 CY7C472 CY7C474 Switching Waveforms (Continued) Mark tCY W, R tCY MARK tRV tPW tRV 7C470–16 Empty Flag and Read Data Flow-Through Mode DATA IN W tRAE R tPW tEFD E/F tEFD tHWZ DATA OUT DATA VALID tA 7C470–17 8 CY7C470 CY7C472 CY7C474 Switching Waveforms (Continued) Full Flag and Write Data Flow-Through Mode R tWAF W tEFD tEFD E/F tSD DATA IN tA DATA OUT DATA VALID 7C470–18 tPW tHD DATA VALID Architecture The CY7C470, CY7C472, and CY7C474 FIFOs consist of an array of 8,192, 16,384, and 32,768 words of 9 bits each, respectively. The control consists of a read pointer, a write pointer, a retransmit pointer, control signals (i.e., write, read, mark, retransmit, and master reset), and flags (i.e., Empty/Full, Half Full, and Programmable Almost Full/Empty). Resetting the FIFO Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (E/F) and Almost Full/Empty flag (PAFE) being LOW, and Half Full flag (HF) being HIGH. The read pointer, write pointer, and retransmit pointer are reset to zero. For a valid reset, Read (R) and Write (W) must be HIGH tRPW/tWPW before the falling edge and tRMR after the rising edge of MR. Writing Data to the FIFO Data can be written to the FIFO when it is not FULL[11]. A falling edge of W initiates a write cycle. Data appearing at the inputs (D0–D8) tSD before and tHD after the rising edge of W will be stored sequentially in the FIFO. Reading Data from the FIFO Data can be read from the FIFO when it is not empty[12]. A falling edge of R initiates a read cycle. Data outputs (Q0–Q8) are in a high-impedance condition when the FIFO is empty and between read operations (R HIGH). The falling edge of R during the last read cycle before the empty condition triggers a high-to-low transition of E/F, prohibiting any further read operations until tRFF after a valid write. Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and resent if necessary. Retransmission can start from anywhere in the FIFO and be repeated without limitation. The retransmit methodology is as follows: mark the current value of the read pointer, after an error in subsequent read operations return to that location and resume reading. This effectively resends all of the data from the mark point. When MARK is LOW, the current value of the read pointer is stored. This operation marks the beginning of the packet to be resent. When RT is LOW, the read pointer is updated with the mark location. During each subsequent read cycle, data is read and the read pointer incremented. Care must be taken when using the retransmit feature. Use the mark function such that the write pointer does not pass the mark pointer, because further write operations will overwrite data. Programmable Almost Full/Empty Flag The CY7C470/2/4 offer a variable offset for the Almost Empty and the Almost Full condition. The offset is loaded into the programmable flag register (PFR) during a master reset cycle. While MR is LOW, the PFR can be loaded from Q8–Q0 by pulsing R LOW or from D8–D0 by pulsing W LOW. The offset options are listed in Table 2. See Table 1 for a description of the six FIFO states. If the PFR is not loaded during master reset (R and W HIGH) the default offset will be 256 words from Full and Empty. Notes: 11. When the FIFO is less than half full, the flags make a LOW-to-HIGH transition on the rising edge of W and make the HIGH-to-LOW transition on the falling edge of R. If the FIFO is more than half full, the flags make the LOW-to-HIGH transition on the rising edge of R and HIGH-to-LOW transition on the falling edge of W. 12. Full and empty states can be decoded from the Half-Full (HF) and Empty/Full (E/F) flags. 9 CY7C470 CY7C472 CY7C474 Table 1. Flag Truth Table[13] CY77C470 (8K x 9) Number of Words in FIFO 0 1 ⇒(P – 1) P ⇒ 4096 4097 ⇒ (8192 – P) (8192 – P+1) ⇒ 8191 8192 CY77C472 (16K x 9) Number of Words in FIFO 0 1 ⇒ (P – 1) P ⇒ 8192 8193 ⇒ (16384 – P) (16384 – P+1) ⇒ 16383 16384 CY77C474 (32K x 9) Number of Words in FIFO 0 1 ⇒ (P – 1) P ⇒ 16384 16385 ⇒ (32768 – P) (32768 – P+1) ⇒ 32767 32768 HF 1 1 1 0 0 0 E/F 0 1 1 1 1 0 PAFE 0 0 1 1 0 0 Empty State Almost Empty Less than Half Full Greater than Half Full Almost Full Full Table 2. Programmable Almost Full/Empty Options[14] D3 0 0 0 0 0 0 0 0 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 PAFE Active when: 256 or less locations from Empty/Full (default) 16 or less locations from Empty/Full 32 or less locations from Empty/Full 64 or less locations from Empty/Full 128 or less locations from Empty/Full 256 or less locations from Empty/Full (default) 512 or less locations from Empty/Full 1024 or less locations from Empty/Full 2048 or less locations from Empty/Full 4098 or less locations from Empty/Full[15] 8192 or less locations from Empty/Full[16] P 256 16 32 64 128 256 512 1024 2048 4098 8192 Notes: 13. See Table 2 for P values. 14. Almost flags default to 256 locations from Empty/Full. 15. Only for CY7C472 and CY7C474. 16. Only for CY7C470. 10 CY7C470 CY7C472 CY7C474 Typical AC and DC Characteristics NORMALIZED tA vs.SUPPLY VOLTAGE 1.20 1.10 1.00 1.00 0.90 0.80 4.00 TA =25 °C 0.80 0.60 –55.00 VCC =5.0V 5.00 0.00 0.00 VCC =5.0V TA =25°C 500.00 CAPACITANCE (pF) NORMALIZED SUPPLY CURRENT vs.FREQUENCY 1.10 1.00 0.90 1.00 0.80 0.60 4.00 VIN =3.0V TA =25 °C f = 33 MHz 4.50 5.00 5.50 6.00 1.00 0.90 0.80 –55.00 VIN =3.0V TA =25°C f = 33 MHz 5.00 65.00 125.00 0.80 0.70 0.60 15.00 VCC =5.0V TA =25°C VIN =3.0V 1000.00 NORMALIZED tA vs. AMBIENT TEMPERATURE 1.60 1.40 1.20 10.00 TYPICAL tA CHANGE vs. OUTPUT LOADING 20.00 15.00 4.50 5.00 5.50 6.00 5.00 65.00 125.00 SUPPLY VOLTAGE(V) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.40 1.20 AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 20.00 25.00 30.00 35.00 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) FREQUENCY (MHz) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 50.00 40.00 30.00 20.00 10.00 0.00 0.00 VCC =5.0V TA =25°C 1.00 2.00 3.00 4.00 100.00 80.00 60.00 40.00 20.00 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE VCC =5.0V TA =25°C 0.00 0.00 1.00 2.00 3.00 4.00 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 11 CY7C470 CY7C472 CY7C474 Ordering Information Speed (ns) 15 Ordering Code CY7C470–15JC CY7C470–15PC CY7C470–15JI 20 25 CY7C470–20DMB CY7C470–20LMB CY7C470–25JC CY7C470–25PC CY7C470–25JI CY7C470–25DMB CY7C470–25LMB 40 CY7C470–40JC CY7C470–40PC CY7C470–40JI CY7C470–40DMB CY7C470–40LMB Speed (ns) 15 Package Name J65 P15 J65 D43 L55 J65 P15 J65 D43 L55 J65 P15 J65 D43 L55 Package Name J65 P15 J65 D43 L55 J65 P15 J65 D43 L55 J65 P15 J65 D43 L55 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier Operating Range Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Industrial Military Commercial Industrial Military Commercial Industrial Military Operating Range Commercial Ordering Code CY7C472–15JC CY7C472–15PC CY7C472–15JI Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier 20 25 CY7C472–20DMB CY7C472–20LMB CY7C472–25JC CY7C472–25PC CY7C472–25JI CY7C472–25DMB CY7C472–25LMB 40 CY7C472–40JC CY7C472–40PC CY7C472–40JI CY7C472–40DMB CY7C472–40LMB 12 CY7C470 CY7C472 CY7C474 Ordering Information (continued) Speed (ns) 15 Ordering Code CY7C474–15JC CY7C474–15PC CY7C474–15JI 20 25 CY7C474–20DMB CY7C474–20LMB CY7C474–25JC CY7C474–25PC CY7C474–25JI CY7C474–25DMB CY7C474–25LMB 40 CY7C474–40JC CY7C474–40PC CY7C474–40JI CY7C474–40DMB CY7C474–40LMB Package Name J65 P15 J65 D43 L55 J65 P15 J65 D43 L55 J65 P15 J65 D43 L55 Package Type 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP 32-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Sidebraze CerDIP 32-Pin Rectangular Leadless Chip Carrier Industrial Military Commercial Industrial Military Commercial Industrial Military Operating Range Commercial MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOS ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter tCY tA tRV tPW tLZR tDVR tHZR tHWZ tSD tHD tEFD tHFD tAFED tRAE tWAF Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Document #: 38–00142–H 13 CY7C470 CY7C472 CY7C474 Package Diagrams 28-Lead (600-Mil) Sidebraze DIP D43 32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 32-Lead Plastic Leaded Chip Carrier 14 CY7C470 CY7C472 CY7C474 Package Diagrams 28-Lead (600-Mil) Molded DIP P15 © Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.