CY7C4821-25AC

CY7C4831/4 1 CY7C4801/4811/4821 CY7C4831/4841/4851 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs Features • Double high speed, low power, first-in first-out (FIFO) memories • Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double 1K x 9 (CY7C4821) • Double 2K x 9 (CY7C4831) • Double 4K x 9 (CY7C4841) • Double 8K x 9 (CY7C4851) • Functionally equivalent to two CY7C4201/4211/4221/ 4231/4241/4251 FIFOs in a single package • 0.65 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10 ns read/write cycle times) • Offers optimal combination of large capacity, high speed, design flexibility, and small footprint • Fully asynchronous and simultaneous read and write operation • Four status flags per device: Empty, Full, and programmable Almost Empty/Almost Full • Low power — ICC1= 60mA • Output Enable (OEA/OEB) pins • Depth Expansion Capability • Width Expansion Capability • Space-saving 64-pin TQFP • Pin compatible and functionally equivalent to IDT72801, 72811, 72821, 72831, 72841,72851 These FIFOs have two independent sets of 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLKA,WCLKB) and two write-enable pins (WENA1, WENA2/LDA, WENB1, WENB2/LDB). When (WENA1,WENB1) is LOW and (WENA2/LDA, WENB2/LDB) is HIGH, data is written into the FIFO on the rising edge of the (WCLKA,WCLKB) signal. While (WENA1, WENA2/LDA, WENB1, WENB2/LDB) is held active, data is continually written into the FIFO on each WCLKA, WCLKB cycle. The output port is controlled in a similar manner by a free-running read clock (RCLKA, RCLKB) and two read-enable pins ((RENA1,RENB1), (RENA2,RENB2)). In addition, the CY7C48X1 has output enable pins (OEA, OEB) for each FIFO. The read (RCLKA, RCLKB) and write (WCLKA, WCLKB) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. The CY7C48X1 provides two sets of four different status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty+7 and Full–7. The flags are synchronous, i.e., they change state relative to either the read clock (RCLKA,RCLKB) or the write clock (WCLKA,WCLKB). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the (RCLKA,RCLKB). The flags denoting Almost Full, and Full states are updated exclusively by (WCLKA,WCLKB) The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle All configurations are fabricated using an advanced 0.65µ N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Functional Description The CY7C48X1 are Double high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 9 bits wide and operate as two separate FIFOs. The CY7C48X1 are pin-compatible to IDT728X1. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. Cypress Semiconductor Corporation Document #: 38-06005 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 26, 2002 CY7C4801/4811/4821 CY7C4831/4841/4851 Logic Block Diagram WCLKA WCLKB WENB1 WENB2/LDB WENA2/LDA INPUT REGISTER INPUT REGISTER WRITE CONTROL FLAG LOGIC DA 0-8 DB0-8 FLAG PROGRAM REGISTER LDA LDB WENA1 EFA PAEA PAFA FFA EFB PAEB PAFB FFB WRITE CONTROL WRITE POINTER A WRITE POINTER B RAM ARRAY A 256x9 . . 8k x 9 RAM ARRAY B 256 x 9 . 8k x 9 . READ POINTER A READ POINTER B READ CONTROL A READ CONTROL B RSA RSB RESET LOGIC THREE–STATE OUTPUT REGISTER THREE–STATE OUTPUT REGISTER OEA QA0-8 OEB QB0-8 RCLKA RENA1 RENA2 RCLKB RENB1 RENB2 48X1–1 Pin Configuration TQFP Top View QA0 FFA EFA OEA RENA2 RCLKA RENA1 GND QB8 QB7 QB6 QB5 QB4 QB3 QB2 QB1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 Vcc WENA2/LDA WCLKA WENA1 RSA DA8 DA7 DA6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851 QB0 FFB EFB OEB RENB2 RCLKB RENB1 GND Vcc PAEB PAFB DB0 DB1 DB2 DB3 DB4 Document #: 38-06005 Rev. *A DA5 DA4 DA3 DA2 DA1 DA0 PAFA PAEA WENB2/LDB WCLKB WENB1 RSB DB8 DB7 DB6 DB5 48X1–1 Page 2 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Selection Guide 7C48X1-10 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC1) (mA) Commercial Industrial 100 8 10 3 0.5 8 60 70 7C48X1-15 66.7 10 15 4 1 10 60 70 7C48X1-25 40 15 25 6 1 15 60 70 7C48X1-35 28.6 20 35 7 2 20 60 70 CY7C4801 Density Package Double 256 x 9 64-pin TQFP CY7C4811 Double 512 x 9 64-pin TQFP CY7C4821 Double 1K x 9 64-pin TQFP CY7C4831 Double 2K x 9 64-pin TQFP CY7C4841 Double 4K x 9 64-pin TQFP CY7C4851 Double 8K x 9 64-pin TQFP Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................... −55°C to +125°C Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V DC Input Voltage .................................................−0.5V to +7.0V Output Current into Outputs (LOW) .............................20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range[1] Range Commercial Industrial [2] Ambient Temperature 0°C to +70°C −40°C to +85°C VCC 5V ± 10% 5V ± 10% Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the “instant on” case temperature. Document #: 38-06005 Rev. *A Page 3 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Pin Definitions Signal Name DA0 − 8 DB0 − 8 QA0 − 8 QB0 − 8 WENA1 WENB1 Description Data Inputs Data Inputs Data Outputs Data Outputs Write Enable 1 I/O I I O O I Data Inputs for 9-bit bus Data Inputs for 9-bit bus Data Outputs for 9-bit bus Data Outputs for 9-bit bus WENA1 and WENB1become the only write enables when the device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when (WENA1,WENB1) is LOW and (FFA,FFB) is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when (WENA1,WENB1) is LOW and (WENA2/LDA,WENB2/LDB) and (FFA,FFB) are HIGH. If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. (WENA1,WENB1) must be LOW and (WENA2/LDA,WENB2/LDB) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the (FFA,FFB) is LOW. If the FIFO is configured to have programmable flags, (WENA2/LDA,WENB2/LDB) is held LOW to write or read the programmable flag offsets. Enables the device for Read operation. Description Write Enable 2 WENA2/LDA WENB2/LDB Dual Mode Pin Load I I RENA1 RENA2 RENB1 RENB2 WCLKA WCKLB Read Enable Inputs I Write Clock I The rising edge clocks data into the FIFO when (WENA1,WENB1) is LOW and (WENA2/LDA,WENB2/LDB) is HIGH and the FIFO is not Full. When (WENA2/LDA,WENB2/LDB) is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when (RENA1 ,RENB1) and (RENA2,RENB2) are LOW and the FIFO is not Empty. When (WENA2/LDA,WENB2/LDB) is LOW, (RCLKA,RCLKB) reads data out of the programmable flag-offset register. When (EFA,EFB) is LOW, the FIFO is empty. (EFA,EFB) is synchronized to (RCLKA,RCLKB). When (FFA,FFB) is LOW, the FIFO is full. (FFA,FFB) is synchronized to (WCLKA,WCLKB). When (PAEA,PAEB) is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAE is synchronized to RCLK. When (PAFA,PAFB) is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is synchronized to WCLK. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When (OEA,OEB) is LOW, the FIFO’s data outputs drive the bus to which they are connected. If (OEA,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. RCLKA RCLKB EFA,EFB FFA,FFB PAEA PAEB PAFA PAFB RSA RSB OEA OEB Read Clock I Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Reset Output Enable O O O O I I Document #: 38-06005 Rev. *A Page 4 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Electrical Characteristics Over the Operating Range[3] 7C48X1-10 Parameter VOH VOL VIH VIL IIX IOS[4] IOZL IOZH ICC1[5] Description Test Conditions Min. 2.4 0.4 2.0 −0.5 VCC = Max. VCC = Max., VOUT = GND OE > VIH, VSS < VO < VCC Com’l Ind −10 −90 −10 +10 60 70 VCC 0.8 +10 2.0 −0.5 −10 −90 −10 +10 60 70 Max. 7C48X1-15 Min. 2.4 0.4 VCC 0.8 +10 2.0 −0.5 −10 −90 −10 +10 60 70 Max. 7C48X1-25 Min. 2.4 0.4 VCC 0.8 +10 2.0 −0.5 −10 −90 −10 +10 60 70 Max. 7C48X1-35 Min. 2.4 0.4 VCC 0.8 +10 Max. Unit V V V V µA mA µA mA mA Output HIGH Voltage VCC = Min., IOH = −2.0 mA Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Short Circuit Current Output OFF, High Z Current Active Power Supply Current VCC = Min., IOL = 8.0 mA Capacitance[6] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF AC Test Loads and Waveforms[7, 8] R1 1.1K Ω 5V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT 420Ω OUTPUT R2 680Ω 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns 48X1–5 48X1–4 1.91V Notes: 3. See the last page of this specification for Group A subgroup testing information. 4. Test no more than one output at a time for not more than one second. 5. Outputs open. Tested at Frequency = 20 MHz. 6. Tested initially and after any design or process changes that may affect these parameters. 7. CL = 30 pF for all AC parameters except for tOHZ. 8. CL = 5 pF for tOHZ. Document #: 38-06005 Rev. *A Page 5 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Characteristics Over the Operating Range 7C48X1-10 Parameter fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tSKEW1 tSKEW2 Description Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-Up Time Data Hold Time Enable Set-Up Time Enable Hold Time Reset Pulse Width[9] 2 10 4.5 4.5 3.5 0.5 3.5 0.5 10 8 8 10 0 3 Z[10] 3 7 7 8 8 8 8 5 15 6 15 0 3 3 8 8 10 10 10 10 10 18 Min. Max. 100 8 2 15 6 6 4 1 4 1 15 10 10 15 0 3 3 12 12 15 15 15 15 12 20 7C48X1-15 Min. Max. 66.7 10 2 25 10 10 6 1 6 1 25 15 15 25 0 3 3 15 15 20 20 20 20 7C48X1-25 Min. Max. 40 15 2 35 14 14 7 2 7 2 35 20 20 35 7C48X1-35 Min. Max. 28.6 20 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Reset Set-Up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low Z[10] Output Enable to Output Valid Output Enable to Output in High Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag Clock to Programmable Almost-Full Flag Skew Time between Read Clock and Write Clock for Empty Flag and Full Flag Skew Time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full Flag Notes: 9. Pulse widths less than minimum values are not allowed. 10. Values guaranteed by design, not currently tested. Document #: 38-06005 Rev. *A Page 6 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Waveforms Write Cycle Timing tCLKH WCLKA (WCLKB) tDS DA0 −DA8 (DB0−DB8) tENS WENA1 (WENB1) WENA2(WENB2) (if applicable) FFA (FFB) tSKEW1 [11] RCLKA (RCLKB) RENA1,RENB2 (RENB1, RENB2) 48X1–6 tCLK tCLKL tDH tENH NO OPERATION NO OPERATION tWFF tWFF Read Cycle Timing tCLKH RCLKA (RCLKB) tENS RENA1,RENA2 (RENB1,RENB2) tREF EFA(EFB) tA QA0−QA8 (QB0−QB8) tENH tCLK tCLKL NO OPERATION tREF VALID DATA tOLZ tOE tOHZ OEA(OEB) tSKEW1 WCLKA,WCLKB WENA1(WENB1) [12] WENA2(WENB2) 48X1–7 Notes: 11. tSKEW1 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge to guarantee that (FFA,FFB) will go HIGH during the current clock cycle. If the time between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW1, then (FFA,FFB) may not change state until the next (WCLKA,WCLKB) rising edge. 12. tSKEW1 is the minimum time between a rising (WCLKA,WCLKB) edge and a rising (RCLKA,RCLKB) edge to guarantee that (EFA,EFB) will go HIGH during the current clock cycle. It the time between the rising edge of (WCLKA,WCLKB) and the rising edge of RCLK is less than tSKEW1, then (EFA,EFB) may not change state until the next (RCLKA,RCLKB) rising edge. Document #: 38-06005 Rev. *A Page 7 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Waveforms (continued) Reset Timing RSA(RSB) tRSS RENA1, RENA2 (RENB1,RENB2) tRSS WENA1 (WENB1) tRSR tRSR [13] tRS tRSS [15] tRSR WENA2/LDA (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFB, PAFB) tRSF tRSF tRSF QA0−QA8 (QB0−QB8) OEA(OEB)=1 [14] OEA(OEB)=0 48X1–8 Notes: 13. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be free-running during reset. 14. After reset, the outputs will be LOW if (OEA,OEB) = 0 and three-state if (OEA,OEB)=1. 15. Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06005 Rev. *A Page 8 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLKA,WCLKB tDS DA0−DA8 (DB0−DB8) tENS WENA1(WENB1) WENA2(WENB2) (if applicable) tSKEW1 RCLKA(RCLKB) tREF EFA(EFB) [17] D0 (FIRSTVALID WRITE) [16] D1 D2 D3 D4 tFRL tA RENA1, RENA2 (RENB1,RENB2) QA0 −QA8 (QB0−QB8) OEA(OEB) D0 tOLZ tOE tA D1 48X1–9 Notes: 16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW). 17. The first word is available the cycle after (EFA, EFB) goes HIGH, always. Document #: 38-06005 Rev. *A Page 9 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Waveforms (continued) Empty Flag Timing WCLKA,WCLKB tDS DA0−DA8 (DB0−DB8) WENA1(WENB1) tENS WENA2(WENB2) (if applicable) RCLKA(RCLKB) tSKEW1 EFA(EFB) RENA1, RENA2 (RENB1,RENB2) LOW OEA(OEB) tA QA0−QA8 (QB0−QB8) DATA IN OUTPUT REGISTER DATA READ 48X1–10 tDS DATA WRITE1 tENS tENH tENS tENH tENS [16] DATA WRITE2 tENH tENH [16] tFRL tFRL tREF tREF tSKEW1 tREF Document #: 38-06005 Rev. *A Page 10 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Waveforms (continued) Full Flag Timing WCLKA,WCLKB [11] NO WRITE NO WRITE NO WRITE tSKEW1 DA0−DA8 (DB0−DB8) FFA(FFB) tDS [11] tSKEW1 DATA WRITE DATA WRITE tWFF tWFF tWFF WENA1(WENB1) WENA2(WENB2) (if applicable) RCLKA(RCLKB) tENH RENA1, RENA2 (RENB1,RENB2) tENS tENS tENH OEA(OEB) LOW tA tA DATA READ NEXT DATA READ 48X1–11 QA0−QA8 (QB0−QB8) DATA IN OUTPUT REGISTER Document #: 38-06005 Rev. *A Page 11 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Waveforms (continued) Programmable Almost Empty Flag Timing tCLKH WCLKA,WCLKB tENS tENH WENA1(WENB1) tCLKL WENA2(WENB2) (if applicable) tENS tENH PAEA(PAEB) tSKEW2 RCLKA(RCLKB) tENS tENH RENA1, RENA2 (RENB1,RENB2) 48X1–12 Note 19 tPAE [18] N + 1 WORDS IN FIFO Note 20 tPAE Programmable Almost Full Flag Timing tCLKH WCLKA,WCLKB tENS tENH WENA1(WENB1) Note 22 tENS tENH PAFA(PAFB) FULL− M+1 WORDS IN FIFO tPAF FULL− M WORDS IN FIFO [23] tSKEW2 RCLKA(RCLKB) tENS RENA1, RENA2 (RENB1,RENB2) 48X1–13 tCLKL Note 21 WENA2(WENB2) (if applicable) [24] tPAF tENS tENH Notes: 18. tSKEW2 is the minimum time between a rising (WCLKA,WCLKB) and a rising (RCLKA,RCLKB) edge for (PAEA,PAEB) to change state during that clock cycle. If the time between the edge of (WCLKA,WCLKB) and the rising (RCLKA,RCLKB) is less than tSKEW2, then (PAEA,PAEB) may not change state until the next RCLK. 19. (PAEA,PAEB) offset = n. 20. If a read is preformed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when (PAEA,PAEB) goes LOW. 21. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW. 22. (PAFA,PAFB) offset = m. 23. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841, 8192-m words for CY7C4851. 24. tSKEW2 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge for (PAFA,PAFB) to change during that clock cycle. If the time between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW2, then (PAFA,PAFB) may not change state until the next (WCLKA,WCLKB). Document #: 38-06005 Rev. *A Page 12 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Switching Waveforms (continued) Write Programmable Registers tCLK tCLKH WCLKA,WCLKB tENS WENA2/LDA (WENB2/LDB) tENS WENA1(WENB1) tDS DA0−DA8 (DB0−DB8) tDH tENH tCLKL PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB PAF OFFSET MSB 48X1–14 Read Programmable Registers tCLK tCLKH RCLKA(RCLKB) tENS WENA2/LDA (WENB2/LDB) tENS RENA1, RENA2 (RENB1,RENB2) tA QA0−QA8 (QB0−QB8) UNKNOWN PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB 48X1–15 tCLKL tENH PAF OFFSET MSB Document #: 38-06005 Rev. *A Page 13 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Architecture The CY7C48X1 functions as two independent FIFOs in a single package, each with its own separate set of controls. The device consists of two arrays of 256 to 8K words of 9 bits each (implemented by a dual-port array of SRAM cells), two read pointers, two write pointers, control signals (RCLKA, RCLKB, WCLKA, WCLKB, RENA1, RENB1, RENA2, RENB2, WENA1, WENB1, WENA2, WENB2, RSA, RSB), and flags (EFA,EFB, PAEA,PAEB, PAFA,PAFB, FFA,FFB). transition of every write clock (WCLKA,WCLKB). Data is stored is the RAM array sequentially and independently of any on-going read operation. Write Enable 2/Load (WENA2/LDA, WENB2/LDB) - This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows for depth expansion. If Write Enable 2/Load (WENA2/LDA, WENB2/LDB) is set active HIGH at Reset (RSA,RSB=LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable 1 (WENA1,WENB1) is LOW and Write Enable 2/Load (WENA2/LDA, WENB2/LDB) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLKA,WCLKB). Data is stored in the RAM array sequentially and independently of any on-going read operation. Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RSA, RSB) cycle. This causes the FIFO to enter the Empty condition signified by (EFA,EFB) being LOW. All data outputs (QA0−8,QB0−8) go LOW tRSF after the rising edge of RSA, RSB. In order for the FIFO to reset to its default state, a falling edge must occur on (RSA,RSB) and the user must not read or write while (RSA,RSB) is LOW. All flags are guaranteed to be valid tRSF after (RSA,RSB) is taken LOW. Programming When (WENA2/LDA, WENB2/LDB) is held LOW during Reset, this pin is the load (LDA,LDB) enable for flag offset programming. In this configuration, (WENA2/LDA, WENB2/LDB) can be used to access the four 8-bit offset registers contained in the CY7C48X1 for writing or reading data to these registers. When the device is configured for programmable flags and both (WENA2/LDA, WENB2/LDB) and (WENA1,WENB1) are LOW, the first LOW-to-HIGH transition of (WCLKA,WCLKB) writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of (WCLKA,WCLKB) store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, WENB2/LDB) and respectively, when (WENA2/LDA, (WENA1,WENB1) are LOW. The fifth LOW-to-HIGH transition of (WCLKA,WCLKB) while (WENA2/LDA, WENB2/LDB) and (WENA1,WENB1) are LOW writes data to the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types. It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the (WENA2/LDA, WENB2/LDB) input HIGH, the FIFO is returned to normal read and write operation. The next time (WENA2/LDA, WENB2/LDB) is brought LOW, a write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when (WENA2/LDA, WENB2/LDB) is LOW and both (RENA1,RENB1) and (RENA2,RENB2) are LOW. LOW-to-HIGH transitions of (RCLKA,RCLKB) read register contents to the data outputs. Writes and reads should not be preformed simultaneously on the offset registers. FIFO Operation When the (WENA1,WENB1) signal is active LOW and (WENA2,WENB2) is active HIGH, data present on the (DA0−8,DB0−8) pins is written into the FIFO on each rising edge (WCLKA,WCLKB) of the (WCLKA,WCLKB) signal. Similarly, when the (RENA1,RENB1) and (RENA2,RENB2) signals are active LOW, data in the FIFO memory will be presented on the (QA0−8,QB0−8) outputs. New data will be presented on each rising edge of (RCLKA,RCLKB) while (RENA1,RENB1) and (RENA2,RENB2) are active. (RENA1,RENB1) and (RENA2,RENB2) must set up tENS before (RCLKA,RCLKB) for it to be a valid read function. (WENA1,WENB1) and (WENA2,WENB2) must occur tENS before (WCLKA,WCLKB) for it to be a valid write function. An output enable (OEA,OEB) pin is provided to three-state the (QA0−8,QB0−8) outputs when (OEA,OEB) is asserted. When (OEA,OEB) is enabled (LOW), data in the output register will be available to the (QA0−8,QB0−8) outputs after tOE. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its (QA0−8,QB0−8) outputs even after additional reads occur. Write Enable 1 (WENA1,WENB1) - If the FIFO is configured for programmable flags, Write Enable 1 (WENA1,WENB1) is the only write enable control pin. In this configuration, when Write Enable 1 (WENA1,WENB1) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH Document #: 38-06005 Rev. *A Page 14 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 256 x 9 x 2 8 7 Empty Offset (LSB) Reg. Default Value = 007h 512 x 9 x 2 0 8 7 Empty Offset (LSB) Reg. Default Value = 007h 1K x 9 x 2 0 8 7 Empty Offset (LSB) Reg. Default Value = 007h 0 8 0 8 1 (MSB) 0 0 8 1 (MSB) 00 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 8 0 8 1 (MSB) 0 0 8 1 (MSB) 00 0 2K x 9 x 2 8 7 Empty Offset (LSB) Reg. Default Value = 007h 4K x 9 x 2 0 8 7 Empty Offset (LSB) Reg. Default Value = 007h 8K x 9 x 2 0 8 7 Empty Offset (LSB) Reg. Default Value = 007h 0 8 2 (MSB) 000 0 8 3 (MSB) 0000 0 8 4 (MSB) 00000 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 8 7 Full Offset (LSB) Reg Default Value = 007h 0 8 2 (MSB) 000 0 8 3 (MSB) 0000 0 8 4 (MSB) 00000 0 Figure 1. Offset Register Location and Default Values. Programmable Flag (PAEA,PAEB, PAFA,PAFB) Operation Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable almost-empty flag (PAEA,PAEB) and programmable almost-full flag (PAFA,PAFB) states are determined by their corresponding offset registers and the difference between the read and write pointers. Table 1. Writing the Offset Registers. LD 0 WEN 0 WCLK[25] Selection Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) No Operation Write Into FIFO No Operation The number formed by the empty offset least significant bit register and empty offset most significant register is referred to as n and determines the operation of (PAEA,PAEB). (PAEA,PAEB) is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. (PAEA,PAEB) is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n+1) or greater unread words. The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of (PAFA,PAFB). (PAEA,PAEB) is synchronized to the LOW-to-HIGH transition of (WCLKA,WCLKB) by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4801 (256–m), CY7C4811 (512–m), CY7C4821 (1K–m), CY7C4831 (2K–m), CY7C4841 (4K–m), and CY7C4851 (8K–m). (PAFA,PAFB) is set HIGH by the LOW-to-HIGH transition of (WCLKA,WCLKB) when the number of available memory locations is greater than m. 0 1 1 1 0 1 Notes: 25. The same selection sequence applies to reading form the registers. REN1 and REN2 are enabled and a read is performed on the LOW- to-HIGH transition of RCLK. Document #: 38-06005 Rev. *A Page 15 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Flag Operation The CY7C48X1 devices provide four flag pins to indicate the condition of the FIFO contents. Empty, Full, (PAEA,PAEB), and (PAFA,PAFB) are synchronous. Full Flag The Full Flag (FFA,FFB) will go LOW when the device is full. Write operations are inhibited whenever (FFA,FFB) is LOW regardless of the state of (WENA1,WENB1) and (WENA2/LDA,WENB2/LDB). Table 2. Status Flags. Number of Words in FIFO CY7C4801 0 1 to n[26] 0 1 to n[26] CY7C4811 0 1 to n[26] (n+1) to (1024 −(m+1)) (1024−m)[27] to 1023 1024 CY7C4821 FF H H H H L PAF H H H L L PAE L L H H H EF L H H H H (FFA,FFB) is synchronized to (WCLKA,WCLKB), i.e., it is exclusively updated by each rising edge of (WCLKA,WCLKB). Empty Flag The Empty Flag (EFA,EFB) will go LOW when the device is empty. Read operations are inhibited whenever (EFA,EFB) is LOW, regardless of the state of (RENA1,RENB1) and (RENA2,RENB2. (EFA,EFB) is synchronized to (RCLKA,RCLKB), i.e., it is exclusively Full Flag. (n+1) to (256-(m+1)) (256−m)[27] to 255 256 (n+1) to (512-(m+1)) (512−m)[27] to 511 512 Number of Words in FIFO CY7C4831 0 1 to n [26] CY7C4841 0 1 to n [26] CY7C4851 0 1 to n [26] FF H H H H L PAF H H H L L PAE L L H H H EF L H H H H (n+1) to (2048 −(m+1)) (n+1) to (4096 −(m+1)) (2048−m)[27] to 2047 2048 (4096−m)[27] to 4095 4096 (n+1) to (8192 −(m+1)) (8192−m)[27] to 8191 8192 Notes: 26. n =Empty Offset (n=7 default value). 27. m = Full Offset (m=7 default value). Document #: 38-06005 Rev. *A Page 16 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Single Device Configuration When FIFO A(B) is in a Single Device Configuration, the Read Enable 2 RENA2(RENB2) control input can be grounded (see Figure 2). in this configuration, the Write Enable2/Load (WENA2/LDA,WENB2/LDB) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. RESET (RSA,RSB) DATA IN DA0−DA8(DB0−DB8) WRITE CLOCK (WCLKA,WCLKB) CY7C4801 DATA OUT QA0−QA8(QB0−QB8) READ CLOCK (RCLKA,RCLKB) CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851 WRITE ENABLE 1 (WENA1,WENB1) WRITE ENABLE2/LOAD(WENA2/LDA,WENB/LDB) PROGRAMMABLE (PAFA,PAFB) FULL FLAG (FFA,FFB) READ ENABLE 1 (RENA1,RENB1) OUTPUT ENABLE (OEA,OEB) PROGRAMMABLE(PAEA,PAEA) EMPTY FLAG(EFA,EFB) Read Enable 2 (RENA2,RENB2) 48X1–16 Figure 2. Block Diagram of 256 x 9,512 x 9,1024 x 9,2048 x 9,4096 x 9,8192 x 9 Double Sync FIFO Used in a Single Device Configuration. Document #: 38-06005 Rev. *A Page 17 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Width Expansion Configuration Word width may be increased simply by connecting the corresponding input control signals of FIFOs A and B. A composite flag should be created for each of the end-point status flags EFA and EFB, also FFA and FFB. The partial status flags PAEA, PAFB, PAFA, PAFB can be detected from any one device. Figure 3 demonstrates an 18-bit word width using the two FIFOs contained in one CY7C4801/4811/4821/4831/4841 /4851. Any word width can be attained by adding additional CY7C4801/4811/4821/4831/4841/4851s. When the CY7C4801/4811/4821/4831/4841/4851 is in a Width Expansion Configuration, the Read Enable 2 (RENA2 and RENB2) control unputs can be grounded (see Figure 3). In this configuration, the Write Enable 2/Load (WENA2/LDA,WENB2/LDB) pins are set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. 9 RESET RESET (RSA) D0−D17 18 9 9 RAM ARRAY A 256 x 9 512 x 9 1024 x 9 2048 x 9 4096 x 9 8192 x 9 RCLKA WCLKB RENA1 WENB1 OEA WENB2/LDB RAM ARRAY B 256 x 9 512 x 9 1024 x 9 2048 x 9 4096 x 9 8192 x 9 RESET(RSB) READCLOCK READ ENABLE OUTPUT ENABLE WRITECLOCK WRITE ENABLE WRITE ENABLE 2/LOAD WCLKA WENA WEN2/LD RCLKB RENB1 OEB EFA EFB EMPTY FLAG FFA FULL FLAG FFB EF FF 9 9 Q0−Q17 18 Read Enable 2 (RENA2) Read Enable 2 (RENB2) 48X1–17 Figure 3. Block Diagram of two FIFOs contained in one CY7C4801/4811/4821/4831/4841/4851 configured for an 18-bit width-expansion. Document #: 38-06005 Rev. *A Page 18 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Bidirectional Configuration The two FIFOs of the CY7C4801/4811/4821/4831/4841/4851 can be used to buffer data flow in two directions. In the example that follows, processor A can write data to processor B via FIFO A, and, in turn, processor B can write processor A via FIFO B. VCC RAM ARRAY A RENA2 WENA2 RCLKA WCLKA WENA1 OEA PROCESSOR A 9 Control Logic CLOCK ADDRESS CONTROL DATA 9 RAM 9 9 RENA1 DA0−DA8 QA −QA 0 8 CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851 RAM ARRAY B WENB1 RCLKB RENB1 WCLKB OEB DB0−DB8 QB0−QB8 WENB2 RENB2 VCC 48X1–18 PROCESSOR A CLOCK ADDRESS CONTROL DATA Control Logic 9 9-BIT BUS 9 RAM 9 9 Figure 4. Block Diagram of Bidirectional Configuration. Depth Expansion CY7C4801/4811/4821/4831/4841/4851can be adapted to applications that require greater than 256/512/1024/2048/4096/ 8192 words. The existence of dual enable pins on the read and write ports allow depth expansion. The Write Enable 2/Load (WENA2, WENB2) pins are used as a second write enables in a depth expansion configuration, thus the Programmable flags are set to the default values. Depth expansion is possible by using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of data. a typical application would have the expansion logic alternate data access from one device to the next in a sequential manner. The CY7C4801/4811/4821/4831/4841/ 4851 operates in the Depth Expansion configuration when the following conditions are met: 1. WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so that these pins operate as second Write Enables. 2. External logic is used to control the flow of data. Document #: 38-06005 Rev. *A 9-BIT BUS Page 19 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Ordering Information Double 256x9 FIFO Speed (ns) 10 15 25 35 Ordering Code CY7C4801-10AC CY7C4801-10AI CY7C4801-15AC CY7C4801-15AI CY7C4801-25AC CY7C4801-25AI CY7C4801-35AC CY7C4801-35AI Package Name A65 A65 A65 A65 A65 A65 A65 A65 Package Type 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Double 512x9 FIFO Speed (ns) 10 15 25 35 Ordering Code CY7C4811-10AC CY7C4811-10AI CY7C4811-15AC CY7C4811-15AI CY7C4811-25AC CY7C4811-25AI CY7C4811-35AC CY7C4811-35AI Package Name A65 A65 A65 A65 A65 A65 A65 A65 Package Type 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Double 1Kx9 FIFO Speed (ns) 10 15 25 35 Ordering Code CY7C4821-10AC CY7C4821-10AI CY7C4821-15AC CY7C4821-15AI CY7C4821-25AC CY7C4821-25AI CY7C4821-35AC CY7C4821-35AI Package Name A65 A65 A65 A65 A65 A65 A65 A65 Package Type 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Document #: 38-06005 Rev. *A Page 20 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Ordering Information (continued) Double 2Kx9 FIFO Speed (ns) 10 15 25 35 Ordering Code CY7C4831-10AC CY7C4831-10AI CY7C4831-15AC CY7C4831-15AI CY7C4831-25AC CY7C4831-25AI CY7C4831-35AC CY7C4831-35AI Package Name A65 A65 A65 A65 A65 A65 A65 A65 Package Type 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Double 4Kx9 FIFO Speed (ns) 10 15 25 35 Ordering Code CY7C4841-10AC CY7C4841-10AI CY7C4841-15AC CY7C4841-15AI CY7C4841-25AC CY7C4841-25AI CY7C4841-35AC CY7C4841-35AI Double 8Kx9 FIFO Speed (ns) 10 15 25 35 Ordering Code CY7C4851-10AC CY7C4851-10AI CY7C4851-15AC CY7C4851-15AI CY7C4851-25AC CY7C4851-25AI CY7C4851-35AC CY7C4851-35AI Package Name A65 A65 A65 A65 A65 A65 A65 A65 Package Type 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Package Name A65 A65 A65 A65 A65 A65 A65 A65 Package Type 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack 64-Lead Thin Quad Flatpack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Document #: 38-06005 Rev. *A Page 21 of 23 CY7C4801/4811/4821 CY7C4831/4841/4851 Package Diagram 64-Lead Thin Plastic Quad Flat Pack A65 Document #: 38-06005 Rev. *A Page 22 of 23 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4801/4811/4821 CY7C4831/4841/4851 Document Title: CY7C4801/4811/4821/CY7C4831.4841/4851 256/512/1K/2K/4K/8K x9 x2 Double Sync (TM) Fifos Document Number: 38-06005 REV. ** *A ECN NO. 106466 122258 Issue Date 07/11/01 12/26/02 Orig. of Change SZV RBI Description of Change Change from Spec Number: 38-00538 to 38-06005 Power up requirements added to Operating Conditions Information Document #: 38-06005 Rev. *A Page 23 of 23