CY7C60223-QXC

CY7C601xx CY7C602xx enCoRe™ II Low Voltage Microcontroller Features • enCoRe™ II Low Voltage (enCoRe II LV)—“enhanced Component Reduction” — Internal crystalless oscillator with support for optional external clock or external crystal or resonator. — Configurable IO for real-world interface without external components • Enhanced 8-bit microcontroller — Harvard architecture — M8C CPU speed can be up to 12 MHz or sourced by an external crystal, resonator, or clock signal • Internal memory — 256 bytes of RAM — 8 Kbytes of Flash including EEROM emulation • Low power consumption — Typically 2.25 mA at 3 MHz — 5 µA sleep • In-system reprogrammability — Allows easy firmware update • General-purpose I/O ports — Up to 36 General Purpose I/O (GPIO) pins — High current drive on GPIO pins. Configurable 8- or 50mA/pin current sink on designated pins — Each GPIO port supports high-impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs, and CMOS output — Maskable interrupts on all I/O pins • SPI serial communication — Master or slave operation — Configurable up to 2-Mbit/second transfers. — Supports half duplex single data line mode for optical sensors • 2-channel 8-bit or 1-channel 16-bit capture timer registers. Capture timer registers store both rising and falling edge times — Two registers each for two input pins — Separate registers for rising and falling edge capture — Simplifies interface to RF inputs for wireless applications • Internal low-power wake-up timer during suspend mode • • • • — Periodic wake-up with no external components Programmable Interval Timer interrupts Reduced RF emissions at 27 MHz and 96 MHz Watchdog timer (WDT) Low voltage detection with user-selectable threshold voltages Improved output drivers to reduce EMI Operating voltage from 2.7V to 3.6VDC Operating temperature from 0–70°C Available in 24/40-pin PDIP, 24-pin SOIC, 24-pin QSOP/SSOP, 28-pin SSOP and 48-pin SSOP. • Advanced development tools based on Cypress PSoC® tools • Industry-standard programmer support • • • • Applications The CY7C601xx/CY7C602xx is targeted for the following applications: • PC Wireless HID devices — Mice (optomechanical, optical, trackball) — Keyboards — Presenter tools • Gaming — Joysticks — Gamepad • General purpose wireless applications — Remote controls — Barcode scanners — POS terminal — Consumer electronics — Toys Introduction The enCoRe II LV family brings the features and benefits of the enCoRe II to non-USB applications. The enCoRe II family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Other external components, such as wake-up circuitry, are also integrated into this chip. The enCoRe II LV is a low-voltage, low-cost 8-bit Flashprogrammable microcontroller The enCoRe II LV features up to 36 general-purpose I/O (GPIO) pins. The I/O pins are grouped into five ports (Port 0 to 4). The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2, 3, and 4 may only be configured as a group. Each GPIO port supports highimpedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50 mA sink current. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has in addition to the port interrupt vector, three dedicated pins that have independent interrupt vectors (P0.2–P0.4). Cypress Semiconductor Corporation Document 38-16016 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 23, 2006 [+] [+] Feedback CY7C601xx CY7C602xx The enCoRe II LV features an internal oscillator. Optionally, an external 1 MHz to 24 MHz crystal can be used to provide a higher precision reference. The enCoRe II LV also supports external clock The enCoRe II LV has 8 Kbytes of Flash for user’s code and 256 bytes of RAM for stack space and user variables. In addition, enCoRe II LV includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free-Running Timer with Capture registers and a 12-bit Programmable Interval Timer. The Power-on reset circuit detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage it generates a reset or may be configured to generate an interrupt. There is a Lowvoltage detect circuit that detects when VCC drops below a programmable trip voltage and it may be configurable to generate a LVD interrupt to inform the processor about the low-voltage event. POR and LVD share the same interrupt; there is no separate interrupt for each. The Watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. The microcontroller supports 17 maskable interrupts in the vectored interrupt controller. All interrupts can be masked. Interrupt sources include LVR/POR, a programmable interval timer, a nominal 1.024-ms programmable output from the Free Running Timer, two capture timers, five GPIO Ports, three GPIO pins, two SPI, a 16-bit free-running timer wrap and an internal wakeup timer interrupt. The wakeup timer causes periodic interrupts when enabled. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edgesensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling. The free-running timer generates an interrupt at 1024-µs rate. It can also generate an interrupt when the free-running counter overflow occurs—every 16.384 ms. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. The two 8bit capture timer registers save a programmable 8-bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.5, P0.6). The two 8-bit capture registers can be ganged into a single 16-bit capture register. The enCoRe II LV supports in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface. Conventions In this document, bit positions in the registers are shaded to indicate which members of the enCoRe II LV family implement the bits. Available in all enCoRe II LV family members CY7C601xx only Logic Block Diagram Figure 1. CY7C601xx/CY7C602xx Block Diagram Interrupt Control 4 SPI/GPIO Pins 16 Extended I/O Pins 16 GPIO Pins Wakeup Timer Internal 12 MHz Oscillator Clock Control Crystal Oscillator CY7C601xx only M8C CPU RAM 256 Byte Flash 8K Byte Capture Timers 12-bit Timer POR / Low-Voltage Detect Vdd Watchdog Timer Document 38-16016 Rev. *C Page 2 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Packages/Pinouts Figure 2. Package Configurations Top View CY7C60223 24-pin PDIP P3.0 P3.1 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 NC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.3/SSEL P1.2 VDD P1.1 P1.0 VSS P2.0 P2.1 P0.0/CLKIN P0.1/CLKOUT P0.2/INT0 P0.3/INT1 CY7C60223 24-pin SOIC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT\P0.1 CLKIN\P0.0 P2.1 P2.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60223 24-pin QSOP NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT\P0.1 CLKIN\P0.0 P2.1 P2.0 NC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2 VDD P1.1 P1.0 VSS CY7C60113 28-pin SSOP VDD P2.7 P2.6 P2.5 P2.4 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS P3.7 P3.6 P3.5 P3.4 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60123 40-pin PDIP VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 T1O1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS P4.3 P4.2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 CY7C60123 48-pin SSOP NC NC NC NC VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 TIO1/P0.6 TIO0/PO.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC VSS P4.3 P4.2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VDD P1.1 P1.0 Document 38-16016 Rev. *C Page 3 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Pin Assignments Table 1. Pin Assignments 48 40 28 24 24 SSOP PDIP SSOP QSOP SOIC 7 6 42 43 34 35 36 37 38 39 40 41 15 14 13 12 11 10 9 8 25 26 28 29 30 31 32 33 23 3 2 38 39 30 31 32 33 34 35 36 37 11 10 9 8 7 6 5 4 21 22 24 25 26 27 28 29 19 5 4 3 2 15 16 18 19 20 21 22 23 13 14 15 17 18 21 22 23 24 9 13 14 16 17 20 21 22 23 9 20 21 23 24 3 4 5 6 16 24 25 26 27 11 10 11 10 18 17 19 20 18 19 1 2 24 PDIP Name P4.0 P4.1 P4.2 P4.3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P1.0 P1.1 P1.2 P1.3/SSEL P1.4/SCLK P1.5/SMOSI P1.6/SMISO P1.7 P0.0/CLKIN GPIO Port 1 bit 0 GPIO Port 1 bit 1 GPIO Port 1 bit 2 GPIO Port 1 bit 3—Configured individually. Alternate function is SSEL signal of the SPI bus GPIO Port 1 bit 4—Configured individually. Alternate function is SCLK signal of the SPI bus GPIO Port 1 bit 5—Configured individually. Alternate function is SMOSI signal of the SPI bus GPIO Port 1 bit 6—Configured individually. Alternate function is SMISO signal of the SPI bus GPIO Port 1 bit 7—Configured individually. TTL voltage threshold GPIO Port 0 bit 0—Configured individually. On CY7C601xx, optional Clock In when external oscillator is disabled or external oscillator input when external oscillator is enabled. On CY7C602xx, oscillator input when configured as Clock In If this pin is used as a General Purpose output it will draw current. This pin should be configured as an input to reduce current draw. GPIO Port 2—configured as a group (byte) GPIO Port 3—configured as a group (byte) Description GPIO Port 4—configured as a group (nibble) Document 38-16016 Rev. *C Page 4 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Table 1. Pin Assignments (continued) 48 40 28 24 24 SSOP PDIP SSOP QSOP SOIC 22 18 12 8 8 24 PDIP 15 Name Description P0.1/CLKOUT GPIO Port 0 bit 1—Configured individually On CY7C601xx, optional clock out when external oscillator is disabled or external oscillator output drive when external oscillator is enabled. On CY7C602xx, oscillator output when configured as Clock Out. If this pin is used as a General Purpose output it will draw current. This pin should be configured as an input to reduce current draw. P0.2/INT0 P0.3/INT1 P0.4/INT2 P0.5/TIO0 P0.6/TIO1 P0.7 NC NC VDD GPIO port 0 bit 2—Configured individually Optional rising edge interrupt INT0 GPIO port 0 bit 3—Configured individually Optional rising edge interrupt INT1 GPIO port 0 bit 4—Configured individually Optional rising edge interrupt INT2 GPIO port 0 bit 5—Configured individually Alternate function Timer capture inputs or Timer output TIO0 GPIO port 0 bit 6—Configured individually Alternate function Timer capture inputs or Timer output TIO1 GPIO port 0 bit 7—Configured individually No connect No connect Power Ground 21 20 19 18 17 16 1,2,3, 4 45,46, 47,48 5 27 44 24 17 16 15 14 13 12 11 10 9 8 7 6 7 6 5 4 3 2 1 12 7 6 5 4 3 2 1 24 14 13 12 11 10 9 7 8 1 23 40 20 17 1 14 28 16 – 13 15 – 12 22 – 19 VSS Document 38-16016 Rev. *C Page 5 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Register Summary enCoRe II LV Register Summary Addr 00 01 02 03 04 05 06 07–09 0A–0B 0C 0D 0E 0F 10 11–13 14 15 16 17 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 30 31 32 34 Name P0DATA P1DATA P2DATA P3DATA P4DATA P00CR P01CR P02CR– P04CR P05CR– P06CR P07CR P10CR P11CR P12CR P13CR P14CR– P16CR P17CR P2CR P3CR P4CR FRTMRL FRTMRH TCAP0R TCAP1R TCAP0F TCAP1F PITMRL PITMRH PIRL PIRH TMRCR TCAPINTE TCAPINTS CPUCLKCR TMRCLKCR CLKIOCR IOSCTR 7 P0.7 P1.7 6 P0.6/TIO1 5 P0.5/TIO0 4 P0.4/INT2 P1.4/SCLK 3 P0.3/INT1 P1.3/SSEL 2 P0.2/INT0 P1.2 1 P0.1/ CLKOUT P1.1 0 P0.0/CLKIN P1.0 R/W bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ----bbbb Default 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10001111 00000000 000ddddd P1.6/SMISO P1.5/SMOSI P2.7–P2.2 P3.7–P3.2 Reserved Reserved CLK Output Int Enable Int Enable Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Reserved TTL Threshold Reserved Reserved Reserved TTL Thresh TTL Thresh TTL Thresh Reserved High Sink High Sink High Sink High Sink High Sink Reserved TTL Thresh TTL Thresh TTL Thresh TTL Thresh TTL Thresh High Sink High Sink Reserved Reserved Reserved P4.3–P4.0 Open Drain Open Drain Open Drain Open Drain Open Drain P2.1–P2.0 P3.1–P3.0 Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable -bbbbbbb bbbbbbbb --bb-bbb bbbb-bbb -bbb-bbb -bb----b -bb--b-b bbbb-bbb -bb-bbbb bbb-bbbb -bb-bbbb -bbbbbbb -bbbbbbb -bbb-bbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr Reserved TIO Output Reserved Reserved Reserved CLK Output Reserved SPI Use Reserved Reserved Reserved Reserved Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Reserved Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Reserved Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Free Running Timer [7:0] Free Running Timer [15:8] Capture 0 Rising [7:0] Capture 1 Rising [7:0] Capture 0 Falling [7:0] Capture 1 Falling [7:0] Prog Interval Timer [7:0] Reserved Prog Interval [7:0] Reserved First Edge Hold 8-bit capture Prescale Reserved Reserved Reserved TCAPCLK Divider Reserved foffset[2:0] TCAPCLK Select XOSC Select ITMRCLK Divider XOSC Enable EFTB Disabled Gain[4:0] Cap0 16bit Enable Cap1 Fall Active Cap1 Fall Active Cap1 Rise Active Cap1 Rise Active Prog Interval [11:8] Reserved Cap0 Fall Active Cap0 Fall Active Cap0 Rise Active Cap0 Rise Active CPU CLK Select ITMRCLK Select CLKOUT Select Prog Interval Timer [11:8] ----rrrr bbbbbbbb ----bbbb bbbbb------bbbb ----bbbb -------b bbbbbbbb ---bbbbb bbbbbbbb Document 38-16016 Rev. *C Page 6 of 62 [+] [+] Feedback CY7C601xx CY7C602xx enCoRe II LV Register Summary (continued) Addr 35 36 3C 3D DA DB DC Name XOSCTR LPOSCTR SPIDATA SPICR 7 32-kHz Low Power 6 Reserved Reserved 5 4 3 XOSC XGM [2:0] 2 1 Reserved 0 Mode R/W ---bbb-b b-bbbbbb bbbbbbbb Default 000ddddd d-dddddd 00000000 00000000 00000000 00000000 00000000 32-kHz Bias Trim [1:0] SPIData[7:0] 32-kHz Freq Trim [3:0] Swap LSB First Comm Mode INT1 GPIO Port 0 CPOL SPI Receive CPHA SPI Transmit Reserved SCLK Select INT0 POR/LVD bbbbbbbb bbbbbbbb bbb----- INT_CLR0 GPIO Port 1 Sleep Timer INT_CLR1 INT_CLR2 TCAP0 Reserved Prog Interval 1-ms Timer Timer GPIO Port 4 GPIO Port 3 GPIO Port 2 Reserved INT2 16-bit Counter Wrap TCAP1 -bbb-bbb DE DF INT_MSK3 INT_MSK2 ENSWINT Reserved GPIO Port 4 GPIO Port 3 GPIO Port 2 Int Enable Int Enable Int Enable Reserved Reserved INT2 Int Enable 16-bit Counter Wrap Int Enable TCAP1 Int Enable r-------bbb-bbb 00000000 00000000 E1 INT_MSK1 TCAP0 Prog Interval 1-ms Timer Int Enable Timer Int Enable Int Enable INT1 Int Enable GPIO Port 0 Int Enable SPI Receive Int Enable Reserved bbb----- 00000000 E0 E2 E3 -----F7 FF 1E0 1E3 1EB 1E4 INT_MSK0 GPIO Port 1 Sleep Timer Int Enable Int Enable INT_VC RESWDT CPU_A CPU_X CPU_PCL CPU_PCH CPU_SP CPU_F CPU_SCR OSC_CR0 LVDCR ECO_TR VLTCMP GIES Reserved Reserved SPI Transmit Int Enable INT0 Int Enable POR/LVD Int Enable bbbbbbbb bbbbbbbb wwwwwww w ------------------------------------ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010 00010100 00000000 00000000 00000000 00000000 Pending Interrupt [7:0] Reset Watchdog Timer [7:0] Temporary Register T1 [7:0] X[7:0] Program Counter [7:0] Program Counter [15:8] Stack Pointer [7:0] XIO WDRS No Buzz PORS Super Sleep Carry Reserved Zero Reserved CPU Speed [2:0] VM[2:0] Global IE Stop ---brbbb r-ccb--b --bbbbbb --bb-bbb bb------ Reserved Reserved Sleep Duty Cycle [1:0] Sleep Timer [1:0] Reserved Reserved Reserved PORLEV[1:0] LVD PPOR ------rr Note: In the R/W column, b = Both Read and Write r = Read Only w = Write Only c = Read/Clear d = calibration value. Should not change during normal use Table 2. CPU Registers and Register Name Register Flags Program Counter Accumulator Stack Pointer Index Register Name CPU_F CPU_PC CPU_A CPU_SP CPU_X CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. The 16-bit Program Counter Register (CPU_PC) allows for direct addressing of the full eight Kbytes of program memory space. The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. Document 38-16016 Rev. *C Page 7 of 62 [+] [+] Feedback CY7C601xx CY7C602xx The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It can also be affected by the SWAP and ADD instructions. The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and Table 3. CPU Flags Register (CPU_F) [R/W] Bit # Field Read/Write Default – 0 7 6 Reserved – 0 – 0 5 4 XIO R/W 0 shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (i.e., AND, OR, XOR). See Table 19. CPU Registers Flags Register The Flags Register can only be set or reset with logical instruction. 3 Super R 0 2 Carry RW 0 1 Zero RW 1 0 Global IE RW 0 Bit [7:5]: Reserved Bit 4: XIO Set by the user to select between the register banks. 0 = Bank 0 1 = Bank 1 Bit 3: Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.) 0 = User Code 1 = Supervisor Code Bit 2: Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation. 0 = No Carry 1 = Carry Bit 1: Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation. 0 = Not Equal to Zero 1 = Equal to Zero Bit 0: Global IE Determines whether all interrupts are enabled or disabled. 0 = Disabled 1 = Enabled Note: This register is readable with explicit address 0xF7. The OR F, expr and AND F, expr must be used to set and clear the CPU_F bits. Accumulator Register Table 4. CPU Accumulator Register (CPU_A) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 3 2 1 0 CPU Accumulator [7:0] – 0 – 0 – 0 – 0 – 0 Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode. Document 38-16016 Rev. *C Page 8 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Index Register Table 5. CPU X Register (CPU_X) Bit # Field Read/Write Default – 0 – 0 – 0 – 0 7 6 5 4 X [7:0] – 0 – 0 – 0 – 0 3 2 1 0 Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. Stack Pointer Register Table 6. CPU Stack Pointer Register (CPU_SP) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 3 2 1 0 Stack Pointer [7:0] – 0 – 0 – 0 – 0 – 0 Bit [7:0]: Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack. CPU Program Counter High Register Table 7. CPU Program Counter High Register (CPU_PCH) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 3 2 1 0 Program Counter [15:8] – 0 – 0 – 0 – 0 – 0 Bit [7:0]: Program Counter [15:8] 8-bit data value holds the higher byte of the program counter. CPU Program Counter Low Register Table 8. CPU Program Counter Low Register (CPU_PCL) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 3 2 1 0 Program Counter [7:0] – 0 – 0 – 0 – 0 – 0 Bit [7:0]: Program Counter [7:0] 8-bit data value holds the lower byte of the program counter. Addressing Modes Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources; the second source is the A, X, SP, or F register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 9. Source Immediate Opcode Instruction Operand 1 Immediate Value Document 38-16016 Rev. *C Page 9 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Examples ADD A, 7 ;In this case, the immediate value of 7 is added with the Accumulator and the result is placed in the Accumulator. ;In this case, the immediate value of 8 is moved to the X register. ;In this case, the immediate value of 9 is logically ANDed with the F register and the result is placed in the F register. Examples ADD A, [X+7] ;In this case, the value in the memory location at address X + 7 is added with the Accumulator, and the result is placed in the Accumulator. ;In this case, the value in the register space at address X + 8 is moved to the X register. MOV AND X, F, 8 9 MOV X, REG[X+8] Destination Direct Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 10.Source Direct Opcode Instruction Examples ADD A, [7] ;In this case, the value in the RAM memory location at address 7 is added with the Accumulator, and the result is placed in the Accumulator. ;In this case, the value in the register space at address 8 is moved to the X register. The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 12.Destination Direct Opcode Instruction Operand 1 Destination Address Operand 1 Source Address Examples ADD [7], A ;In this case, the value in the memory location at address 7 is added with the Accumulator, and the result is placed in the memory location at address 7. The Accumulator is unchanged. ;In this case, the Accumulator is moved to the register space location at address 8. The Accumulator is unchanged. MOV REG[8], A MOV X, REG[8] Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes. Table 11.Source Indexed Opcode Instruction Operand 1 Source Index Destination Indexed The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Table 13.Destination Indexed Opcode Instruction Example ADD [X+7], A ;In this case, the value in the memory location at address X+7 is added with the Accumulator and the result is placed in the memory location at address X+7. The Accumulator is unchanged. Operand 1 Destination Index Document 38-16016 Rev. *C Page 10 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 14.Destination Direct Source Immediate Opcode Instruction Examples ADD [7], 5 ;In this case, value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. ;In this case, the immediate value of 6 is moved into the register space location at address 8. Table 16.Destination Direct Source Direct Opcode Instruction Example MOV [7], [8] ;In this case, the value in the memory location at address 8 is moved to the memory location at address 7. Operand 1 Destination Address Operand 2 Source Address Operand 1 Destination Address Operand 2 Immediate Value Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Table 17.Source Indirect Post Increment Opcode Operand 1 Source Address Address Instruction Example MVI A, [8] ;In this case, the value in the memory location at address 8 is an indirect address. The memory location pointed to by the Indirect address is moved into the Accumulator. The indirect address is then incremented. MOV REG[8], 6 Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 15.Destination Indexed Source Immediate Opcode Instruction Examples ADD [X+7], 5 ;In this case, the value in the memory location at address X+7 is added with the immediate value of 5, and the result is placed in the memory location at address X+7. ;In this case, the immediate value of 6 is moved into the location in the register space at address X+8. Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 18.Destination Indirect Post Increment Opcode Instruction Example MVI [8], A ;In this case, the value in the memory location at address 8 is an indirect;address. The Accumulator is moved into the memory location pointed to by the indirect address. The indirect address is then incremented. Operand 1 Destination Index Operand 2 Immediate Value MOV REG[X+8], 6 Operand 1 Destination Address Address Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Document 38-16016 Rev. *C Page 11 of 62 [+] [+] Feedback CY7C601xx CY7C602xx Instruction Set Summary The instruction set is summarized in Table 19 numerically and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com web site). Table 19.Instruction Set Summary Sorted Numerically by Opcode Order[1, 2] Opcode Hex Opcode Hex Opcode Hex Cycles Cycles Cycles Bytes Bytes Instruction Format Flags Instruction Format Flags Bytes Instruction Format Flags 00 15 01 02 03 04 05 06 4 6 7 7 8 9 1 SSC 2 ADD A, expr 2 ADD A, [expr] 2 ADD A, [X+expr] 2 ADD [expr], A 2 ADD [X+expr], A 3 ADD [expr], expr 3 ADD [X+expr], expr 1 PUSH A 2 ADC A, expr 2 ADC A, [expr] 2 ADC A, [X+expr] 2 ADC [expr], A 2 ADC [X+expr], A 3 ADC [expr], expr 3 ADC [X+expr], expr 1 PUSH X 2 SUB A, expr 2 SUB A, [expr] 2 SUB A, [X+expr] 2 SUB [expr], A 2 SUB [X+expr], A 3 SUB [expr], expr 3 SUB [X+expr], expr 1 POP A 2 SBB A, expr C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z 2D 2E 8 9 2 OR [X+expr], A 3 OR [expr], expr 3 OR [X+expr], expr 1 HALT 2 XOR A, expr 2 XOR A, [expr] 2 XOR A, [X+expr] 2 XOR [expr], A 2 XOR [X+expr], A 3 XOR [expr], expr 3 XOR [X+expr], expr 2 ADD SP, expr 2 CMP A, expr 2 CMP A, [expr] 2 CMP A, [X+expr] 3 CMP [expr], expr 3 CMP [X+expr], expr 2 MVI A, [ [expr]++ ] 2 MVI [ [expr]++ ], A 1 NOP 3 AND reg[expr], expr 3 AND reg[X+expr], expr 3 OR reg[expr], expr 3 OR reg[X+expr], expr 3 XOR reg[expr], expr 3 XOR reg[X+expr], expr Z Z Z 5A 5B 5C 5D 5 4 4 6 7 2 MOV [expr], X 1 MOV A, X 1 MOV X, A 2 MOV A, reg[expr] 2 MOV A, reg[X+expr] 3 MOV [expr], [expr] 2 MOV reg[expr], A 2 MOV reg[X+expr], A 3 MOV reg[expr], expr 3 MOV reg[X+expr], expr 1 ASL A 2 ASL [expr] 2 ASL [X+expr] 1 ASR A 2 ASR [expr] 2 ASR [X+expr] 1 RLC A 2 RLC [expr] 2 RLC [X+expr] 1 RRC A 2 RRC [expr] 2 RRC [X+expr] 2 AND F, expr 2 OR F, expr 2 XOR F, expr 1 CPL A C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z Z Z Z 2F 10 30 31 32 33 34 35 36 9 4 6 7 7 8 9 Z Z Z Z Z Z Z 5E 5F 10 60 61 62 63 64 65 66 67 5 6 8 9 4 7 8 4 7 8 4 7 8 4 7 8 4 4 4 4 07 10 08 09 0A 0B 0C 0D 0E 4 4 6 7 7 8 9 37 10 38 39 3A 3B 3C 3D 5 5 7 8 8 9 if (A=B) Z=1 if (A