CY7C603XX_1107

CY7C603xx enCoRe™ III Low Voltage enCoRe™ III Low Voltage Features ■ Applications ■ ■ ■ ■ ■ ■ Powerful Harvard-architecture processor ❐ M8C processor speeds to 12 MHz ❐ Low power at high speed ❐ 2.4 V to 3.6 V operating voltage ❐ Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) ❐ Commercial temperature range: 0 °C to +70 °C Configurable peripherals ❐ 8-bit timers, counters, and PWM ❐ Full duplex master or slave SPI ❐ 10-bit ADC ❐ 8-bit successive approximation ADC ❐ Comparator Flexible on-chip memory ❐ 8K flash program storage 50,000 erase/write cycles ❐ 512 bytes SRAM data storage ❐ In-System serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash Complete development tools ® ❐ Free development software (PSoC Designer™) ❐ Full-featured, In-circuit emulator and programmer ❐ Complex breakpoint structure ❐ 128K trace memory Precision, programmable clocking ❐ Internal ±2.5% 24 and 48 MHz oscillator ❐ Internal oscillator for watchdog and sleep Programmable pin configurations ❐ 10 mA drive on all general purpose I/O (GPIO) ❐ Pull-up, pull-down, high-Z, strong, or open drain drive modes on all GPIO ❐ Up to 8 analog inputs on GPIO ❐ Configurable interrupt on all GPIO Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of IO combinations Additional system resources 2 ❐ I C master, slave, and Multimaster to 400 kHz ❐ Watchdog and sleep timers ❐ User-configurable low-voltage detection ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference Wireless mice Wireless gamepads Wireless presenter tools Wireless keypads PlayStation® 2 wired gamepads PlayStation 2 bridges for wireless gamepads ❐ Applications requiring a cost effective low voltage 8-bit microcontroller. ■ Logic Block Diagram Port 3 Port 2 Port 1 Port 0 ■ System Bus ■ Global Digital Interconnect SRAM 512 Bytes Interrupt Controller SROM Global Analog Interconnect Flash 8K Sleep and Watchdog CPU Core (M8C) ■ Clock Sources (Includes IMO and ILO) enCoRe III LV Core DIGITAL SYSTEM Digital PSoC Block Array ANALOG SYSTEM Analog PSoC Block Array Analog Ref. ■ ■ ■ Digital Clocks POR and LVD I2C System Resets Switch Mode Pump Internal Voltage Ref. Analog Mux SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 38-16018 Rev. *N • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 7, 2011 CY7C603xx Contents enCoRe III Low Voltage Functional Overview ................ 3 enCoRe III LV Core ..................................................... 3 The Digital System ...................................................... 3 The Analog System ..................................................... 3 Additional System Resources ..................................... 4 enCoRe III LV Device Characteristics ............................. 4 Getting Started .................................................................. 4 Development Kits ........................................................ 4 Development Tools .......................................................... 5 PSoC Designer Software Subsystems ........................ 5 In-Circuit Emulator ....................................................... 5 Designing with PSoC Designer ....................................... 6 Select Components ..................................................... 6 Configure Components ............................................... 6 Organize and Connect ................................................ 6 Generate, Verify, and Debug ....................................... 6 Pin Information ................................................................. 7 28-pin Part Pinout ........................................................ 7 32-pin Part Pinout ........................................................ 8 Register Reference ......................................................... 11 Register Conventions ................................................ 11 Register Mapping Tables .......................................... 11 Electrical Specifications ................................................ 15 Absolute Maximum Ratings ....................................... 16 Operating Temperature ............................................. 16 DC Electrical Characteristics ..................................... 17 AC Electrical Characteristics ..................................... 22 Packaging Information ................................................... 28 Packaging Dimensions .............................................. 28 Thermal Impedances ................................................ 30 Solder Reflow Peak Temperature ............................. 30 Ordering Information ...................................................... 31 Ordering Code Definitions ......................................... 31 Acronyms ........................................................................ 32 Acronyms Used ......................................................... 32 Reference Documents .................................................... 32 Document Conventions ................................................. 33 Units of Measure ....................................................... 33 Numeric Conventions ................................................ 33 Glossary .......................................................................... 33 Document History Page ................................................. 38 Sales, Solutions, and Legal Information ...................... 39 Worldwide Sales and Design Support ....................... 39 Products .................................................................... 39 PSoC® Solutions ...................................................... 39 Document Number: 38-16018 Rev. *N Page 2 of 39 CY7C603xx enCoRe III Low Voltage Functional Overview The enCoRe III low voltage (enCoRe III LV) CY7C603xx device is based on the flexible PSoC® architecture. This supports a simple set of peripherals that can be configured to match the needs of each application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. A fast CPU, flash program memory, SRAM data memory, and configurable IO are included in both 28-pin SSOP and 32-pin QFN packages. Figure 1. Digital System Block Diagram Port 3 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital enCoRe III LV Block Array Row 0 DBB00 DBB01 DCB02 Row Input Configuration The enCoRe III LV architecture, as shown in Figure 1, consists of four main areas: the enCoRe III LV Core, the system resources, digital system, and analog system. Configurable global bus resources allow combining all the device resources into a complete custom system. Each enCoRe III LV device supports a limited set of digital and analog peripherals. Depending on the package, up to 28 general purpose I/Os (GPIOs) are also included. The GPIOs provide access to the global digital and analog interconnects. 4 DCB03 4 Row Output Configuration 8 8 8 8 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] enCoRe III LV Core The enCoRe III LV core is a powerful engine that supports a rich feature set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low-speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a four MIPS 8-bit Harvard -architecture microprocessor. The core includes a CPU, memory, clocks, and configurable GPIO. System resources provide additional capability, such as digital clocks to increase flexibility, I2C functionality for implementing an I2C master, slave, multi-master, an internal voltage reference that provides an absolute value of 1.3 V to a number of subsystems, a switch mode pump (SMP) that generates normal operating voltages off a single battery cell, and various system resets supported by the M8C. The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. The Analog System The analog system consists of two configurable blocks. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the common analog functions for this device (available as user modules) are: ■ ■ ■ ■ Analog-to-digital converters (single with 8-bit resolution) Pin-to-pin comparators Single-ended comparators with absolute (1.3-V) reference 1.3-V reference (as a system resource) The Digital System The digital system consists of 4 digital enCoRe III LV blocks. Each block is an 8-bit resource. Digital peripheral configurations include the following: ■ ■ ■ ■ ■ ■ PWM usable as timer or counter SPI master and slave I2C slave and multi-master CMP ADC10 SARADC Analog blocks are provided in columns of two, which includes one continuous time (CT) (CT - ACE00 or ACE01) and one switched capacitor (SC) (SC - ASE10 or ASE11) blocks. Document Number: 38-16018 Rev. *N Page 3 of 39 CY7C603xx Figure 2. Analog System Block Diagram enCoRe III LV Device Characteristics The enCoRe III LV devices have four digital blocks and four analog blocks. Table 1 lists the resources available for specific enCoRe III LV devices. Table 1. enCoRe III LV Device Characteristics Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size 512 Bytes Part Number Flash Size 8K Array Input Configuration ACI0[1:0] AllIO X X X X ACI1[1:0] CY7C60323PVXC 24 1 4 24 0 2 4 Getting Started ACOL1MUX Analog Mux Bus X Array ACE00 ACE01 ASE10 ASE11 The quickest path to understanding the enCoRe III LV silicon is by reading this data sheet and using the PSoC Designer integrated development environment (IDE). This data sheet is an overview of the enCoRe III LV and presents specific pin, register, and electrical specifications. enCoRe III LV is based on the architecture of the CY8C21x34. For in-depth information, along with detailed programming information, refer to the PSoC Programmable System-on-Chip Technical Reference Manual, which is available at http://www.cypress.com. For up-to-date ordering, packaging, and electrical specification information, refer to the latest device data sheets on the web at http://www.cypress.com. The Analog Multiplexer System The analog mux bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters (ADC). An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Additional System Resources System resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow. ■ Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks may be generated using digital blocks as clock dividers. The I2C module provides 100 kHz and 400 kHz communication over two wires. slave, master, and multi-master modes are all supported. Low voltage detection interrupts can signal the application of falling voltage levels, while the advanced power-on reset (POR) circuit eliminates the need for a system supervisor. An internal 1.3-V voltage reference provides an absolute reference for the analog system. An integrated switch mode pump generates normal operating voltages from a single 1.2 V battery cell, providing a low-cost boost converter. Versatile analog multiplexer system. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. ■ ■ Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. ■ ■ Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. ■ Document Number: 38-16018 Rev. *N Page 4 of 39 CY7C603xx Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 38-16018 Rev. *N Page 5 of 39 CY7C603xx Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 38-16018 Rev. *N Page 6 of 39 CY7C603xx Pin Information The enCoRe III LV device is available in 28-pin SSOP and 32-pin QFN packages. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, VDD, SMP, and XRES are not capable of Digital IO. 28-pin Part Pinout Figure 3. CY7C60323-PVXC 28-pin Device A , I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] Vss M, I2C SCL, P1[7] M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M XRES P1[6], M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M Table 2. Pin Definitions - CY7C60323-PVXC 28-pin Device Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Digital Analog IO I, M IO I, M IO I, M IO I, M IO M IO M IO I, M IO I, M Power IO M IO M IO M IO M Power IO M IO M IO M IO M Input IO I, M IO I, M IO M IO M IO I, M IO I, M IO I, M IO I, M Power Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output, integrating input. Analog column mux input, integrating input. Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. I2C serial clock (SCL). I2C serial data (SDA). I2C SCL, ISSP-SCLK. Ground connection. I2C SDA, ISSP-SDATA. Optional external clock input (EXTCLK). Active HIGH external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage. LEGEND A = analog, I = input, O = output, and M = analog mux input. Document Number: 38-16018 Rev. *N Page 7 of 39 CY7C603xx 32-pin Part Pinout Figure 4. CY7C60323-LFXC 32-pin Device A, I, M A, I, M A, I, M A, I, M P0[4], A, I, M P0[2], A, I, M 26 25 A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 Vss P0[3], P0[5], P0[7], Vdd P0[6], QFN (Top View) M, I2C SDA, P1[5] M, P1[3] Figure 5. CY7C60333-LFXC 32-pin Device Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M 26 25 15 M, EXTCLK, M, P1[4] P1[6] 16 32 31 A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, I2C SCL, P1[7] 30 29 28 27 M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES 1 2 3 4 5 6 7 8 QFN (Top View) M, I2C SCL, P1[1] Vss 9 10 11 12 Document Number: 38-16018 Rev. *N M, I2C SDA, P1[5] M, P1[3] M, I2C SDA, P1[0] M, P1[2] 13 14 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES Page 8 of 39 CY7C603xx Figure 6. CY7C60323-LTXC 32-pin Device Sawn Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, 12C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 QFN Figure 7. CY7C60333-LTXC 32-pin Device Sawn Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, 12C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 M, 12C SDA, P1[5] M, P1[3] M, 12C SCL, P1[1] Vss M, 12C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES QFN Document Number: 38-16018 Rev. *N M, 12C SDA, P1[5] M, P1[3] M, 12C SCL, P1[1] Vss M, 12C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES Page 9 of 39 CY7C603xx Table 3. 32-pin Part Pinout (QFN[1]) Pin No. 1 2 3 4 5 6 6 7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Input M M M M M M I, M I, M I, M I, M Power I, M I, M I, M Power IO IO IO IO Power M M M M IO Power M M M M Type Digital IO IO IO IO IO IO Power M Analog I, M M M M M M Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] SMP P3[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description Analog column mux input, integrating input. In CY7C60323 part. Switch mode pump (SMP) connection to required external components in CY7C60333 part. In CY7C60323 Part. Ground connection in CY7C60333 part. I2C serial clock (SCL). I2C serial data (SDA). I2C SCL, ISSP-SCLK. Ground connection. I2C SDA, ISSP-SDATA. Optional external clock input (EXTCLK). Active HIGH external reset with internal pull-down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input Analog column mux input, integrating input. Ground connection. P0[7] P0[5] P0[3] Vss LEGEND A = analog, I = input, O = output, and M = analog mux input. Note 1. The QFN package has a center pad that must be connected to ground (Vss). Document Number: 38-16018 Rev. *N Page 10 of 39 CY7C603xx Register Reference This section lists the registers of the enCoRe III LV device. For detailed register information, refer the PSoC System-on-Chip Technical Reference Manual. Register Mapping Tables The enCoRe III LV device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set to 1 the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Register Conventions The register conventions specific to this section are listed in Table 4. Table 4. Register Conventions Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Table 5. Register Map 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 Addr (0,Hex) Access 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C ASE11CR0 Access Name ASE10CR0 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C # Access is bit specific. IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 CUR_PP STK_PP RW Access RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC RW RW RW RW # RW # RW RW RW RW Access Blank fields are Reserved and must not be accessed. Document Number: 38-16018 Rev. *N Page 11 of 39 CY7C603xx Table 5. Register Map 0 Table: User Space (continued) Name Addr (0,Hex) Access 1D 1E 1F DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 # W RW # # W RW # # W RW # # W RW # TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ADC0_CR ADC1_CR CMP_CR1 CMP_CR0 AMX_IN AMUXCFG PWM_CR Name Addr (0,Hex) 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 # # RW # RW RW RW Access Name Addr (0,Hex) 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. DAC_D CPU_SCR1 CPU_SCR0 RW RW RW RW RW RW RW CPU_F DEC_CR0 DEC_CR1 INT_MSK0 INT_MSK1 INT_VC RES_WDT Access Name INT_CLR3 INT_MSK3 Addr (0,Hex) DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RL RW RW RW RW RC W Access RW RW Blank fields are Reserved and must not be accessed. Document Number: 38-16018 Rev. *N Page 12 of 39 CY7C603xx Table 6. Register Map 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 Addr (1,Hex) Access 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU 20 21 22 23 24 25 26 27 28 29 2A 2B RW RW RW CLK_CR3 RW RW RW AMD_CR1 ALT_CR0 RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B RW RW RW RW RW RW RW RW ASE11CR0 Access Name ASE10CR0 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB # Access is bit specific. IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RW Access RW Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB W W RW W RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW Access Blank fields are Reserved and must not be accessed. Document Number: 38-16018 Rev. *N Page 13 of 39 CY7C603xx Table 6. Register Map 1 Table: Configuration Space (continued) Name DCB03FN DCB03IN DCB03OU Addr (1,Hex) Access 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 RW RW RW Name TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Addr (1,Hex) 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW Access RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Name Addr (1,Hex) AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. DAC_CR CPU_SCR1 CPU_SCR0 FLS_PR1 RW RW RW RW RW RW RW CPU_F Access Name Addr (1,Hex) EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL Access Blank fields are Reserved and must not be accessed. Document Number: 38-16018 Rev. *N Page 14 of 39 CY7C603xx Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe III LV device. For up-to-date electrical specifications, check the latest data sheet by visiting the web at http://www.cypress.com. Specifications are valid for 0 °C  TA  70 °C and TJ  85 °C as specified, except where noted. Refer to Table 19 on page 22 for the electrical specifications for the internal main oscillator (IMO) using SLIMO mode. Figure 10. Voltage versus CPU Frequency 3.60 V Vdd Voltage Vdd Voltage 3.60 V Figure 11. IMO Frequency Trim Options SLIMO Mode=1 SLIMO Mode=0 3.00 V 2.70 V 2.40 V 93 kHz Valid Operating Region 3.00 V SLIMO SLIMO Mode=1 Mode=1 2.40 V 3 MHz 12 MHz 93 kHz 6 MHz 12 MHz 24 MHz CPU Frequency IMO Frequency The allowable CPU operating region for 12 MHz has been extended down to 2.7 V from the original 3.0 V design target. The customer’s application is responsible for monitoring voltage and throttling back CPU speed in accordance with Figure 10 when voltage approaches 2.7 V. Refer to Table 16 for LVD specifications. Note that the device does not support a preset trip at 2.7 V. To detect VDD drop at 2.7 V, an external circuit or device such as the WirelessUSB LP - CYRF6936 must be employed; or if the design permits, the nearest LVD trip value at 2.9 V can be used. Document Number: 38-16018 Rev. *N Page 15 of 39 CY7C603xx Absolute Maximum Ratings Table 7. Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min –40 Typ – 125 Max +90 See package label 72 Unit °C °C Notes Higher storage temperatures reduce data retention time. TBAKETEMP Bake temperature TBAKETIME Bake time See package label 0 –0.5 Vss – 0.5 Vss – 0.5 –25 2000 – – – – – – – – Hours TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to Vss DC input voltage DC voltage applied to tri-state Maximum current into any port pin Electro static discharge voltage Latch up current +70 5 VDD + 0.5 VDD + 0.5 +25 – 200 °C V V V mA V mA Human body model ESD. Operating Temperature Table 8. Operating Temperature Parameter TA TJ Description Ambient temperature Junction temperature Min 0 0 Typ – – Max +70 +85 Unit °C °C The temperature rise from ambient to junction is package specific. See Table 31 on page 30. The user must limit the power consumption to comply with this requirement. Notes Document Number: 38-16018 Rev. *N Page 16 of 39 CY7C603xx DC Electrical Characteristics DC Chip-Level Specifications Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and 0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 9. DC Chip-Level Specifications Parameter VDD IDD3 Supply voltage Supply current, IMO = 6 MHz using SLIMO mode. Description Min 2.40 – Typ – 1.2 Max 3.6 2 Unit V mA Notes See Table 16 on page 20. Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. Conditions are VDD = 2.55 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. VDD = 2.55 V, 0 °C 3.0 V Notes Document Number: 38-16018 Rev. *N Page 17 of 39 CY7C603xx Table 11. 2.7V DC GPIO Specifications Parameter RPU RPD VOH Pull-up resistor Pull-down resistor High output level Description Min 4 4 VDD – 0.4 – Typ 5.6 5.6 – Max 8 8 – Unit k k V IOH = 2.5 mA (6.25 Typ), VDD = 2.4 to 3.0 V (16 mA maximum, 50 mA Typ combined IOH budget). IOL = 10 mA, VDD = 2.4 to 3.0 V (90 mA maximum combined IOL budget). Notes VOL Low output level – 0.75 V IOH IOL VIL VIH VH IIL CIN COUT High level source current Low level sink current Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output 2.5 10 – 2.0 – – – – – – – – 90 1 3.5 3.5 – – 0.75 – – – 10 10 mA mA V V mV nA pF pF Gross tested to 1 A. Package and pin dependent. Temp = 25 °C. Package and pin dependent. Temp = 25 °C. VDD = 2.4 to 3.0. VDD = 2.4 to 3.0. DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and 0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 12. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA IEBOA IEBOA00 CINOA VCMOA GOLOA ISOA Description Input offset voltage (absolute value) Input leakage current (Port 0 analog pins) Input leakage current (Port 0, Pin 0 analog pin) Input capacitance (Port 0 analog pins) Common mode voltage range Open loop gain Amplifier supply current Min – – – – – 0 – – Typ 2.5 10 200 50 4.5 – 80 10 Max 15 – – – 9.5 VDD – 1 – 30 Units mV µV/C pA nA pF V dB µA Gross tested to 1 µA Gross tested to 1 µA Package and pin dependent. Temp = 25 C Notes TCVOSOA Average input offset voltage drift Table 13. 2.7-V DC Operational Amplifier Specifications Symbol VOSOA IEBOA IEBOA00 CINOA VCMOA GOLOA ISOA Description Input offset voltage (absolute value) Input leakage current (Port 0 analog pins) Input leakage current (Port 0, Pin 0 analog pin) Input capacitance (Port 0 analog pins) Common mode voltage range Open loop gain Amplifier supply current Min – – – – – 0 – – Typ 2.5 10 200 50 4.5 – 80 10 Max 15 – – – 9.5 VDD – 1 – 30 Units mV µV/C pA nA pF V dB µA Gross tested to 1 µA Gross tested to 1 µA Package and pin dependent. Temp = 25 C Notes TCVOSOA Average input offset voltage drift Document Number: 38-16018 Rev. *N Page 18 of 39 CY7C603xx DC Switch Mode Pump Specifications Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and 0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 14. DC Switch Mode Pump (SMP) Specifications Parameter VPUMP3V Description 3.3 V output voltage from pump Min 3.00 Typ 3.25 Max 3.60 Unit V Notes Configurated as in Note 2. Average, neglecting ripple. SMP trip voltage is set to 3.25 V. Configurated as in Note 2. Average, neglecting ripple. SMP trip voltage is set to 2.55 V. Configurated as in Note 2. SMP trip voltage is set to 3.25 V. SMP trip voltage is set to 2.55 V. Configurated as in Note 2. SMP trip voltage is set to 3.25 V. Configurated as in Note 2. SMP trip voltage is set to 2.55 V. Configurated as in Note 2. 0 °C < TA < 100 °C. 1.25 V at TA = –40 °C. Configurated as in Note 2. VO is the VDD value for PUMP trip specified by the VM[2:0] setting in the DC POR and LVD specification, Table 16 on page 20. Configurated as in Note 2. VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD specification, Table 16 on page 20. VPUMP2V 2.6 V output voltage from pump 2.45 2.55 2.80 V IPUMP Available output current VBAT = 1.5 V, VPUMP = 3.25 V VBAT = 1.3 V, VPUMP = 2.55 V Input voltage range from battery Input voltage range from battery Minimum input voltage from battery to start pump Line regulation (over Vi range) 8 8 1.0 1.0 1.2 – – – – – – – 3.3 2.8 – mA mA V V V VBAT3V VBAT2V VBATSTART VPUMP_Line – 5 – %VO VPUMP_Load Load regulation – 5 – %VO VPUMP_Ripple Output vovltage ripple (depends on cap/load) E3 Efficiency – 35 100 50 – – mVpp Configurated as in Note 2. Load is 5 mA. % Configurated as in Note 2. Load is 5 mA. SMP trip voltage is set to 3.25 V. For I load = 1 mA, VPUMP = 2.55 V, VBAT = 1.3 V, 10 H inductor, 1 F capacitor, and Schottky diode. E2 Efficiency 35 80 – % FPUMP DCPUMP Switching frequency Switching duty cycle – – 1.3 50 – – MHz % Note 2. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 12 on page 20. Document Number: 38-16018 Rev. *N Page 19 of 39 CY7C603xx Figure 12. Basic Switch Mode Pump Circuit D 1 Vdd VPUMP L1 VBAT enCoRe III LV SMP C 1 + Battery Vss DC Analog Mux Bus Specifications Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and 0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70° C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 15. DC Analog Mux Bus Specifications Parameter RSW RVDD Description Switch resistance to common analog bus Resistance of initialization switch to VDD Min – – Typ – – Max 400 800 800 Unit    Notes VDD > 2.7 V 2.4 V 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 38-16018 Rev. *N Page 27 of 39 CY7C603xx Figure 14. Definition of Timing for Fast-/Standard-Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL TSPI2C THDDATI2CTSUSTAI2C TBUFI2C THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition TSUSTOI2C P STOP Condition S Packaging Information This section illustrates the packaging specifications for the CY7C603xx device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com. Packaging Dimensions Figure 15. 28-pin (210-Mil) SSOP 51-85079 *E Document Number: 38-16018 Rev. *N Page 28 of 39 CY7C603xx Figure 16. 32-pin QFN (5 × 5 mm) (SAWN) 001-30999 *C Document Number: 38-16018 Rev. *N Page 29 of 39 CY7C603xx Thermal Impedances Table 31. Thermal Impedances per Package Package 28-pin SSOP 32-pin QFN [21] Typical JA [19] 62 °C / W 19 °C / W Typical JC 28 °C / W 32 °C / W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 32. Solder Reflow Peak Temperature Package 28-pin SSOP 32-pin QFN Maximum Peak Temperature 260 °C 260 °C Time at Maximum Peak Temperature 30 s 30 s Notes 19. TJ = TA + Power x JA 20. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. 21. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Document Number: 38-16018 Rev. *N Page 30 of 39 CY7C603xx Ordering Information The following table lists the CY7C603xx device’s key package features and ordering codes Table 33. CY7C603xx Device Key Features and Ordering Information Package Type 28-SSOP 28-SSOP Tape and Reel 32-QFN SAWN 32-QFN SAWN Tape and Reel Ordering Part Number CY7C60323-PVXC CY7C60323-PVXCT CY7C60323-LTXC CY7C60323-LTXCT Flash Size 8K 8K 8K 8K RAM Size 512 512 512 512 SMP No No No No I/O 24 24 28 28 Ordering Code Definitions CY 7 C 60 xxx Part Number: 1xx, 2xx = enCoRe II LV; 3xx = enCoRe III LV; 4xx = enCoRe IV LV Family name: Low Voltage RF Companion MCU Technology: CMOS Cypress Products Company ID : CY = Cypress Document Number: 38-16018 Rev. *N Page 31 of 39 CY7C603xx Acronyms Acronyms Used Table 34 lists the acronyms that are used in this document. Table 34. Acronyms Used in this Datasheet Acronym AC ADC API CPU CT DAC DC DTMF ECO EEPROM GPIO ICE IDE ILO IMO I/O ISSP LCD LPC LVD MAC Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current dual-tone multi-frequency external crystal oscillator electrically erasable programmable read-only memory general purpose I/O in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output in-system serial programming liquid crystal display low power comparator low voltage detect multiply-accumulate Acronym MIPS PCB PGA PLL POR PPOR PSoC® PWM QFN RTC SAR SC SLIMO SMP SPITM SRAM SROM SSOP USB WDT XRES Description million instructions per second printed circuit board programmable gain amplifier phase-locked loop power-on reset precision power on reset Programmable System-on-Chip pulse-width modulator quad flat no leads real time clock successive approximation switched capacitor slow IMO switch mode pump serial peripheral interface static random access memory supervisory read only memory shrink small-outline package universal serial bus watchdog timer external reset Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Number: 38-16018 Rev. *N Page 32 of 39 CY7C603xx Document Conventions Units of Measure Table 35 lists the units of measures. Table 35. Units of Measure Symbol kB dB °C µF fF pF kHz MHz rt-Hz k  Unit of Measure 1024 bytes decibels degree Celsius microfarads femtofarads picofarads kilohertz megahertz root hertz kilohms ohm microamperes milliamperes nanoamperes pikoamperes Symbol µH µs ms ns ps µV mV mVpp nV V µW W mm ppm % microhenry Unit of Measure microseconds milliseconds nanoseconds picoseconds microvolts millivolts millivolts peak-to-peak nanovolts volts microwatts watts millimeter parts per million percent µA mA nA pA Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are switched capacitor (SC) and continuous time (CT) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. analog blocks analog-to-digital (ADC) Application Programming Interface (API) asynchronous bandgap reference bandwidth Document Number: 38-16018 Rev. *N Page 33 of 39 CY7C603xx Glossary bias (continued) 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. block buffer bus clock comparator compiler configuration space crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation. debugger dead band digital blocks digital-to-analog (DAC) Document Number: 38-16018 Rev. *N Page 34 of 39 CY7C603xx Glossary duty cycle emulator (continued) The relationship of a clock period high time to its low time, expressed as a percent. Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). external reset (XRES) flash Flash block frequency gain I2C ICE input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. interrupt service routine (ISR) jitter low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. master device Document Number: 38-16018 Rev. *N Page 35 of 39 CY7C603xx Glossary (continued) An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. microcontroller mixed-signal modulator noise oscillator parity phase-locked loop (PLL) pinouts port power-on reset (POR) PSoC® PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse-width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. The time it takes for an output signal or value to stabilize after the input has changed from one value to another. register reset ROM serial settling time Document Number: 38-16018 Rev. *N Page 36 of 39 CY7C603xx Glossary shift register slave device (continued) A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. SRAM SROM stop bit synchronous tri-state UART user modules user space VDD VSS watchdog timer Document Number: 38-16018 Rev. *N Page 37 of 39 CY7C603xx Document History Page Description Title: CY7C603xx, enCoRe™ III Low Voltage Document Number: 38-16018 Rev. ** *A ECN No. 339394 399556 Orig. of Change BON BHA Submission Date See ECN See ECN New Advance Data Sheet. Changed from Advance Information to Preliminary. Changed data sheet format. Removed CY7C604xx. Modified Figure 10 to include 2.7 V Vdd at 12 MHz operation. Corrected part numbers in section 4 to match with part numbers in Ordering Information. From CY7C60323-28PVXC, CY7C60323-56LFXC and CY7C60333-56LFXC to CY7C60323-PVXC, CY7C60323-LFXC and CY7C60333-LFXC respectively. Changed from Preliminary to Final data sheet. Change title from Wireless enCoRe II to enCoRe III Low Voltage. Applied new template formatting. Added 32-Pin Sawn QFN Pin Diagram, package diagram, and ordering information. Added Packaging Handling information. Deleted note regarding link to amkor.com for MLF package dimensions. Added Table of Contents. Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification. Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications. Updated copyright and Sales, Solutions, and Legal Information URLs. Updated 28-Pin SSOP and 32-Pin QFN (PUNCH and SAWN) package diagrams. Updated Cypress website links. Updated Development Kits. Updated 3.3 V AC Chip-Level Specifications and 2.7 V AC Chip-Level Specifications. Removed AC Analog Mux Bus Specs section. Updated 32-pin Sawn QFN package diagram. Removed inactive parts from Ordering Information. Updated revision in the footer. Updated Logic Block Diagram to enCore III LV. Added Ordering Code Definitions Added Acronyms and Units of Measure table. Datasheet updated as per latest Template. Updated 3.3-V and 2.7-V AC Digital Block Specifications. Updated DC Operational Amplifier Specifications. Updated I2C Timing Diagram. Added DC I2C Specifications. Added UILO max limit. Added Tjit_IMO specification, removed existing jitter specifications. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. Updated Packaging Information. Updated in new template. Removed prune parts CY7C60333-LTXC and CY7C60333-LTXCT from the datasheet. Updated Getting Started, Development Tools, and Designing with PSoC Designer. Updated Thermal Impedances and Solder Reflow Peak Temperature table. Description of Change *B *C 461240 470485 TYJ TYJ See ECN See ECN *D *E *F *G 513713 2197567 2620679 2852393 KKVTMP UVS/AESA CMCC/PYR S XUT See ECN See ECN 12/12/2008 01/15/2010 *H 2892683 NJF 03/15/2010 *I *J 2911952 3014656 GNKK BHA 04/13/2010 09/15/2010 *K 3114976 NJF 12/19/10 *L *M *N 3180466 3210223 3285017 CSAI CSAI DIVA 02/23/2011 03/30/2011 07/07/2011 Document Number: 38-16018 Rev. *N Page 38 of 39 CY7C603xx Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC® Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-16018 Rev. *N Revised July 7, 2011 Page 39 of 39 All products and company names mentioned in this document may be the trademarks of their respective holders.