CY7C63743

CY7C637xx Errata Revision: ** March 30, 2004 Errata Document for CY7C637xx / enCoRe™ USB Combination Low-speed USB & PS/2 Peripheral Controller This document describes the errata for the enCoRe™ USB Combination Low-speed USB & PS/2 Periheral Controller / CY7C637xx. Details include errata trigger conditions, available workarounds, and silicon revision applicability. This document should be used to compare to the datasheet for this device to fully describe the device functionality. Please contact your local Cypress Sales Representative if you have further questions. Part Numbers Affected Part Number CY7C63722 CY7C63723 CY7C63743 Device Characteristics All packages All packages All packages enCoRe™ USB Combination Low-speed USB & PS/2 Peripheral Controller Qualification Status Product status: In Production - Qual report: 001406 enCoRe™ USB Combination Low-speed USB & PS/2 Peripheral Controller Errata Summary The following table defines the errata applicability to available enCoRe™ USB Combination Low-speed USB & PS/2 Peripheral Controller family devices. An "X" indicates that the errata pertains to the selected device. Note: Errata titles are hyperlinked. Click on table entry to jump to description. Items CY7C637xx Rev Letter Fix Status 1. Faulty GPIO Interrupt X A No silicon fix planned. 1. Faulty GPIO Interrupt • PROBLEM DEFINITION When a falling edge interrupt is enabled for a GPIO pin, reading the GPIO Port 1 coincident to a rising edge of that GPIO signal may generate a false GPIO interrupt. Any Port 0 or Port 1 GPIO pin with Falling Edge GPIO Interrupt Enabled Port 1 Read Signal (See Note 1) GPIO Interrupt Signal (See Note 2) Proper GPIO Interrupt Trigger False GPIO interrupt on a Rising edge Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 2004 CY7C637xx When a rising edge interrupt is enabled for a GPIO pin, reading the GPIO Port 1 coincident to a falling edge of that GPIO signal may generated a false GPIO intterupt Any Port 0 or Port 1 GPIO pin with Rising Edge GPIO Interrupt Enabled Port 1 Read Signal (See Note 1) GPIO Interrupt Signal (See Note 2) Proper GPIO Interrupt Trigger False GPIO interrupt on a Falling edge Note 1: Port 1 Read is an internal signal that is asserted when Port 1 is read with an "IORD 01h" instruction. Note 2: The GPIO Interrupt signal is an internal signal. The arrow indicates that a GPIO interrupt is triggered. • PARAMETERS AFFECTED Interrupts • TRIGGER CONDITION(S) Reading the GPIO Port 1 when either rising or falling edge interrupts are enabled for a GPIO pin. • SCOPE OF IMPACT The chip enters the GPIO Interrupt Service Routine (ISR) in error. • WORKAROUND Workarounds will need to be tailored to individual applications based on the flexibility of changing the GPIO usage, the timing of the GPIO interrupt sources and firmware interrupt latencies. • FIX STATUS No silicon fix is planned. References 1. 38-08022 CY7C63722/23/43 enCoRe™ USB Combination Low-speed USB & PS/2 Peripheral Controller datasheet. 2 CYC7637xx Document History Page Document Title: CY7C637xx Rev. A Errata Document Number: 38-17015 REV. 1.0 1.1 ** 215104 ECN NO. Issue Date March 14, 2003 May 1, 2003 See ECN Orig. of Change bon bon bha Initial release Added pictures to clarify the issus. Enter errata into spec system Description of Change © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.