CY7C638XX

CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller 1. Features ■ ■ ■ ■ 125 mA 3.3V voltage regulator powers external 3.3V devices 3.3V IO pins ❐ ❐ USB 2.0-USB-IF certified (TID # 40000085) enCoRe™ II USB - “enhanced Component Reduction” ❐ 4 IO pins with 3.3V logic levels Each 3.3V pin supports high impedance input, internal pull up, open drain output or traditional CMOS output Master or slave operation Configurable up to 4 Mbit/second transfers in the master mode Supports half duplex single data line mode for optical sensors Crystalless oscillator with support for an external clock. The internal oscillator eliminates the need for an external crystal or resonator. Two internal 3.3V regulators and an internal USB pull up resistor Configurable IO for real world interface without external components ■ SPI serial communication ❐ ❐ ❐ ❐ ❐ ■ USB Specification compliance ❐ ❐ ❐ ❐ ❐ ■ Conforms to USB Specification, Version 2.0 Conforms to USB HID Specification, Version 1.1 Supports one low speed USB device address Supports one control endpoint and two data endpoints Integrated USB transceiver with dedicated 3.3V regulator for USB signalling and D– pull up. Harvard architecture M8C CPU speed is up to 24 MHz or sourced by an external clock signal Up to 256 bytes of RAM Up to eight Kbytes of Flash including EEROM emulation No external components for switching between PS/2 and USB modes No General Purpose IO (GPIO) pins required to manage dual mode capability Typically 10 mA at 6 MHz 10 μA sleep Allows easy firmware update Up to 20 GPIO pins 2 mA source current on all GPIO pins. Configurable 8 or 50 mA/pin current sink on designated pins. Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output Maskable interrupts on all IO pins ■ ■ 2-channel 8-bit or 1-channel 16-bit capture timer registers. Capture timer registers store both rising and falling edge times. Two registers each for two input pins ❐ Separate registers for rising and falling edge capture ❐ Simplifies the interface to RF inputs for wireless applications ❐ Internal low power wakeup timer during suspend mode: ❐ Periodic wakeup with no external components ■ Enhanced 8-bit microcontroller ❐ ❐ ■ ■ ■ ■ ■ ■ ■ ■ 12-bit Programmable Interval Timer with interrupts Advanced development tools based on Cypress PSoC® tools Watchdog timer (WDT) Low voltage detection with user configurable threshold voltages Operating voltage from 4.0V to 5.5V DC Operating temperature from 0–70°C Available in 16 and 18-pin PDIP; 16, 18, and 24-pin SOIC; 24-pin QSOP, and 32-pin QFN packages Industry standard programmer support ■ Internal memory ❐ ❐ ■ Interface can auto configure to operate as PS/2 or USB ❐ ❐ 1.1 Applications The CY7C63310/CY7C638xx is targeted for the following applications: ■ ■ Low power consumption ❐ ❐ ■ In system reprogrammability: ❐ ■ PC HID devices ❐ Mice (optomechanical, optical, trackball) Gaming ❐ ❐ ■ GPIO ports ❐ ❐ ❐ Joysticks Game pad General purpose Barcode scanners POS terminal ❐ Consumer electronics ❐ Toys ❐ Remote controls ❐ Security dongles ❐ ❐ ❐ ■ A dedicated 3.3V regulator for the USB PHY. Aids in signalling and D– line pull up Cypress Semiconductor Corporation Document 38-08035 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 08 2008 [+] [+] Feedback CY7C63310, CY7C638xx 2. Logic Block Diagram 3.3V Regulator Low-Speed USB/PS2 Transceiver and Pull up Low-Speed USB SIE Interrupt Control 4 3VIO/SPI Pins Up to 14 Extended IO Pins Up to 6 GPIO pins Wakeup Timer Internal 24 MHz Oscillator Clock Control External Clock Watchdog Timer M8C CPU RAM Up to 256 Byte Flash Up to 8K Byte 12-bit Timer 16-bit Free running timer POR / Low-Voltage Detect Vdd Document 38-08035 Rev. *K Page 2 of 83 [+] [+] Feedback CY7C63310, CY7C638xx 3. Introduction Cypress has reinvented its leadership position in the low speed USB market with a new family of innovative microcontrollers. Introducing enCoRe II USB - “enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to advance its family of low speed USB microcontrollers, which enable peripheral developers to design new products with a minimum number of components. The enCoRe II USB technology builds on the enCoRe family. The enCoRe family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Also integrated into this chip are other external components commonly found in low speed USB applications, such as pull up resistors, wakeup circuitry, and a 3.3V regulator. Integrating these components reduces the overall system cost. The enCoRe II is an 8-bit Flash programmable microcontroller with an integrated low speed USB interface. The instruction set is optimized specifically for USB and PS/2 operations, although the microcontrollers may be used for a variety of other embedded applications. The enCoRe II features up to 20 GPIO pins to support USB, PS/2, and other applications. The IO pins are grouped into four ports (Port 0 to 3). The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2 and 3 are configured only as a group. Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to five pins that support a programmable drive strength of up to 50 mA sink current. GPIO Port 1 features four pins that interface at a voltage level of 3.3V. Additionally, each IO pin may be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector; in addition, GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.2 P0.4). The enCoRe II features an internal oscillator. With the presence of USB traffic, the internal oscillator may be set to precisely tune to USB timing requirements (24 MHz ±1.5%). Optionally, an external 12 MHz or 24 MHz clock is used to provide a higher precision reference for USB operation. The clock generator provides the 12 MHz and 24 MHz clocks that remain internal to the microcontroller. The enCoRe II also has a 12-bit programmable interval timer and a 16-bit Free Running Timer with Capture Timer registers. In addition, the enCoRe II includes a Watchdog timer and a vectored interrupt controller. The enCoRe II has up to eight Kbytes of Flash for user code and up to 256 bytes of RAM for stack space and user variables. The power on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates a reset or may be configured to generate an interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. It is configurable to generate an LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt. There is no separate interrupt for each. The Watchdog timer may be used to ensure the firmware never gets stalled in an infinite loop. The microcontroller supports 22 maskable interrupts in the vectored interrupt controller. Interrupt sources include a USB bus reset, LVR/POR, a programmable interval timer, a 1.024 ms output from the free-running timer, three USB endpoints, two capture timers, four GPIO Ports, three Port 0 pins, two SPI, a 16-bit free running timer wrap, an internal sleep timer, and a bus active interrupt. The sleep timer causes periodic interrupts when enabled. The USB endpoints interrupt after a USB transaction complete is on the bus. The capture timers interrupt when a new timer value is saved because of a selected GPIO edge event. A total of seven GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility on the edge sensitive GPIO pins, the interrupt polarity is programmed as rising or falling. The free-running 16-bit timer provides two interrupt sources: the 1.024 ms outputs and the free running counter wrap interrupt. The programmable interval timer provides up to 1 μsec resolution and provides an interrupt every time it expires. These timers are used to measure the duration of an event under firmware control by reading the desired timer at the start and at the end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers save a programmable 8-bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.5, P0.6). The two 8-bit captures may be ganged into a single 16-bit capture. The enCoRe II includes an integrated USB serial interface engine (SIE) that allows the chip to easily interface to a USB host. The hardware supports one USB device address with three endpoints. The USB D+ and D– pins are optionally used as PS/2 SCLK and SDATA signals so that products are designed to respond to either USB or PS/2 modes of operation. The PS/2 operation is supported with internal 5 KΩ pull up resistors on P1.0 (D+) and P1.1 (D–), and an interrupt to signal the start of PS/2 activity. In USB mode, the integrated 1.5 KΩ pull up resistor on D– may be controlled under firmware. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. The enCoRe II supports in system programming by using the D+ and D– pins as the serial programming mode interface. The programming protocol is not USB. 4. Conventions In this data sheet, bit positions in the registers are shaded to indicate which members of the enCoRe II family implement the bits. Available in all enCoRe II family members CY7C638(1/2/3)3 only Document 38-08035 Rev. *K Page 3 of 83 [+] [+] Feedback CY7C63310, CY7C638xx 5. Pinouts Figure 5-1. Pin Diagrams Top View CY7C63801, CY7C63310 16-Pin PDIP SSEL/P1.3 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P1.2 VCC P1.1/D– P1.0/D+ VSS P0.0 P0.1 P0.2/INT0 CY7C63801, CY7C63310 16-Pin SOIC TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VCC P1.1/D– P1.0/D+ CY7C63803 16-Pin SOIC TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VCC P1.1/D– P1.0/D+ CY7C63813 18-Pin PDIP SSEL/P1.3 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 P1.2/VREG VCC P1.1/D– P1.0/D+ VSS P0.0 P0.1 P0.2/INT0 P0.3/INT1 CY7C63813 18-Pin SOIC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VCC P1.1/D– P1.0/D+ CY7C63823 24-Pin QSOP NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 P2.1 P2.0 NC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2/VREG VCC P1.1/D– P1.0/D+ VSS CY7C63823 24-Pin SOIC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 P2.1 P2.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2/VREG VCC P1.1/D– P1.0/D+ CY7C63833 P0.7 32-Pin QFN P1.6/MISO P1.7 CY7C63833 32-Pin Sawn QFN P0.7 P1.7 P1.6/MISO NC NC NC NC NC NC NC NC NC 32 31 30 29 28 27 26 25 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1 P0.0 P2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P1.0/D+ P2.0 P1.1/DVss NC NC NC Vdd 24 23 22 21 20 19 18 17 P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL NC P1.2/VREG NC 32 31 30 29 28 27 26 25 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1 P0.0 P2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P1.0/D+ P2.0 P1.1/DVss Vdd NC NC NC 24 23 22 21 20 19 18 17 P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL NC P1.2/VREG NC Document 38-08035 Rev. *K NC Page 4 of 83 [+] [+] Feedback CY7C63310, CY7C638xx Figure 5-2. CY7C63823 Die Form 23 1 2 3 4 Y 22 Cypress Logo 21 20 19 18 17 16 X 15 14 5 6 7 8 9 12 10 11 13 Legend Die step = 1792.98 μm x 2272.998 μm Die size = 1727 μm x 2187 μ m Bond pad opening = 70 μm x 70 μ m Die thickness = 14 mils Table 5-1. Die Pad Summary Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pad Name P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 CLKIN P2.1 P2.0 VSS PI.0 D+ P1.1 D– VDD P1.2 VREG P1.3 P3.0 P3.1 P1.4 P1.5 SMOSI P1.6 SMISO P1.7 Reserved X (microns) -742.730 -755.060 -755.060 -755.060 -755.060 -755.060 -755.060 -755.060 -755.060 -393.580 537.500 736.110 736.110 736.110 736.110 723.510 723.510 723.510 723.510 723.510 723.510 696.630 -795.400 Y (microns) 911.990 792.200 699.300 606.400 -430.080 -522.980 -618.830 -714.020 -810.220 -977.930 -964.700 -936.680 -625.130 -260.670 53.800 336.780 438.690 532.880 635.310 728.220 839.290 1008.480 1023.270 Document 38-08035 Rev. *K Page 5 of 83 [+] [+] Feedback CY7C63310, CY7C638xx Table 5-2. Pin Description 32 QFN 24 QSOP 24 SOIC 18 SIOC 18 PDIP 16 SOIC 16 PDIP Name Description 21 22 9 8 14 19 20 11 10 14 18 19 11 10 13 10 15 9 13 P3.0 P3.1 P2.0 P2.1 P1.0/D+ GPIO Port 3. Configured as a group (byte). GPIO Port 2. Configured as a group (byte). GPIO Port 1 bit 0/USB D+ [1] If this pin is used as a General Purpose output, it draws current. This pin must be configured as an input to reduce current draw. GPIO Port 1 bit 1/USB D– [1] If this pin is used as a General Purpose output, it draws current. This pin must be configured as an input to reduce current draw. 15 15 14 11 16 10 14 P1.1/D– 18 17 16 13 18 12 16 P1.2/VREG GPIO Port 1 bit 2. Configured individually. 3.3V if regulator is enabled. (The 3.3V regulator is not available in the CY7C63310 and CY7C63801.) A 1-μF min, 2-μF max capacitor is required on Vreg output. P1.3/SSEL GPIO Port 1 bit 3. Configured individually. Alternate function is SSEL signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V IO is still available. P1.4/SCLK GPIO Port 1 bit 4. Configured individually. Alternate function is SCLK signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V IO is still available. P1.5/SMOSI GPIO Port 1 bit 5. Configured individually. Alternate function is SMOSI signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V IO is still available. P1.6/SMISO GPIO Port 1 bit 6. Configured individually. Alternate function is SMISO signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V IO is still available. P1.7 GPIO Port 1 bit 7. Configured individually. TTL voltage threshold. GPIO Port 0 bit 0. Configured individually. On CY7C638xx and CY7C63310, external clock input when configured as Clock In. GPIO Port 0 bit 1. Configured individually. On CY7C638xx and CY7C63310, clock output when configured as Clock Out. 20 18 17 14 1 13 1 23 21 20 15 2 14 2 24 22 21 16 3 15 3 25 23 22 17 4 16 4 26 7 24 9 23 9 18 8 5 13 7 11 P0.0 6 8 8 7 12 6 10 P0.1 5 4 3 7 6 5 7 6 5 6 5 4 11 10 9 5 4 3 9 8 7 P0.2/INT0 GPIO Port 0 bit 2. Configured individually. Optional rising edge interrupt INT0. P0.3/INT1 GPIO Port 0 bit 3. Configured individually. Optional rising edge interrupt INT1. P0.4/INT2 GPIO Port 0 bit 4. Configured individually. Optional rising edge interrupt INT2. Note 1. P1.0(D+) and P1.1(D–) pins must be in IO mode when used as GPIO and in Isb mode. Document 38-08035 Rev. *K Page 6 of 83 [+] [+] Feedback CY7C63310, CY7C638xx Table 5-2. Pin Description (continued) 32 QFN 24 QSOP 24 SOIC 18 SIOC 18 PDIP 16 SOIC 16 PDIP Name Description 2 4 4 3 8 2 6 P0.5/TIO0 GPIO Port 0 bit 5. Configured individually Alternate function Timer capture inputs or Timer output TIO0 P0.6/TIO1 GPIO Port 0 bit 6. Configured individually Alternate function Timer capture inputs or Timer output TIO1 P0.7 NC NC NC NC NC NC NC NC NC NC GPIO Port 0 bit 7. Configured individually Not present in the 16 pin PDIP or SOIC package No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect Supply Ground 1 3 3 2 7 1 5 32 10 11 12 17 19 27 28 29 30 31 16 13 2 1 12 2 1 24 1 6 16 13 15 12 12 9 17 14 11 8 15 12 Vcc VSS 6. CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 6-1. CPU Registers and Register Names CPU Register Flags Program Counter Accumulator Stack Pointer Index Register Name CPU_F CPU_PC CPU_A CPU_SP CPU_X The Stack Pointer Register (CPU_SP) holds the address of the current top of the stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It is also affected by the SWAP and ADD instructions. The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] globally enables or disables interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed, such as AND, OR, XOR, and others. See Table 8-1 on page 12. The 16-bit Program Counter Register (CPU_PC) allows direct addressing of the full 8 Kbytes of program memory space. The Accumulator Register (CPU_A) is the general purpose register, which holds the results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. Document 38-08035 Rev. *K Page 7 of 83 [+] [+] Feedback CY7C63310, CY7C638xx 7. CPU Registers The CPU registers in enCoRe II devices are in two banks with 256 registers in each bank. Bit[4]/XIO bit in the CPU Flags register must be set/cleared to select between the two register banks Table 7-1 on page 8 7.1 Flags Register The Flags Register is set or reset only with logical instruction. Table 7-1. CPU Flags Register (CPU_F) [R/W] Bit # Field Read/Write Default – 0 7 6 Reserved – 0 – 0 5 4 XIO R/W 0 3 Super R 0 2 Carry RW 0 1 Zero RW 1 0 Global IE RW 0 Bit [7:5]: Reserved Bit 4: XIO Set by the user to select between the register banks 0 = Bank 0 1 = Bank 1 Bit 3: Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.) 0 = User Code 1 = Supervisor Code Bit 2: Carry Set by the CPU to indicate whether there has been a carry in the previous logical/arithmetic operation. 0 = No Carry 1 = Carry Bit 1: Zero Set by the CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation. 0 = Not Equal to Zero 1 = Equal to Zero Bit 0: Global IE Determines whether all interrupts are enabled or disabled 0 = Disabled 1 = Enabled Note CPU_F register is only readable with the explicit register address 0xF7. The OR F, expr and AND F, expr instructions must be used to set and clear the CPU_F bits. Table 7-2. CPU Accumulator Register (CPU_A) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 CPU Accumulator [7:0] Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode Document 38-08035 Rev. *K Page 8 of 83 [+] [+] Feedback CY7C63310, CY7C638xx Table 7-3. CPU X Register (CPU_X) Bit # Field Read/Write Default – 0 – 0 – 0 – 0 7 6 5 4 X [7:0] – 0 – 0 – 0 – 0 3 2 1 0 Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. Table 7-4. CPU Stack Pointer Register (CPU_SP) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 Stack Pointer [7:0] Bit [7:0]: Stack Pointer [7:0] 8-bit data value holds a pointer to the current top of the stack. Table 7-5. CPU Program Counter High Register (CPU_PCH) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 Program Counter [15:8] Bit [7:0]: Program Counter [15:8] 8-bit data value holds the higher byte of the program counter. Table 7-6. CPU Program Counter Low Register (CPU_PCL) Bit # Field Read/Write Default – 0 – 0 – 0 7 6 5 4 – 0 3 – 0 2 – 0 1 – 0 0 – 0 Program Counter [7:0] Bit [7:0]: Program Counter [7:0] 8-bit data value holds the lower byte of the program counter. 7.2 Addressing Modes 7.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources; the second source is the A or the X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 7-7. Source Immediate Opcode Instruction Examples ADD A 7 The immediate value of 7 is added with the Accumulator and the result is placed in the Accumulator. The immediate value of 8 is moved to the X register. The immediate value of 9 is logically ANDed with the F register and the result is placed in the F register. Operand 1 Immediate Value MOV AND X F 8 9 Document 38-08035 Rev. *K Page 9 of 83 [+] [+] Feedback CY7C63310, CY7C638xx 7.2.2 Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in the RAM memory space or the register space that is the source of the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 7-8. Source Direct Opcode Instruction Examples ADD A [7] The value in the RAM memory location at address 7 is added with the Accumulator, and the result is placed in the Accumulator. The value in the register space at address 8 is moved to the X register. 7.2.4 Destination Direct The result of an instruction using this addressing mode is placed within the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 7-10. Destination Direct Operand 1 Source Address Opcode Instruction Examples ADD [7] A The value in the memory location at address 7 is added with the Accumulator, and the result is placed in the memory location at address 7. The Accumulator is unchanged. The Accumulator is moved to the register space location at address 8. The Accumulator is unchanged. Operand 1 Destination Address MOV X REG[8] MOV REG[8] A 7.2.3 Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in the RAM memory space or the register space that is the source of the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 7-9. Source Indexed Opcode Instruction Examples ADD A [X+7] The value in the memory location at address X + 7 is added with the Accumulator, and the result is placed in the Accumulator. The value in the register space at address X + 8 is moved to the X register. 7.2.5 Destination Indexed The result of an instruction using this addressing mode is placed within the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Table 7-11. Destination Indexed Opcode Instruction Example ADD [X+7] A The value in the; memory location at address X+7 is added with the Accumulator, and the result is placed in the memory location at address x+7. The Accumulator is unchanged. Operand 1 Source Index Operand 1 Destination Index MOV X REG[X+8] Document 38-08035 Rev. *K Page 10 of 83 [+] [+] Feedback CY7C63310, CY7C638xx 7.2.6 Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within the RAM memory space or the register space. Operand 1 is the address of the result. The source of the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 7-12. Destination Direct Source Immediate Opcode Instruction Examples ADD [7] 5 The value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. The immediate value of 6 is moved into the register space location at address 8. . Table 7-14. Destination Direct Source Direct Opcode Instruction Example MOV [7] [8] The value in the memory location at address 8 is moved to the memory location at address 7. Operand 1 Destination Address Operand 2 Source Address Operand 1 Destination Address Operand 2 Immediate Value 7.2.9 Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Table 7-15. Source Indirect Post Increment MOV REG[8] 6 7.2.7 Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source of the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 7-13. Destination Indexed Source Immediate Opcode Instruction Examples ADD [X+7] 5 The value in the memory location at address X+7 is added with the immediate value of 5, and the result is placed in the memory location at address X+7. The immediate value of 6 is moved into the location in the register space at address X+8. Opcode Instruction Example MVI A [8] Operand 1 Source Address Address The value in the memory location at address 8 is an indirect address. The memory location pointed to by the indirect address is moved into the Accumulator. The indirect address is then incremented. Operand 1 Destination Index Operand 2 Immediate Value 7.2.10 Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 7-16. Destination Indirect Post Increment Opcode Instruction Example MVI [8] A The value in the memory location at address 8 is an indirect address. The Accumulator is moved into the memory location pointed to by the indirect address. The indirect address is then incremented. MOV REG[X+8] 6 Operand 1 Destination Address Address 7.2.8 Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Document 38-08035 Rev. *K Page 11 of 83 [+] [+] Feedback CY7C63310, CY7C638xx 8. Instruction Set Summary The instruction set is summarized in Table 8-1 numerically and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the Cypress web site at http://www.cypress.com). Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order[2, 3] Opcode Hex Opcode Hex Opcode Hex Cycles Cycles Cycles Bytes Bytes Instruction Format Flags C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z Z Z Z Z Z Z Z Z Z Z Z Instruction Format Flags Z Z Z Z Z Z Z Z Z Z Bytes Instruction Format Flags Z Z Z 00 15 01 02 03 04 05 06 08 09 0A 0B 0C 0D 0E 10 11 12 13 14 15 16 18 19 1A 1B 1C 1D 1E 20 21 22 23 24 25 26 4 6 7 7 8 9 4 4 6 7 7 8 9 4 4 6 7 7 8 9 5 4 6 7 7 8 9 5 4 6 7 7 8 9 1 SSC 2 ADD A, expr 2 ADD A, [expr] 2 ADD A, [X+expr] 2 ADD [expr], A 2 ADD [X+expr], A 3 ADD [expr], expr 3 ADD [X+expr], expr 1 PUSH A 2 ADC A, expr 2 ADC A, [expr] 2 ADC A, [X+expr] 2 ADC [expr], A 2 ADC [X+expr], A 3 ADC [expr], expr 3 ADC [X+expr], expr 1 PUSH X 2 SUB A, expr 2 SUB A, [expr] 2 SUB A, [X+expr] 2 SUB [expr], A 2 SUB [X+expr], A 3 SUB [expr], expr 3 SUB [X+expr], expr 1 POP A 2 SBB A, expr 2 SBB A, [expr] 2 SBB A, [X+expr] 2 SBB [expr], A 2 SBB [X+expr], A 3 SBB [expr], expr 3 SBB [X+expr], expr 1 POP X 2 AND A, expr 2 AND A, [expr] 2 AND A, [X+expr] 2 AND [expr], A 2 AND [X+expr], A 3 AND [expr], expr 3 AND [X+expr], expr 1 ROMX 2 OR A, expr 2 OR A, [expr] 2 OR A, [X+expr] 2 OR [expr], A 2D 2E 30 31 32 33 34 35 36 38 39 3A 3B 3C 3D 8 9 9 4 6 7 7 8 9 5 5 7 8 8 9 2 OR [X+expr], A 3 OR [expr], expr 3 OR [X+expr], expr 1 HALT 2 XOR A, expr 2 XOR A, [expr] 2 XOR A, [X+expr] 2 XOR [expr], A 2 XOR [X+expr], A 3 XOR [expr], expr 3 XOR [X+expr], expr 2 ADD SP, expr 2 CMP A, expr 2 CMP A, [expr] 2 CMP A, [X+expr] 3 CMP [expr], expr 3 CMP [X+expr], expr 2 MVI A, [ [expr]++] 2 MVI [ [expr]++], A 1 NOP 3 AND reg[expr], expr 3 AND reg[X+expr], expr 3 OR reg[expr], expr 3 OR reg[X+expr], expr 3 XOR reg[expr], expr 3 XOR reg[X+expr], expr 3 TST [expr], expr 3 TST [X+expr], expr 3 TST reg[expr], expr 3 TST reg[X+expr], expr 1 SWAP A, X 2 SWAP A, [expr] 2 SWAP X, [expr] 1 SWAP A, SP 1 MOV X, SP 2 MOV A, expr 2 MOV A, [expr] 2 MOV A, [X+expr] 2 MOV [expr], A 2 MOV [X+expr], A 3 MOV [expr], expr 3 MOV [X+expr], expr 2 MOV X, expr 2 MOV X, [expr] 2 MOV X, [X+expr] 5A 5B 5C 5D 5E 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 5 4 4 6 7 5 6 8 9 4 7 8 4 7 8 4 7 8 4 7 8 4 4 4 4 4 4 7 8 4 4 7 8 7 8 5 5 5 5 5 7 2 MOV [expr], X 1 MOV A, X 1 MOV X, A 2 MOV A, reg[expr] 2 MOV A, reg[X+expr] 3 MOV [expr], [expr] 2 MOV reg[expr], A 2 MOV reg[X+expr], A 3 MOV reg[expr], expr 3 MOV reg[X+expr], expr 1 ASL A 2 ASL [expr] 2 ASL [X+expr] 1 ASR A 2 ASR [expr] 2 ASR [X+expr] 1 RLC A 2 RLC [expr] 2 RLC [X+expr] 1 RRC A 2 RRC [expr] 2 RRC [X+expr] 2 AND F, expr 2 OR F, expr 2 XOR F, expr 1 CPL A 1 INC A 1 INC X 2 INC [expr] 2 INC [X+expr] 1 DEC A 1 DEC X 2 DEC [expr] 2 DEC [X+expr] 3 LCALL 3 LJMP 1 RETI 1 RET 2 JMP 2 CALL 2 JZ 2 JNZ 2 JC 2 JNC 2 JACC Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z 2F 10 5F 10 07 10 37 10 if (A=B) Z=1 if (A10