CY7C64315-16LKXCT

CY7C6431x CY7C64345, CY7C6435x enCoRe™ V Full-Speed USB Controller Features Powerful Harvard Architecture Processor ❐ M8C processor speeds running up to 24 MHz ❐ Low power at high processing speeds ❐ Interrupt controller ❐ 3.0V to 5.5V operating voltage without USB ❐ Operating voltage with USB enabled: • 3.15 to 3.45V when supply voltage is around 3.3V • 4.35 to 5.25V when supply voltage is around 5.0V ❐ Temperature range: 0°C to 70°C ■ Flexible On-Chip Memory ❐ Up to 32K Flash program storage 50,000 erase/write cycles ❐ Up to 2048 bytes SRAM data storage ❐ Flexible protection modes ❐ In-System Serial Programming (ISSP) ■ Complete Development Tools ❐ Free development tool (PSoC Designer™) ❐ Full featured, in-circuit emulator and programmer ❐ Full speed emulation ❐ Complex breakpoint structure ❐ 128K trace memory ■ Precision, Programmable Clocking ❐ Crystal-less oscillator with support for an external crystal or resonator ❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator ❐ Internal low speed oscillator at 32 kHz for watchdog and sleep. The frequency range is 19–50 kHz with a 32 kHz typical value ❐ 0.25% accuracy for USB with no external components ■ Programmable Pin Configurations ❐ 25 mA sink current on all GPIO ■ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO Configurable inputs on all GPIO ❐ Low dropout voltage regulator for Port 1 pins. Programmable to output 3.0, 2.5, or 1.8V at the IO pins ❐ Selectable, regulated digital IO on Port 1 • Configurable input threshold for Port 1 • 3.0V, 20 mA total Port 1 source current • Hot-swappable ❐ 5 mA strong drive mode on Ports 0 and 1 ❐ ❐ ■ Full-Speed USB (12 Mbps) ❐ Eight unidirectional endpoints ❐ One bidirectional control endpoint ❐ USB 2.0 compliant ❐ Dedicated 512 bytes buffer ❐ No external crystal required Additional System Resources ❐ Configurable communication speeds 2 ❐ I C™ slave • Selectable to 50 kHz, 100 kHz, or 400 kHz • Implementation requires no clock stretching • Implementation during sleep modes with less than 100 µA • Hardware address detection ❐ SPI™ master and SPI slave • Configurable between 93.75 kHz and 12 MHz ❐ Three 16-bit timers ❐ 8-bit ADC used to monitor battery voltage or other signals with external components ❐ Watchdog and sleep timers ❐ Integrated supervisory circuit ■ enCoRe V Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO enCoRe V CORE System Bus SRAM 2048 Bytes Interrupt Controller SROM Flash 32K Sleep and Watchdog CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator 3 16-Bit Timers I2C Slave/SPI Master-Slave POR and LVD System Resets Full Speed USB SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-12394 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 7, 2008 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Functional Overview The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components with one, low cost single-chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The architecture for this device family, as illustrated in enCoRe V Block Diagram Block Diagram, is comprised of three main areas: the CPU core, the system resources, and the full-speed USB system. Depending on the enCoRe V package, up to 36 general purpose IO (GPIO) are also included. This product is an enhanced version of Cypress’ successful full-speed USB peripheral controllers. Enhancements include faster CPU at lower voltage operation, lower current consumption, twice the RAM and Flash, hot-swappable IOs, I2C hardware address recognition, new very low current sleep mode, and new package options. ■ Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (power on reset) circuit eliminates the need for a system supervisor. The 5V maximum input, 1.8, 2.5, or 3V selectable output, low dropout regulator (LDO) provides regulation for IOs. A register controlled bypass mode allows the user to disable the LDO. Standard Cypress PSoC IDE tools are available for debugging the enCoRe V family of parts. ■ ■ Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com. The enCoRe V Core The enCoRe V Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard architecture microprocessor. System resources provide additional capability, such as a configurable I2C slave and SPI master-slave communication interface and various system resets supported by the M8C. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com/shop/. Under Product Categories click PSoC® Mixed Signal Arrays to view a current list of available items. Additional System Resources System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below. ■ Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://www.cypress.com/techtrain. Full-speed USB (12 Mbps) with nine configurable endpoints and 512 bytes of dedicated USB RAM. No external components are required except two series resistors. It is specified for commercial temperature USB operation. For reliable USB operation, ensure the supply voltage is between 4.35V and 5.25V, or around 3.3V. 10-bit on-chip ADC shared between system performance manager (used to calculate parameters based on temperature for flash write operations) and the user. The I2C slave and SPI master-slave module provides 50, 100, or 400 kHz communication over two wires. SPI communication over 3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). In I2C slave mode, the hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device is received. Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Support located at the top of the web page, and select CYPros Consultants. ■ Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a four hour guaranteed response at http://www.cypress.com/support. ■ Application Notes A long list of application notes assists you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Documentation list located at the top of the web page. Application notes are sorted by date by default. ■ Document Number: 001-12394 Rev. *F Page 2 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Development Tools PSoC Designer™ is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows XP and Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. Code Generation Tools PSoC Designer supports multiple third-party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to be merged seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. PSoC Designer Software Subsystems System-Level View The system-level view is a drag-and-drop visual embedded system design environment based on PSoC Express. In this view you solve design problems the same way you might think about the system. Select input and output devices based upon system requirements. Add a communication interface and define the interface to the system (registers). Define when and how an output device changes state based upon any/all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.x. You choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. You configure the user modules for your chosen application and connect them to each other and to the proper pins. Then you generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share common code editor, builder, and common debug, emulation, and programming tools. Document Number: 001-12394 Rev. *F Page 3 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select Components 2. Configure Components 3. Organize and Connect 4. Generate, Verify, and Debug Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the IO pins, or connect system-level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog-to-digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan. In the chip-level view, you perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Select Components Both the system-level and chip-level views provide a library of pre-built, pre-tested hardware peripheral components. In the system-level view these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view the components are called “user modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed-signal varieties. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s Debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. Document Number: 001-12394 Rev. *F Page 4 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym API CPU GPIO GUI ICE ILO IMO IO LSb LVD MSb POR PPOR PSoC® SLIMO SRAM Description application programming interface central processing unit general purpose IO graphical user interface in-circuit emulator internal low speed oscillator internal main oscillator input/output least significant bit low voltage detect most significant bit power on reset precision power on reset Programmable System-on-Chip™ slow IMO static random access memory Units of Measure A units of measure table is located in the Electrical Specifications section. Table 7 on page 14 lists all the abbreviations used to measure the enCoRe V devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Document Number: 001-12394 Rev. *F Page 5 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Pin Configuration The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables. 16-Pin Part Pinout Figure 1. CY7C64315/CY7C64316 16-Pin enCoRe V Device P2[5] P0[1] 15 P0[3] 14 16 13 P0[7] P2[3] P1[7] P1[5] P1[1] 1 2 3 4 12 QFN 11 (Top View) 10 9 6 D+ D– Vdd 7 8 P0[4] XRES P1[4] P1[0] Table 1. 16-Pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type IO IOHR IOHR IOHR Power USB line USB line Power IOHR IOHR Input IOH IOH IOH IOH IO Name P2[3] P1[7] P1[5] P1[1](1, 2) Vss D+ D– Vdd P1[0](1, 2) P1[4] XRES P0[4] P0[7] P0[3] P0[1] P2[5] Description Digital IO, Crystal Input (Xin) Digital IO, SPI SS, I2C SCL Digital IO, SPI MISO, I2C SDA Digital IO, ISSP CLK, 12C SCL, SPI MOSI Ground connection USB PHY USB PHY Supply Digital IO, ISSP DATA, I2C SDA, SPI CLK Digital IO, optional external clock input (EXTCLK) Active high external reset with internal pull down Digital IO Digital IO Digital IO Digital IO Digital IO, Crystal Output (Xout) LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Notes 1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered. 2. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *F Vss 5 Page 6 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x 32-Pin Part Pinout Figure 2. CY7C64345 32-Pin enCoRe V USB Device P0[3] P0[7] P0[6] P0[4] 26 P0[5] 32 31 30 29 28 27 P0[1] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] 25 P0[2] Vss Vdd 1 2 3 4 5 6 9 10 11 12 13 14 15 16 7 8 24 23 22 21 20 19 18 17 P0[0] P2[6] P2[4] P2[2] P2[0] P3[2] P3[0] XRES QFN ( Top View) P1[2] P1[4] Table 2. 32-Pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Type IOH IO IO IO IOHR IOHR IOHR IOHR Power IO IO Power IOHR IOHR IOHR IOHR Reset IO IO IO IO IO IO Name P0[1] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1](1, 2) Vss D+ D– Vdd P1[0](1, 2) P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] Digital IO Digital IO, Crystal Output (Xout) Digital IO, Crystal Input (Xin) Digital IO Digital IO, I2C SCL, SPI SS Digital IO, I2C SDA, SPI MISO Digital IO, SPI CLK Digital IO, ISSP CLK, I2C SCL, SPI MOSI Ground USB PHY USB PHY Supply voltage Digital IO, ISSP DATA, I2C SDA, SPI CLK Digital IO Digital IO, optional external clock input (EXTCLK) Digital IO Active high external reset with internal pull down Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Description Document Number: 001-12394 Rev. *F P1[0] P1[6] Vdd Vss D+ D– Page 7 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Table 2. 32-Pin Part Pinout (QFN) (continued) Pin No. 24 25 26 27 28 29 30 31 32 CP Type IOH IOH IOH IOH Power IOH IOH IOH Power Power Name P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Vss Digital IO Digital IO Digital IO Digital IO Supply voltage Digital IO Digital IO Digital IO Ground Ensure the center pad is connected to ground Description LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Document Number: 001-12394 Rev. *F Page 8 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x 48-Pin Part Pinout Figure 3. CY7C64355/CY7C64356 48-Pin enCoRe V USB Device P0[1] Vss P0[3] Vdd P0[6] P0[4] P0[2] 39 P0[5] P0[7] P0[0] NC NC 43 48 47 46 45 44 42 41 40 38 37 NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] 1 2 3 4 5 6 36 35 34 33 32 31 30 29 28 27 QFN (Top View) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 P1[5] P1[3] Table 3. 48-Pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Type NC IO IO IO IO IO IO IO IO IO IO IOHR IOHR NC NC IOHR IOHR Power IO IO Power IOHR IOHR IOHR IOHR NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1](1, 2) Vss D+ D– Vdd P1[0](1, 2) P1[2] P1[4] P1[6] Pin Name No connection Digital IO Digital IO, Crystal Out (Xout) Digital IO, Crystal In (Xin) Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO, I2C SCL, SPI SS Digital IO, I2C SDA, SPI MISO No connection No connection Digital IO, SPI CLK Digital IO, ISSP CLK, I2C SCL, SPI MOSI Supply ground USB USB Supply voltage Digital IO, ISSP DATA, I2C SDA, SPI CLK Digital IO, Digital IO, optional external clock input (EXTCLK) Digital IO Page 9 of 29 Description Document Number: 001-12394 Rev. *F P1[1] P1[0] P1[2] P1[4] NC NC D+ DVdd Vss 22 23 24 26 25 P2[6] P2[4] P2[2] P2[0] P4[2] P4[0] P3[6] P3[4] P3[2] P3[0] XRES P1[6] [+] Feedback CY7C6431x CY7C64345, CY7C6435x Table 3. 48-Pin Part Pinout (QFN) (continued) Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Type XRES IO IO IO IO IO IO IO IO IO IO IOH IOH IOH IOH Power NC NC IOH IOH IOH Power IOH Pin Name Ext Reset P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd NC NC P0[7] P0[5] P0[3] Vss P0[1] Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Supply voltage No connection No connection Digital IO Digital IO Digital IO Supply ground Digital IO Description Active high external reset with internal pull down LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Document Number: 001-12394 Rev. *F Page 10 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Register Reference The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order. Register Conventions The register conventions specific to this section are listed in the following table. Table 4. Register Conventions Convention R W O L C # Description Read register or bits Write register or bits Only a read/write register or bits Logical register or bits Clearable register or bits Access is bit specific Register Mapping Tables The enCoRe V device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space). The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Document Number: 001-12394 Rev. *F Page 11 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE Addr (0,Hex) Access Name 00 RW EP1_CNT0 01 RW EP1_CNT1 02 EP2_CNT0 03 EP2_CNT1 PRT1DR 04 RW EP3_CNT0 PRT1IE 05 RW EP3_CNT1 06 EP4_CNT0 07 EP4_CNT1 PRT2DR 08 RW EP5_CNT0 PRT2IE 09 RW EP5_CNT1 0A EP6_CNT0 0B EP6_CNT1 PRT3DR 0C RW EP7_CNT0 PRT3IE 0D RW EP7_CNT1 0E EP8_CNT0 0F EP8_CNT1 PRT4DR 10 RW PRT4IE 11 RW 12 13 14 15 16 17 18 PMA0_DR 19 PMA1_DR 1A PMA2_DR 1B PMA3_DR 1C PMA4_DR 1D PMA5_DR 1E PMA6_DR 1F PMA7_DR 20 21 22 23 24 PMA8_DR 25 PMA9_DR 26 PMA10_DR 27 PMA11_DR 28 PMA12_DR SPI_TXR 29 W PMA13_DR SPI_RXR 2A R PMA14_DR SPI_CR 2B # PMA15_DR 2C TMP_DR0 2D TMP_DR1 2E TMP_DR2 2F TMP_DR3 30 USB_SOF0 31 R USB_SOF1 32 R USB_CR0 33 RW USBIO_CR0 34 # USBIO_CR1 35 # EP0_CR 36 # EP0_CNT0 37 # EP0_DR0 38 RW EP0_DR1 39 RW EP0_DR2 3A RW EP0_DR3 3B RW EP0_DR4 3C RW EP0_DR5 3D RW EP0_DR6 3E RW EP0_DR7 3F RW Gray fields are reserved; do not access these fields. Addr (0,Hex) Access 40 # 41 RW 42 # 43 RW 44 # 45 RW 46 # 47 RW 48 # 49 RW 4A # 4B RW 4C # 4D RW 4E # 4F RW 50 51 52 53 54 55 56 57 58 RW 59 RW 5A RW 5B RW 5C RW 5D RW 5E RW 5F RW 60 61 62 63 64 RW 65 RW 66 RW 67 RW 68 RW 69 RW 6A RW 6B RW 6C RW 6D RW 6E RW 6F RW 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. Name Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access I2C_XCFG I2C_XSTAT I2C_ADDR I2C_BP I2C_CP CPU_BP CPU_CP I2C_BUF CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK2 INT_MSK1 INT_MSK0 INT_SW_EN INT_VC RES_WDT INT_MSK3 RW R RW R R RW R RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RC W RW PT0_CFG PT0_DATA1 PT0_DATA0 PT1_CFG PT1_DATA1 PT1_DATA0 PT2_CFG PT2_DATA1 PT2_DATA0 RW RW RW RW RW RW RW RW RW CPU_F RL CPU_SCR1 CPU_SCR0 # # Document Number: 001-12394 Rev. *F Page 12 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 Addr (1,Hex) Access Name Addr (1,Hex) Access 00 RW PMA4_RA 40 RW 01 RW PMA5_RA 41 RW 02 PMA6_RA 42 RW 03 PMA7_RA 43 RW PRT1DM0 04 RW PMA8_WA 44 RW PRT1DM1 05 RW PMA9_WA 45 RW 06 PMA10_WA 46 RW 07 PMA11_WA 47 RW PRT2DM0 08 RW PMA12_WA 48 RW PRT2DM1 09 RW PMA13_WA 49 RW 0A PMA14_WA 4A RW 0B PMA15_WA 4B RW PRT3DM0 0C RW PMA8_RA 4C RW PRT3DM1 0D RW PMA9_RA 4D RW 0E PMA10_RA 4E RW 0F PMA11_RA 4F RW PRT4DM0 10 RW PMA12_RA 50 RW PRT4DM1 11 RW PMA13_RA 51 RW 12 PMA14_RA 52 RW 13 PMA15_RA 53 RW 14 EP1_CR0 54 # 15 EP2_CR0 55 # 16 EP3_CR0 56 # 17 EP4_CR0 57 # 18 EP5_CR0 58 # 19 EP6_CRO 59 # 1A EP7_CR0 5A # 1B EP8_CR0 5B # 1C 5C 1D 5D 1E 5E 1F 5F 20 60 21 61 22 62 23 63 24 64 25 65 26 66 27 67 28 68 SPI_CFG 29 RW 69 2A 6A 2B 6B 2C TMP_DR0 6C RW 2D TMP_DR1 6D RW 2E TMP_DR2 6E RW 2F TMP_DR3 6F RW USB_CR1 30 # 70 31 71 32 72 USBIO_CR2 33 RW 73 PMA0_WA 34 RW 74 PMA1_WA 35 RW 75 PMA2_WA 36 RW 76 PMA3_WA 37 RW 77 PMA4_WA 38 RW 78 PMA5_WA 39 RW 79 PMA6_WA 3A RW 7A PMA7_WA 3B RW 7B PMA0_RA 3C RW 7C PMA1_RA 3D RW 7D PMA2_RA 3E RW 7E PMA3_RA 3F RW 7F Gray fields are reserved; do not access these fields. # Access is bit specific. Name Addr (1,Hex) Access Name 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C IO_CFG 9D OUT_P1 9E 9F A0 OSC_CR0 A1 ECO_CFG A2 OSC_CR2 A3 VLT_CR A4 VLT_CMP A5 A6 A7 A8 IMO_TR A9 ILO_TR AA AB SLP_CFG AC SLP_CFG2 AD SLP_CFG3 AE AF B0 B1 B2 B3 B4 B5 B6 B7 CPU_F B8 B9 BA BB BC BD BE BF Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW # RW RW R W W RW RW RW RL Document Number: 001-12394 Rev. *F Page 13 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up to date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com Figure 4. Voltage versus CPU Frequency 5.5V 5.5V Figure 5. IMO Frequency Trim Options lid ng Va rati n e io O p eg R Vdd Voltage 3.0V 3.0V 750 kHz 3 MHz CPU Frequency Vdd Voltage SLIMO Mode = 01 SLIMO Mode = 00 SLIMO Mode = 10 24 MHz 750 kHz 3 MHz 6 MHz 12 MHz 24 MHz IMO Frequency The following table lists the units of measure that are used in this section. Table 7. Units of Measure Symbol oC dB fF Hz KB Kbit kHz kΩ MHz MΩ µA µF µH µs µV µVrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol µW mA ms mV nA ns nV Ω pA pF pp ppm ps sps s V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 001-12394 Rev. *F Page 14 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x ADC Electrical Specifications Table 8. ADC Electrical Specifications Symbol Input Input Voltage Range Input Capacitance Resolution 8-Bit Sample Rate 8 23.4375 Vss 1.3 5 10 Volts pF Bits ksps Settings 8, 9, or 10 Data Clock set to 6 MHz. Sample Rate = 0.001/(2^Resolution/Data clock) Data Clock set to 6 MHz. Sample Rate = 0.001/(2^Resolution/Data clock) For any configuration For any configuration This gives 72% of maximum code Description Min Typ Max Units Conditions 10-Bit Sample Rate 5.859 ksps DC Accuracy DNL INL Offset Error Operating Current Data Clock 2.25 -1 -2 0 15 275 +2 +2 90 350 12 LSB LSB mV µA MHz Source is chip’s internal main oscillator. See device data sheet of accuracy. Not guaranteed. See DNL 24 30 12 0 1 dB dB dB dB 5 %FSR For any resolution Ω Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution. Monotonicity Power Supply Rejection Ration PSRR (Vdd>3.0V) PSRR (2.2 < Vdd < 3.0) PSRR (2.0 < Vdd < 2.2) PSRR (Vdd < 2.0) Gain Error Input Resistance 1/(500fF*D 1/(400fF*D 1/(300fF*D ata-Clock) ata-Clock) ata-Clock) Document Number: 001-12394 Rev. *F Page 15 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Electrical Characteristics Absolute Maximum Ratings Storage Temperature (TSTG) (3) ............................................. ..............................................................-55oC to 125oC (Typical +25oC) Supply Voltage Relative to Vss (Vdd) .................................... ......................................................................................... -0.5V to +6.0V DC Input Voltage (VIO)........................................................... .........................................................................Vss - 0.5V to Vdd + 0.5V DC Voltage Applied to Tri-state (VIOZ) ................................... .........................................................................Vss - 0.5V to Vdd + 0.5V Maximum Current into any Port Pin (IMIO)............................. .................................................................................... -25mA to +50 mA Electro Static Discharge Voltage (ESD) (4) ............................ ......................................................................................................2000V Latch-up Current (LU) (5) ....................................................... ................................................................................................... 200 mA Operating Conditions Ambient Temperature (TA) ..................................................... .............................................................................................0oC to 70oC Operational Die Temperature (TJ)(6) ...................................... .............................................................................................0oC to 85oC DC Electrical Characteristics DC Chip Level Specifications Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 9. DC Chip Level Specifications Parameter Vdd IDD24 IDD12 IDD6 ISB0 ISB1 Description Supply Voltage Supply Current, IMO = 24 MHz Conditions See table titled DC POR and LVD Specifications on page 18. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 24 MHz, No USB/I2C/SPI. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 12 MHz, No USB/I2C/SPI. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 6 MHz, No USB/I2C/SPI. Vdd = 3.0V, TA = 25oC, IO regulator turned off. Vdd = 3.0V, TA = 25oC, IO regulator turned off. Min 3.0 – Typ – – Max 5.5 3.1 Units V mA Supply Current, IMO = 12 MHz – – 2.0 mA Supply Current, IMO = 6 MHz – – 1.5 mA Deep Sleep Current Standby Current with POR, LVD, and Sleep Timer – – 0.1 – – 1.5 µA µA Notes 3. Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 85oC degrade reliability. 4. Human Body Model ESD. 5. According to JESD78 standard. 6. The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 27. The user must limit the power consumption to comply with this requirement. Document Number: 001-12394 Rev. *F Page 16 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Table 10.DC Characteristics – USB Interface Symbol Rusbi Rusba Vohusb Volusb Vdi Vcm Vse Cin Iio Rps2 Rext Description USB D+ Pull Up Resistance USB D+ Pull Up Resistance Static Output High Static Output Low Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance High Z State Data Line Leakage PS/2 Pull Up Resistance External USB Series Resistor In series with each USB pin On D+ or D- line -10 3 21.78 0.2 0.8 0.8 With idle bus While receiving traffic Conditions Min 0.900 1.425 2.8 Typ 5 22.0 2.5 2.0 50 +10 7 22.22 Max 1.575 3.090 3.6 0.3 Units kΩ kΩ V V V V V pF µA kΩ Ω DC General Purpose IO Specifications Table 11 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and 0°C ≤ TA ≤ 70°C. Typical parameters apply to 5V and 3.3V at 25°C. These are for design guidance only. Table 11. 3.0V and 5.5V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 VOH10 Description Pull Up Resistor High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out High Output Voltage Port 1 Pins with LDO Enabled for 2.5V Out High Output Voltage Port 1 Pins with LDO Enabled for 2.5V Out High Output Voltage Port 1 Pins with LDO Enabled for 1.8V Out High Output Voltage Port 1 Pins with LDO Enabled for 1.8V Out Min 4 IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA Vdd - 0.2 source current in all IOs. IOH = 1 mA Vdd > 3.0, maximum of 20 mA Vdd - 0.9 source current in all IOs. IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA Vdd - 0.2 source current in all IOs. IOH = 5 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 µA, Vdd > 3.1V, maximum of 4 IOs all sourcing 5 mA IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs IOH < 10 µA, Vdd > 3.0V, maximum of 20 mA source current in all IOs IOH = 2 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs IOH < 10 µA, Vdd > 3.0V, maximum of 20 mA source current in all IOs IOH = 1 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs Vdd - 0.9 Conditions Typ 5.6 – – – Max 8 – – – Units kΩ V V V – – V 2.85 3.00 3.3 V 2.20 – – V 2.35 2.50 2.75 V 1.90 – – V 1.60 1.80 2.1 V 1.20 – – V Document Number: 001-12394 Rev. *F Page 17 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Table 11. 3.0V and 5.5V DC GPIO Specifications Symbol VOL Description Low Output Voltage Conditions IOL = 20 mA, Vdd > 3.3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). Vdd = 3.3 to 5.5. Vdd = 3.3 to 5.5. Min – Typ – Max 0.75 Units V VIL VIH VH IIL CPIN Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Pin Capacitance Package and pin dependent. Temp = 25oC. – 2.0 50 – 0.5 – – 60 0.001 1.7 0.8 200 1 5 V V mV µA pF DC POR and LVD Specifications Table 12 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 12. DC POR and LVD Specifications Symbol VPPOR VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 10b, HPOR = 1 Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b(7) VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min – – – 2.85 2.95 3.06 – – 4.62 Typ 2.82 – – 2.92 3.02 3.13 – – 4.73 Max 2.95 – – 2.99 3.09 3.20 – – 4.83 Units V – – V V V – – V Note 7. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. Document Number: 001-12394 Rev. *F Page 18 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x DC Programming Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC Programming Specifications Symbol VddIWRITE IDDP VILP VIHP IILP Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify(8) IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify(8) VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Write Endurance(9) FlashDR Flash Data Retention(10) Min 3.0 – – VIH – – – Vdd - 0.9 50,000 10 Typ – 5 – – – – – – – 20 Max – 25 VIL – 0.2 1.5 Vss + 0.75 Vdd – – Units V mA V V mA mA V V Cycles Years AC Electrical Characteristics AC Chip Level Specifications The following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. AC Chip Level Specifications Symbol FMAX FCPU F32K1 FIMO24 FIMO12 FIMO6 DCIMO TRAMP Description Maximum Operating Frequency(11) Maximum Processing Frequency(12) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 24 MHz ± 5%(13) Internal Main Oscillator Stability for 12 MHz(13) Internal Main Oscillator Stability for 6 MHz(13) Duty Cycle of IMO Supply Ramp Time Min 24 24 19 22.8 11.4 5.7 40 0 Typ – – 32 24 12 6.0 50 – Max – – 50 25.2 12.6 6.3 60 – Units MHz MHz kHz MHz MHz MHz % µs Notes 8. Driving internal pull down resistor. 9. Erase/write cycles per block. 10. Following maximum Flash write cycles at Tamb = 55C and Tj = 70C 11. Vdd = 3.0V and TJ = 85oC, digital clocking functions. 12. Vdd = 3.0V and TJ = 85oC, CPU speed. 13. Trimmed for 3.3V operation using factory trim values. Document Number: 001-12394 Rev. *F Page 19 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x Table 15.AC Characteristics – USB Data Timings Symbol Tdrate Tdjr1 Tdjr2 Tudj1 Tudj2 Tfdeop Tfeopt Tfeopr Tfst Description Full speed data rate Receiver data jitter tolerance Receiver data jitter tolerance Driver differential jitter Driver differential jitter Source jitter for differential transition Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition Conditions Average bit rate To next transition To pair transition To next transition To pair transition To SE0 transition Min 12–0.25% -18.5 -9 -3.5 -4.0 -2 160 82 Typ 12 – – – – – – – – 14 Max 12 + 0.25% 18.5 9 3.5 4.0 5 175 Units MHz ns ns ns ns ns ns ns ns Table 16.AC Characteristics – USB Driver Symbol Tr Tf TR Vcrs Description Transition rise time Transition fall time Rise/fall time matching Output signal crossover voltage 50 pF 50 pF Conditions Min 4 4 90.00 1.3 Typ – – – – Max 20 20 111.1 2.0 Units ns ns % V Document Number: 001-12394 Rev. *F Page 20 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x AC General Purpose IO Specifications Table 17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC GPIO Specifications Symbol FGPIO TRise23 TRise01 TFall Description GPIO Operating Frequency Rise Time, Strong Mode Ports 2, 3 Rise Time, Strong Mode Ports 0, 1 Fall Time, Strong Mode All Ports Conditions Normal Strong Mode, Ports 0, 1 Vdd = 3.3 to 5.5V, 10% - 90% Vdd = 3.3 to 5.5V, 10% - 90% Vdd = 3.3 to 5.5V, 10% - 90% Min 0 15 10 10 Typ – – – – Max 12 80 50 50 Units MHz ns ns ns Figure 6. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise23 TRise01 TFall AC External Clock Specifications Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC External Clock Specifications Symbol FOSCEXT – – – Frequency High Period Low Period Power Up IMO to Switch Description Min 0.750 20.6 20.6 150 Typ – – – – Max 25.2 5300 – – Units MHz ns ns µs Document Number: 001-12394 Rev. *F Page 21 of 29 [+] Feedback CY7C6431x CY7C64345, CY7C6435x AC Programming Specifications Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK1 TDSCLK2 Description Rise Time of SCLK Fall Time of SCLK Data Setup Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK, Vdd > 3.6V Data Out Delay from Falling Edge of SCLK, 3.0V