4601/603/61
CY7C64601/603/613
CY7C64601/603/613 EZ-USB FX USB Microcontroller Data Sheet
Cypress Semiconductor Corporation Document #: 38-08005 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600 Revised September 21, 2001
CY7C64601/603/613
TABLE OF CONTENTS 1.0 FEATURES ...................................................................................................................................... 3 1.1 EZ-USB FX Features ....................................................................................................................... 3 1.2 Example Applications .................................................................................................................... 4 2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 4 2.1 Microprocessor ............................................................................................................................... 5 2.2 USB SIE ........................................................................................................................................... 5 2.3 Endpoints ........................................................................................................................................ 6 2.4 Default USB Machine ...................................................................................................................... 7 2.5 IBN (In-Bulk-NAK) Interrupts ......................................................................................................... 7 2.6 Slave FIFOs ..................................................................................................................................... 7 2.7 DMA .................................................................................................................................................. 8 2.8 GPIF (General Programmable Interface) ...................................................................................... 8 3.0 PIN ASSIGNMENTS ........................................................................................................................ 9 3.1 Pin Diagrams ................................................................................................................................... 9 3.2 CY7C646xx Pin Descriptions ....................................................................................................... 13 4.0 REGISTER SUMMARY .................................................................................................................. 22 5.0 INPUT/OUTPUT PIN SPECIAL CONSIDERATION ...................................................................... 29 6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 29 7.0 OPERATING CONDITIONS ........................................................................................................... 29 8.0 DC CHARACTERISTICS ............................................................................................................... 29 9.0 AC ELECTRICAL CHARACTERISTICS ....................................................................................... 30 9.1 USB Transceiver ........................................................................................................................... 30 9.2 Program Memory Read ................................................................................................................ 30 9.3 Data Memory Read ....................................................................................................................... 31 9.4 Data Memory Write ....................................................................................................................... 32 9.5 DMA Read ...................................................................................................................................... 33 9.6 DMA Write ...................................................................................................................................... 34 9.7 Slave FIFOs—Output Enables ..................................................................................................... 34 9.8 Slave FIFOs—Synchronous Read ............................................................................................... 35 9.9 Slave FIFOs—Synchronous Write ............................................................................................... 35 9.10 Slave FIFOs—Asynchronous Read[9, 10] ....................................................................................................................................36 9.11 Slave FIFOs—Asynchronous Write[9, 10] ...................................................................................................................................36 9.12 GPIF Signals (Internally Clocked) ............................................................................................. 37 9.13 GPIF Signals (Externally Clocked) ............................................................................................ 37 10.0 ORDERING INFORMATION ........................................................................................................ 38 11.0 PACKAGE DIAGRAMS ............................................................................................................... 38 11.1 52 PQFP ....................................................................................................................................... 38 11.2 80 PQFP ....................................................................................................................................... 40 11.3 128 PQFP ..................................................................................................................................... 42
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1.0 Features
The CY7C646xx (EZ-USB FX) is Cypress Semiconductor ’s second-generation full-speed USB family. FX products offer higher performance and a higher level of integration than first-generation EZ-USB products. The FX builds on the EZ-USB feature set, including an intelligent USB core, enhanced 8051, 8-Kbyte RAM, and high-performance I/O. The CY7C646xx enhances the EZUSB family by providing faster operation and more ways to transfer data into and out of the chip at very high speed.
12 MHz XTAL ADDR(16) Data(8)
GPIF
X4 PLL
48 MHz, 4-clock cycle 8051 Core SIO SIO 3 Timers
Transceiver
Enhanced USB SIE
Data Bus (8)
4/8KB RAM
I/O Ports
USB
4 x 64 bytes FIFOs
8/16 bits
2 KB FIFO (ISO) DMA
I2C
CY7C64613-128
1.1 EZ-USB FX Features
Engine
• Single-chip integrated USB Transceiver, Serial Interface Engine (SIE), and Enhanced 8051 Microprocessor • Soft: 8051 runs from internal RAM, which is: — Downloaded via USB, or — Loaded from EEPROM • 14 Bulk/Interrupt endpoints, each with a maximum packet size of 64 bytes • 16 Isochronous endpoints, with 2 KB of buffer space (1 KB, double buffered) which may be divided among the sixteen isochronous endpoints • Integrated, industry standard 8051 with enhanced features: — Four clocks per cycle — Two UARTS — Three counter/timers — Expanded interrupt system • • • • • • • — Two data pointers 3.3-volt operation Smart Serial Interface Engine (SIE) Vectored USB interrupts Separate buffers for the SETUP and DATA portions of a CONTROL transfer Integrated I2C™ controller 48-MHz or 24-MHz 8051 operation Enhanced IO — IO port registers mapped to SFRs
— Port bits can be controlled using 8051 bit addressing instructions • Four integrated general purpose 8-bit FIFOs — 64 bytes each — Automatic conversion to and from 16-bit buses Document #: 38-08005 Rev. ** Page 3 of 42
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— FIFOs can use externally supplied clock — Easy interface to ASIC and DSP ICs — Brings glue FIFOs inside for lower system cost • DMA Controller — Moves data between slave FIFOs, memory, and ports — Very fast transfers—one clock (20.8 ns) per byte for internal transfers — Can use external RAM as additional FIFO (addressed through A/D buses) • Special Autovectors for DMA and FIFO interrupts • 400-kHz or 100-kHz I2C operation • General Programmable Interface (GPIF) — Allows direct connection to most parallel interfaces: 8- and 16-bit — Programmable Waveform Descriptors and Configuration Registers to define waveforms — Supports multiple Ready (RDY) inputs and Control (CTL) outputs • Three package options - 128-pin PQFP, 80-pin PQFP, and 52-pin PQFP
1.2
• • • • • • • • • •
Example Applications
DSL modems ATAPI interface Memory card readers Legacy conversion devices Cameras Scanners Home PNA Wireless LAN MP3 players Networking
2.0
Functional Overview
The CY7C646xx enhances the line of Cypress EZ-USB chips while maintaining code compatibility. The CY7C646xx builds on the feature set that has already made the EZ-USB family a popular choice for high-integration, high-speed USB applications: • Soft operation. Program code can be downloaded into on-chip RAM via the USB cable, eliminating the need for external program memory or mask ROM headaches. • Enhanced 8051. A speedy four clocks per cycle, plus expanded features. • Smart SIE. The USB Serial Interface Engine does much of the low-level USB overhead in logic, simplifying the 8051 code. • DMA for very fast 8-bit or 16-bit transfers. In the fastest (synchronous byte) mode, one byte can be transferred per 48-MHz clock, or every 20.8 nanoseconds. • General Programmable Interface (GPIF). A reconfigurable 8- or 16-bit parallel interface allows the CY7C646xx to perform local bus mastering, and can implement a wide variety of protocols such as ATAPI, printer parallel port, and Utopia. • Abundant endpoints and buffers. 16x64 byte buffers for bulk/interrupt/control endpoints, 2x1024 byte FIFOs for up to 16 isochronous endpoints. • Glueless memory expansion. The 8051 16-bit address bus and 8-bit data bus is available, along with strobes RD#, WR#, OE# and CS#. The buses are brought out on separate pins (not multiplexed, as in the standard 8051), saving one clock per external memory cycle. • 48-MHz or 24-MHz 8051 selectable by EEPROM configuration byte. • Five 8-bit IO ports. • Optimum 8051 IO efficiency. IO pins can be addressed as external registers (as in EZ-USB) or through 8051 SFR (Special Function Register) bits for faster operation. • Four internal FIFOs for glueless interface to ASICs, DSPs, or external logic. These FIFOs can be clocked either by an internal or external clock, and can operate either synchronously (using strobes and a clock) or asynchronously (using strobes only). The FIFOs have 8-16 and 16-8 bit conversion modes that simplify interface to external data buses. • The vectored interrupt system is expanded to accommodate the FIFO flags and DMA systems. Also, the 8051 can clear the USB (INT2) or the FIFO/DMA (INT4) interrupt request bit for the interrupt currently being serviced by writing an SFR location, saving time and code in the interrupt service routine. • 400-kHz or 100-kHz I2C bus controller speed.
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2.1 Microprocessor
The CY7C646xx uses a 12-MHz crystal for low EMI. An internal oscillator and PLL develops an internal 48-MHz clock for use by the USB Serial Interface Engine and the 8051 microprocessor. The 8051 can run at either 24 MHz or 48 MHz, controlled by a byte in the EEPROM attached to the I2C bus. The default rate (with no EEPROM connected) is 24 MHz. The internal microprocessor is an enhanced version of the industry-standard 8051. Enhancements include 4 clock per cycle operation, a second data pointer, and an enhanced interrupt system. The 8051 includes two UARTS, three counter-timers, and 256 bytes of register RAM. The EZ-USB family implements IO differently than the standard 8051, by having its IO control registers in external memory space. The CY7C646xx preserves this addressing for backward EZ-USB compatibility, and adds the ability to control IO registers using 8051 SFRs (Special Function Registers). This improves IO access time. For example, an IO pin may be toggled using one 8051 instruction, e.g., CPL (bit). The 8051 program and data memory consists of an internal 8 KB RAM. This RAM is normally downloaded via the USB cable at plug-in, followed by the 8051 starting up and executing the downloaded code. This gives the CY7C646xx family its ‘soft’ operation feature, whereby permanent memory such as ROM or Flash memory is not required. Program code updates can easily be done in the field since the code is loaded from the PC, not by physically changing or reprogramming a memory device. The 8051 program memory can also be loaded from the EEPROM connected to the I2C bus on reset for stand-alone use without the USB connected. The 128-pin version of the CY7C646xx brings out the full 8051 address and data buses, plus decoded control signals OE#, CS#, RD#, PSEN, and WR# to allow glueless connection to external memory devices. The 80- and 52-pin packages allow smaller footprints and more effective solutions for certain designs, but do not have external access to the 8051 buses.
2.2
USB SIE
The CY7C646xx uses the EZ-USB family enhanced SIE (Serial Interface Engine). This SIE has the intelligence to perform full USB enumeration, creating a default USB device with predefined endpoints and alternate settings. This enhanced SIE is essential in achieving the family’s soft operation, since it provides the mechanism to download firmware prior to the 8051 running. Once the 8051 is in control, it can use advanced features of the SIE to simplify its USB firmware. Endpoint zero SETUP data is placed in a separate 8-byte RAM space for easy access. GET_Descriptor requests are simplified by using a special Setup Data Pointer. The 8051 simply loads a descriptor address into this 16-bit register, and the SIE takes care of the remaining overhead, i.e., dividing the descriptor into packets, sending them via endpoint 0 in response to IN tokens, and providing the necessary handshakes. The 8051 can do other chores while the SIE completes this USB transfer.
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2.3 Endpoints
Type Control Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Bulk/Interrupt Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Buffer Size 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1] 0–1023[1]
Endpoint EP0-IN EP0-OUT EP1-IN EP1-OUT EP2-IN EP2-OUT EP3-IN EP3-OUT EP4-IN EP4-OUT EP5-IN EP5-OUT EP6-IN EP6-OUT EP7-IN EP7-OUT EP8-IN EP8-OUT EP9-IN EP9-OUT EP10-IN EP10-OUT EP11-IN EP11-OUT EP12-IN EP12-OUT EP13-IN EP13-OUT EP14-IN EP14-OUT EP15-IN EP15-OUT
Note: 1. 1023 FIFO bytes may be divided among all Isochronous endpoints.
The CY7C646xx has Control, Bulk, and Interrupt endpoints which each have 64-byte buffers to accommodate the maximum USB specified packet size, giving the highest USB throughput. One endpoint pair is dedicated to endpoint zero, with separate EP0-IN and EP0-OUT buffers to simplify programming. Fourteen additional 64-byte buffers may be used as Bulk or Interrupt endpoints. These endpoints may also be double-buffered by using an endpoint paring mechanism. Double buffering allows the 8051 to access a packet as another is being transmitted or received over USB. This technique is essential in high-bandwidth applications where NAKs by the USB function would reduce performance. The CY7C646xx also has sixteen Isochronous (ISO) endpoints which share 1024 bytes of double-buffered endpoint memory (2 KB total). The ISO buffer sizes are programmable within 16-byte increments. The Isochronous endpoint buffers are accessed as FIFOs.
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Endpoint data is serviced either directly by the 8051, or moved on or off-chip using the DMA system built into the CY7C646xx. Bulk data is available in 64-byte random-access buffers that can also be addressed as a FIFO using the special AutoPointer feature. Each endpoint has a unique interrupt vector. This allows ISRs (Interrupt Service Routines) automatically to be called with minimum overhead and latency, simply by including the ISR address in an interrupt jump table.
2.4
Default USB Machine
When the CY7C64613 is plugged into USB with no EEPROM attached to its I2C port (but with the SCL and SDA pull-ups installed), the intelligent SIE enumerates as a generic USB device with the following characteristics: ID bytes (hex) VID (Vendor ID) PID (Product ID) DID (Device ID) 0547 2235 0000
Default Endpoints Endpoint Type Alternate Setting 0 0 1 IN 2 IN 2 OUT 4 IN 4 OUT 6 IN 6 OUT 8 IN 8 OUT 9 IN 9 OUT 10 IN 10 OUT CTL INT BULK BULK BULK BULK BULK BULK ISO ISO ISO ISO ISO ISO 64 0 0 0 0 0 0 0 0 0 0 0 0 0 1 64 16 64 64 64 64 64 64 16 16 16 16 16 16 2 64 64 64 64 64 64 64 64 256 256 16 16 16 16 Max Packet Size (bytes)
Powering up with default USB characteristics allows code to be written without initial consideration of the enumeration code that establishes the default USB device, speeding the learning process.
2.5
IBN (In-Bulk-NAK) Interrupts
The CY7C646xx has an interrupt that indicates that an IN token has been received by an endpoint, and the SIE has NAK’d the transfer due to no data being available in the endpoint buffer. Interrupt request bits are provided for endpoints EP1N through EP7IN, and a previously reserved vector is added to the USB vectored interrupts.
2.6
Slave FIFOs
Many high-bandwidth USB designs use a FIFO between the USB interface chip and external logic to match data rates, or to smooth the USB data delivery (which, being packet oriented, occurs in bursts). The CY7C646xx moves this glue logic into the part by providing four 64-byte internal slave FIFOs. The FIFOs also provide two important interface functions, external clocking and bus width conversion. Using external clocking, external logic (such as a DSP or ASIC) can clock data into or out of the slave FIFOs under control of its own clock, rather than synchronizing with the clock supplied by the CY7C646xx (24 or 48 MHz). The FIFOs can be controlled Document #: 38-08005 Rev. ** Page 7 of 42
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either synchronously (using strobe signals and a clock) or asynchronously (using strobe signals only). The slave FIFO data is available as two 8-bit buses, which may be used simultaneously to operate as a single 16-bit data bus. The 16-bit connection, along with fast double-byte mode, combine to give fast conversion between 8 and 16 bit buses. A flexible set of FIFO flags (full, empty, and programmable) provide FIFO flow control.
2.7
DMA
With many sources and destinations for USB data, such as endpoint buffers, slave FIFOs, and internal/external RAM buffers, it is important to move blocks of data between them quickly. Using internal DMA, the 8051 sets up source, destination, and transfer length registers, and then initiates a DMA transfer. The maximum DMA transfer rate occurs between internal resources, such as endpoint buffers and slave FIFOs. This maximum rate is one byte per 48-MHz clock, or 48 Mbytes per second.
2.8
GPIF (General Programmable Interface)
The GPIF is a flexible 8 or 16-bit parallel interface driven by a user-programmable set of vectors that operate similarly to a finite state machine. It allows the CY7C646xx to perform local bus mastering, and can implement a wide variety of protocols such as ATAPI, printer parallel port, and Utopia. The GPIF has six programmable Control Outputs (CTL), six Address Outputs (ADR), and six general purpose Ready Inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, or determines what state a ready input (or multiple inputs) must be before proceeding. A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the CY7C646xx and the external design.
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3.0
3.1
Pin Assignments
Pin Diagrams
PC2/INT0#
PC3/INT1#
PC0/RxD0
PC1/TxD0
PC6/W R#
AINFLAG 41
PC7/RD#
PC4/T0
PC5/T1
GND
GND
AOE
52
51
50
49
48
47
46
45
44
43
VCC SCL SDA WAKEUP# AVCC XIN XOUT AGND RESERVED PA4/FWR# PA5/FRD# CLKOUT GND
1 2 3 4 5 6 7 8 9 10 11 12 13
42
40 39 38 37 36 35
VCC
GND XCLK AOUTFLAG PB7/T2OUT/AFI[7] PB6/INT6/AFI[6] PB5/INT5#/AFI[5] PB4/INT4/AFI[4] PB3/TxD2/AFI[3] PB2/RxD2/AFI[2] PB1/T2EX/AFI[1] PB0/T2/AFI[0] RESET VCC
52 PQFP 10 x 10 mm
34 33 32 31 30 29 28 27
14
15
16
17
18
25 USBD+
19
20
21
22
23
XCLKSEL
DISCO N#
RESERVED
USBD-
VCC
G ND
24
RESERVED
RESERVED
RESERVED
RESERVED
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RESERVED
G ND
26
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PC3/INT1#/RDY3
PC0/RXD0/RDY0
PC1/TXD0/RDY1
PC6/WR#/CTL4
CTL0/AINFLAG
PC7/RD#/CTL5
PC5/T1/CTL3
PC4/T0/CTL1
RDY1/BSEL
RDY0/ASEL
RDY2/AO E
PC2/INT0#
G ND
GND
80
Vcc SCL SDA WAKEUP# AVCC XIN XOUT AGND RESERVED GND PA0/T0OUT PA1/T1OUT PA2/OE# PA3/CS# PA4/FWR#/RDY4/SLWR PA5/FRD#/RDY5/SLRD PA6/RXD0OUT PA7/RXD1OUT CLKOUT GND
1
61
Vcc
NC
NC
NC
NC
NC
60
GND XCLK CTL2/AOUTFLAG CTL1/BINFLAG NC NC PB7/T2OUT/D7/GDA7/AFI7 PB6/INT6/D6/GDA6/AFI6
80 PQFP 14 x 14 mm
PB5/INT5#/D5/GDA5/AFI5 PB4/INT4/D4/GDA4/AFI4 PB3/TXD1/D3/GDA3/AFI3 PB2/RXD1/D2/GDA2/AFI2 PB1/T2EX/D1/GDA1/AFI1 PB0/T2/D0/GDA0/AFI0 NC NC NC GND RESET#
20
41
Vcc
21
USBD-
Vcc
GND
RDY3/BO E
DISCO N#
PD0/G DB0/BFI0
PD3/G DB3/BFI3
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PD7/G DB7/BFI7
PD2/G DB2/BFI2
PD6/GDB7/BFI6
PD1/G DB1/BFI1
PD5/G DB5/BFI5
PD4/G DB4/BFI4
RDY4/SLWR
RESERVED
XCLKSEL
RESERVED
RDY5/SLRD
USBD+
GND
40
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PB 7/T2OU T/AFI[7]
P B5/IN T5#/AFI[5]
P E3/AOUTE MTY
P E4/BOUTEMTY
P B1/T2E X/A FI[1]
P B2/RxD 1/AFI[2]
P E0/BOUTFLAG
P B3/TxD1/A FI[3]
P B6/IN T6/A FI[6]
P B4/IN T4/A FI[4]
P E2/BIN FULL
P B0/T2/AFI[0]
P E1/AIN FULL
R ESE RVE D
R ESE RVE D
R ESE RVE D
R ESE RVE D
R ESE RVE D
R ESE RVE D
AOU TFLAG
A INFLAG
B INFLAG
R ESE T+
U SBD + 66
102
101
100
78
77
76
74
73
72
71
70
69
68
67
75
99
98
96
95
94
93
92
91
90
89
88
87
85
84
83
82
81
80
79
97
86
65
U SBD-
X CLK
A SEL
GN D
GN D
GN D
GN D
GN D
V CC
V CC
VC C
P E7
P E6
P E5
BSEL AOE A0 A1 A2 A3 VCC PC0/RxD0 PC1/TxD0 PC2/INT0# PC3/INT1# A4 A5 A6 A7 A8 GND A9 A10 A11 PC4/T0 PC5/T1 PC6/WR# PC7/RD# A12 A13
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
64 63 62 61 60 59 58 57 56 55 54 53
PD7/BFI[7] PD6/BFI[6] GND PD5/BFI[5] PD4/BFI[4] PD3/BFI[3] PD2/BFI[2] PD1/BFI[1] PD0/BFI[0] VCC RESERVED RESERVED GND EA RESERVED RESERVED DISCON# GND SLRD SLWR BOE No Connect No Connect BKPT GND RESERVED
128 PQFP 14 x 20 mm
52 51 50 49 48 47 46 45 44 43 42 41 40 39
25
26
27
29
30
31
32
33
34
35
36
10
11
12
13
14
15
16
18
19
20
21
22
23
24
37 RE SER VED
28
N o Connect ADR5
PA0/T0out
XOU T
PA 4/FW R #
W A KEU P#
P A5/FRD #
PA1/T1out
PA6/R XD0out
PA7/RX D1out
P A2/OE#
PA3/C S#
C LKOU T
D0
D1
D2
D3
D4
D5
D6
SC L
A14
A15
D7
PSEN #
3.2
128 18 21 48
CY7C646xx Pin Descriptions
80 5 8 28 52 5 8 18 Name AVCC AGND DISCON# Type Power Power O/Z Default N/A N/A H Description Analog VCC. This signal provides power to the analog section of the chip. Analog Ground. Connect to ground with as short a path as possible. Disconnect. This pin can drive HIGH, LOW, or float. DISCON# pin floats when the register bit USBCS.2 is LOW, and drives when it is HIGH. The drive level of the DISCON# pin is the invert of register bit USBCS.3. The DISCON# pin is normally connected to the USB D+ line through a 1500Ω resistor. The CY7C646xx signals a USB connection by setting USBCS.3=0 (drive 3.3V) and USBCS.2=1 (output enable). The CY7C646xx signals a USB disconnect by setting USBCS.2=0 which floats the pin and disconnects the 1500Ω resistor from D+.
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RES ERV ED
XCLKS EL
GND
GND
XIN
GND
AGND
GND
V CC
AV CC
V CC
VC C
SDA
38
17
1
2
3
4
5
6
7
8
9
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3.2
128 65 66 105 106 107 108 114 115 116 117 118 120 121 122 127 128 1 2 8 9 10 11 13 14 15 16 33
CY7C646xx Pin Descriptions (continued)
80 38 39 52 24 25 Name USBD– USBD+ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 PSEN# Type I/O/Z I/O/Z Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Output Default Z Z L L L L L L L L L L L L L L L L Z Z Z Z Z Z Z Z H Program Store Enable. This active-LOW signal indicates an 8051 code fetch from external memory. It is active for program memory fetches from 0x1B40-0xFFFF when the EA pin is LOW, or from 0x0000-0xFFFF when the EA pin is HIGH. Breakpoint. This pin goes active (HIGH) when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the USBBAV register (BPEN=1). If the BPPULSE bit in the USBBAV register is HIGH, this signal pulses HIGH for eight 24-/48MHz clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears the BREAK bit (by writing 1 to it) in the USBBAV register. Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC through a 10K resistor, and to GND through a 1-µF capacitor. Hysteresis input. External Access. This pin determines where the 8051 fetches code between addresses 0x0000 and 0x1B3F. If EA=0 the 8051 fetches this code from its internal RAM. IF EA=1 the 8051 fetches this code from external memory. 8051 Data Bus. This bidirectional bus is high-impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is also used for DMA transfers that use the RD#/FRD#, WR#,FWR# pins as strobes. The data bus is active only for external bus accesses, and is driven LOW in suspend. Description USB D– Signal. Connect to the USB D– signal through a 24Ω resistor. USB D+ Signal. Connect to the USB D+ pin through a 24Ω resistor. 8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address. During DMA transfers that use the RD# and WR# strobes, the address bus contains the incrementing DMA source or destination address for data transferred over D[7..0].
41
BKPT
Output
L
69
42
28
RESET#
Input
N/A
51
EA
Input
N/A
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3.2
128 19
CY7C646xx Pin Descriptions (continued)
80 6 52 6 Name XIN Type Input Default N/A Description Crystal Input. Connect this signal to a 12-MHz series-resonant, fundamental mode crystal and 22–33 pF capacitor to GND. Also connect a 1-MΩ resistor between XIN and XOUT. Crystal Output. Connect this signal to a 12-MHz series-resonant, fundamental mode crystal and 22–33 pF capacitor to GND. Also connect a 1-MΩ resistor between XIN and XOUT. 24- or 48-MHz clock, phase locked to the 12-MHz input clock. Output frequency is set by an external EEPROM bit (Config0.2). If no EEPROM is connected to the I2C port (but the required pull-up resistors are present), the 8051 defaults to 24-MHz operation. The 8051 may three-state this output by setting CPUCS.1=1. The CLKOUT pin may be inverted by setting the boot EEPROM bit CONFIG0.1=1.
20
7
7
XOUT
Output
N/A
34
19
12
CLKOUT
O/Z
24 MHz
Port A
25 11 PA0 or T0OUT I/O/Z I (PA0) Multiplexed pin whose function is selected by two bits: PORTACFG.0 and IFCONFIG.3. PA0 is a bidirectional IO port pin. T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows. Multiplexed pin whose function is selected by two bits: PORTACFG.1 and IFCONFIG.3. PA1 is a bidirectional IO port pin. T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows. Multiplexed pin whose function is selected by two bits: PORTACFG.2 and IFCONFIG.3. PA2 is a bidirectional IO port pin. OE# is an active-LOW output enable for external memory. If the OE# pin is used, it should be externally pulled up to VCC to ensure that the write strobe is inactive (high) at power-on. Multiplexed pin whose function is selected by the PORTACFG.3 bit. PA3 is a bidirectional I/O port pin. CS# is an active-LOW chip select for external memory. If the CS# pin is used, it should be externally pulled up to VCC to ensure that the write strobe is inactive (HIGH) at power-on. Multiplexed pin whose function is selected by the following bits: PORTACFG.4, PORTACF2.4, and IFCONFIG[1..0]. PA4 is a bidirectional I/O port pin. FWR# is the write strobe output for an external FIFO connected to the data bus D[7..0]. If the FWR# pin is used, it should be externally pulled up to VCC to ensure that the write strobe is inactive at poweron. RDY4 is a GPIF input signal. SLWR is the write strobe input for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0].
26
12
PA1 or T1OUT
I/O/Z
I (PA1)
27
13
PA2 or OE# or
I/O/Z
I (PA2)
28
14
PA3 or CS#
I/O/Z
I (PA3)
29
15
10
PA4 or FWR# or RDY4 or SLWR
I/O/Z
I (PA4)
Document #: 38-08005 Rev. **
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CY7C64601/603/613
3.2
128 30
CY7C646xx Pin Descriptions (continued)
80 16 52 11 Name PA5 or FRD# or RDY5 or SLRD Type I/O/Z Default I (PA5) Description Multiplexed pin whose function is selected by the following bits: PORTACFG.5, PORTACF2.5, and IFCONFIG[1..0]. PA5 is a bidirectional I/O port pin. FRD# is the write strobe output for an external FIFO connected to the data bus D[7..0]. If the FRD# pin is used, it should be externally pulled up to VCC to ensure that the read strobe is inactive at poweron. RDY5 is a GPIF input signal. SLRD is the read strobe input for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0]. Multiplexed pin whose function is selected by the PORTACFG.6 bit. PA6 is a bidirectional I/O port pin. RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1. Multiplexed pin whose function is selected by the PORTACFG.7 bit. PA7 is a bidirectional I/O port pin. RXD1OUT is an active-HIGH output from 8051 UART1. When RXD1OUT is selected and UART1 is in mode 0, this pin provides the output data for UART1 only when it is in sync mode. In modes 1, 2, and 3, this pin is HIGH.
31
17
PA6 or RXD0OUT
I/O/Z
I (PA6)
32
18
PA7 or RXD1OUT
I/O/Z
I (PA7)
Port B
The following descriptions apply to the PORT B pins: D[7..0] is the 8051 data bus. This bus is optionally available on PORT B pins to provide access to the 8051 data bus in smaller EZUSB II packages that do not bring out the 8051 address and data buses. GDA[7..0] is the GPIF A data bus. AFI[7..0] is the bidirectional A-FIFO data bus. 79 47 29 PB0 or T2 or D[0] or GDA[0] or AFI [0] I/O/Z I (PB0) Multiplexed pin whose function is selected by the following bits: PORTBCFG.0 and IFCONFIG[1..0]. PB0 is a bidirectional I/O port pin. T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does not use this pin. AFI [0] is the bidirectional A-FIFO data bus. Multiplexed pin whose function is selected by the following bits: PORTBCFG.1 and IFCONFIG[1..0]. PB1 is a bidirectional I/O port pin. T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON. AFI [1] is the bidirectional A-FIFO data bus. Multiplexed pin whose function is selected by the following bits: PORTBCFG.2 and IFCONFIG[1..0]. PB2 is a bidirectional I/O port pin. RXD1is an active-HIGH input signal for 8051 UART1, which provides data to the UART in all modes. AFI [2] is the bidirectional A-FIFO data bus.
80
48
30
PB1 or T2EX or D[1] or GDA[1] or AFI [1]
I/O/Z
I (PB1)
81
49
31
PB2 or RXD1 or D[2] or GDA[2] or AFI [2]
I/O/Z
I (PB2)
Document #: 38-08005 Rev. **
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3.2
128 82
CY7C646xx Pin Descriptions (continued)
80 50 52 32 Name PB3 or TXD1 or D[3] or GDA[3] or AFI [3] Type I/O/Z Default I (PB3) Description Multiplexed pin whose function is selected by the following bits: PORTBCFG.3 and IFCONFIG[1..0]. PB3 is a bidirectional I/O port pin. TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. AFI [3] is the bidirectional A-FIFO data bus. Multiplexed pin whose function is selected by the following bits: PORTBCFG.4 and IFCONFIG[1..0]. PB4 is a bidirectional I/O port pin. INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is edge-sensitive, active HIGH. AFI [4] is the bidirectional A-FIFO data bus. Multiplexed pin whose function is selected by the following bits: PORTBCFG.5 and IFCONFIG[1..0]. PB5 is a bidirectional I/O port pin. INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is edge-sensitive, active LOW. AFI [5] is the bidirectional A-FIFO data bus. Multiplexed pin whose function is selected by the following bits: PORTBCFG.6 and IFCONFIG[1..0]. PB6 is a bidirectional I/O port pin. INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin is edge-sensitive, active HIGH. AFI [6] is the bidirectional A-FIFO data bus. Multiplexed pin whose function is selected by the following bits: PORTBCFG.7 and IFCONFIG[1..0]. PB7 is a bidirectional I/O port pin. T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows. AFI [7] is the bidirectional A-FIFO data bus.
83
51
33
PB4 or INT4 or D[4] or GDA[4] or AFI [4] PB5 or INT5# or D[5] or GDA[5] or AFI [5] PB6 or INT6 or D[6] or GDA[6] or AFI [6] PB7 or T2OUT or D[7] or GDA[7] or AFI [7]
I/O/Z
I (PB4)
84
52
34
I/O/Z
I (PB5)
85
53
35
I/O/Z
I (PB6)
86
54
36
I/O/Z
I (PB7)
Port C
110 68 43 PC0 or RXD0 or RDY0 I/O/Z I (PC0) Multiplexed pin whose function is selected by the PORTCCFG.0 and PORTCGPIF.0 bits. PC0 is a bidirectional I/O port pin. RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes. RDY0 is a GPIF input signal. Multiplexed pin whose function is selected by the PORTCCFG.1 and PORTCGPIF.1 bits. PC1 is a bidirectional I/O port pin. TXD0 is the active-HIGH TXD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode. RDY1 is a GPIF input signal. Multiplexed pin whose function is selected by the PORTCCFG.2 bit. PC2 is a bidirectional I/O port pin. INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0). Multiplexed pin whose function is selected by the: PORTCCFG.3 and PORTCGPIF.3 bits. PC3 is a bidirectional I/O port pin. INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). RDY3 is a GPIF input signal.
111
69
44
PC1 or TXD0 or RDY1
I/O/Z
I (PC1)
112
70
45
PC2 or INT0#
I/O/Z
I (PC2)
113
71
46
PC3 or INT1# or RDY3
I/O/Z
I (PC3)
Document #: 38-08005 Rev. **
Page 15 of 42
CY7C64601/603/613
3.2
128 123
CY7C646xx Pin Descriptions (continued)
80 73 52 48 Name PC4 or T0 or CTL1 Type I/O/Z Default I (PC4) Description Multiplexed pin whose function is selected by the PORTCCFG.4 and PORTCGPIF.4 bits. PC4 is a bidirectional I/O port pin. T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit. CTL1 is a GPIF output signal. Multiplexed pin whose function is selected by the PORTCCFG.5 and PORTCGPIF.5 bits. PC5 is a bidirectional I/O port pin. T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit. CTL3 is a GPIF output signal. Multiplexed pin whose function is selected by the PORTCCFG.6 and PORTCGPIF.6 bits. PC6 is a bidirectional I/O port pin. WR# is the active-LOW write strobe output for external memory. If the WR# signal is used, it should be externally pulled up to VCC to ensure that the write strobe is inactive at power-on. CTL4 is a GPIF output signal. Multiplexed pin whose function is selected by the PORTCCFG.7 and PORTCGPIF.7 bits. PC7 is a bidirectional I/O port pin. RD# is the active-LOW read strobe output for external memory. If the RD# signal is used, it should be externally pulled up to VCC to ensure that the write strobe is inactive at power-on. CTL5 is a GPIF output signal.
124
74
49
PC5 or T1 or CTL3
I/O/Z
I (PC5)
125
75
50
PC6 or WR# or CTL4
I/O/Z
I (PC6)
126
76
51
PC7 or RD# or CTL5
I/O/Z
I (PC7)
Port D
Port D is multiplexed between three sources: PD0–PD7 are bidirectional I/O port pins. GDB[7..0] is the GPIF B data bus. BFI[7..0] is the bidirectional B-FIFO data bus. 56 30 PD0 or GDB[0] or BFI [0] PD1 or GDB[1] or BFI [1] PD2 or GDB[2] or BFI [2] PD3 or GDB[3] or BFI [3] PD4 or GDB[4] or BFI [4] PD5 or GDB[5] or BFI [5] PD6 or GDB[6] or BFI [6] I/O/Z I (PD0) I (PD1) I (PD2) I (PD3) I (PD4) I (PD5) I (PD6) Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [0] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [1] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [2] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [3] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [4] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [5] is the bidirectional B-FIFO data bus. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [6] is the bidirectional B-FIFO data bus. Page 16 of 42
57
31
I/O/Z
58
32
I/O/Z
59
33
I/O/Z
60
34
I/O/Z
61
35
I/O/Z
63
36
I/O/Z
Document #: 38-08005 Rev. **
CY7C64601/603/613
3.2
128 64
CY7C646xx Pin Descriptions (continued)
80 37 52 Name PD7 or GDB[7] or BFI [7] Type I/O/Z Default I (PD7) Description Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. BFI [7] is the bidirectional B-FIFO data bus.
Port E
88 PE0 or ADR0 or BOUTFLAG I/O/Z I (PE0) Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE0 is a bidirectional I/O port pin. ADR0 is a GPIF address output pin. BOUTFLAG is the B-OUT FIFO flag output, which indicates a programmable level of FIFO fullness. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE1 is a bidirectional I/O port pin. ADR1 is a GPIF address output pin. AINFULL is the A-IN FIFO flag output, which indicates FIFO full. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE2 is a bidirectional I/O port pin. ADR2 is a GPIF address output pin. BINFULL is the B-IN FIFO flag output, which indicates FIFO full. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE3 is a bidirectional I/O port pin. ADR3 is a GPIF address output pin. AOUTEMTY is the A-OUT FIFO flag output, which indicates FIFO empty. Multiplexed pin whose function is selected by the IFCONFIG[2..0] bits. PE4 is a bidirectional I/O port pin. ADR4 is a GPIF address output pin. BOUTEMTY is the B-OUT FIFO flag output, which indicates FIFO empty. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. PE5 is a bidirectional I/O port pin. CTL3 is a GPIF output signal. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. PE6 is a bidirectional I/O port pin. CTL4 is a GPIF output signal. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. PE7 is a bidirectional I/O port pin. CTL5 is a GPIF output signal. ADR5 is a GPIF address output pin. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY0 is a GPIF input signal. ASEL is the select input for the A-IN and A-OUT FIFOs. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY1 is a GPIF input signal. BSEL is the select input for the B-IN and B-OUT FIFOs.
89
PE1 or ADR1 or AINFULL
I/O/Z
I (PE1)
90
PE2 or ADR2 or BINFULL
I/O/Z
I (PE2)
91
PE3 or ADR3 or AOUTEMTY
I/O/Z
I (PE3)
92
PE4 or ADR4 or BOUTEMTY
I/O/Z
I (PE4)
93
PE5 or CTL3
I/O/Z
I (PE5)
94
PE6 or CTL4
I/O/Z
I (PE6)
95
PE7 or CTL5
I/O/Z
I (PE7)
24 102 63
ADR5 RDY0 or ASEL
O Input
X X
103
64
RDY1 or BSEL
Input
X
Document #: 38-08005 Rev. **
Page 17 of 42
CY7C64601/603/613
3.2
128 104
CY7C646xx Pin Descriptions (continued)
80 65 52 42 Name RDY2 or AOE Type Input Default X Description Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY2 is a GPIF input signal. AOE is the output enable input for the A-OUT FIFO. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY3 is a GPIF input signal. BOE is the output enable input for the B-OUT FIFO. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY4 is a GPIF input signal. SLWR is the input-only write strobe for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0]. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. RDY5 is a GPIF input signal. SLRD is the input-only read strobe for the slave FIFOs connected to AFI[7..0] and/or BFI[7..0]. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. AINFLAG is the A-IN FIFO flag output which indicates a programmable level of FIFO fullness. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL1 is a GPIF control output. BINFLAG is the B-IN FIFO flag output which indicates a programmable level of FIFO fullness. Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL2 is a GPIF control output. AOUTFLAG is the A-OUT FIFO flag output which indicates a programmable level of FIFO fullness. External clock input, used for synchronously clocking data into the slave FIFOs. XCLK also serves as a timing reference for all slave FIFO control signals and GPIF. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Leave open. Reserved. Connect to Ground. USB Wakeup. If the 8051 is in suspend, a HIGH-to-LOW edge on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP# LOW inhibits the EZUSB chip from suspending. I2C Clock. Connect to VCC with a 1K resistor, even if no I2C peripheral is attached. Page 18 of 42
44
25
RDY3 or BOE
Input
X
45
26
RDY4 or SLWR
Input
X
46
27
RDY5 or SLRD
Input
X
101
62
41
CTL0 or AINFLAG
Output
X
96
57
CTL1 or BINFLAG
Output
X
97
58
37
CTL2 or AOUTFLAG
Output
X
98
59
38
XCLK
Input
N/A
53 54 70 71 73 74 76 77 50 49 7 4
22 23
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Input
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
20 19 4
Reserved Reserved WAKEUP#
5
2
2
SCL
OD
Z
Document #: 38-08005 Rev. **
CY7C64601/603/613
3.2
128 6 38 39 37 22 4 17 36 55 68 75 100 109 3 12 23 35 40 47 52 62 67 72 78 87 99 119 42 43 60 72 79 44 45 46 55 56 66 67 77 78 39 47 40 43 26 29 21 10 20 13 80 52 61 40 41 27 21 14
CY7C646xx Pin Descriptions (continued)
80 3 23 24 22 9 1 52 3 16 17 15 9 1 Name SDA XCLKSEL Reserved Reserved Reserved VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC Type OD Input Rsrvd Rsrvd Rsrvd Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Default Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Description I2C Data. Connect to VCC with a 1K resistor, even if no I2C peripheral is attached. HIGH: Use XCLK pin for GPIF and slave FIFOs. LOW: Use internal 48-MHz clock for GPIF and slave FIFOs. Reserved. Connect to Ground. Reserved. Connect to Ground. Reserved. Connect to Ground. VCC. Connect to 3.3 V power source. VCC. Connect to 3.3 V power source. VCC. Connect to 3.3 V power source. VCC. Connect to 3.3 V power source. VCC. Connect to 3.3 V power source. VCC. Connect to 3.3 V power source. VCC. Connect to 3.3 V power source. VCC. Connect to 3.3 V power source. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. No-connect. This pin must be left open. Page 19 of 42
Document #: 38-08005 Rev. **
CY7C64601/603/613
t
4.0
Addr
Register Summary
Name FIFO A-IN Description D7 D6 D5 D4 D3 D2 D1 D0
7800 AINDATA 7801 AINBC 7802 AINPF 7803 AINPFPIN 7804 (reserved) FIFO B-IN 7805 BINDATA 7806 BINBC 7807 BINPF 7808 BINPFPIN 7809 (reserved)
Read Data from FIFO A Input FIFO A Byte Count FIFO A-IN Prog. Flag (internal bit) FIFO A-IN Prog. Flag (external pin)
D7 0 LTGT LTGT
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
Read Data from FIFO B Input FIFO B Byte Count FIFO B-IN Prog. Flag (internal bit) FIFO B-IN Prog. Flag (external pin)
D7 0 LTGT LTGT
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
FIFO A/B-IN Control 780A ABINTF 780B ABINIE 780C ABINIRQ 780D (reserved) FIFO A-OUT 780E AOUTDATA 780F AOUTBC 7810 AOUTPF 7811 AOUTPFPIN Load Output FIFO A Output FIFO A Byte Count FIFO A-OUT Prog. Flag (internal bit) FIFO A-OUT Programmable Flag (external pin) D7 0 LTGT LTGT D6 D6 D6 D6 D5 D5 D5 D5 D4 D4 D4 D4 D3 D3 D3 D3 D2 D2 D2 D2 D1 D1 D1 D1 D0 D0 D0 D0 Input FIFOs Toggle control and flags Input FIFO Interrupt Enables Input FIFO Interrupt Requests INTOG 0 0 INSEL 0 0 AINPF
AINPFIE AINPFIR
AINEF
AINEFIE AINEFIR
AINFF
AINFFIE AINFFIR
BINPF
BINPFIE BINPFIR
BINEF
BINEFIE BINEFIR
BINFF
BINFFIE BINFFIR
7812 (reserved) FIFO B-OUT 7813 BOUTDATA 7814 BOUTBC 7815 BOUTPF 7816 BOUTPFPIN 7817 (reserved) FIFO A/B OUT Control 7818 ABOUTTF 7819 ABOUTIE 781A ABOUTIRQ 781B (reserved) FIFO A/B Global Control 781C ABSETUP FIFO Setup 0 0 ASYNC DBLIN 0
OUTDLY
Load Output FIFO B Output FIFO B Byte Count FIFO B-OUT Prog. (internal bit) FIFO B-OUT Prog. Flag (external pin)
D7 0 LTGT LTGT
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
Output FIFOs Toggle control and flags Output FIFO Interrupt Enables Output FIFO Interrupt Requests
OUTTOG
OUTSEL
AOUTPF AOUTPFIE AOUTPFIR
AOUTEF AOUTEFIE AOUTEFIR
AOUTFF AOUTFFIE AOUTFFIR
BOUTPF BOUTPFIE BOUTPFIR
BOUTEF BOUTEFIE BOUTEFIR
BOUTFF BOUTFFIE BOUTFFIR
0 0
0 0
0
DBLOUT
Document #: 38-08005 Rev. **
Page 20 of 42
CY7C64601/603/613
4.0
Addr
Register Summary (continued)
Name Description FIFO Control Signals Polarity Write (data=x) to reset all flags D7 0 * D6 0 * D5 BOE * D4 AOE * D3 SLRD * D2 SLWR * D1 ASEL * D0 BSEL *
781D ABPOLAR 781E ABFLUSH 781F-7823 (reserved) 7824 WFSELECT 7825 IDLE_CS 7826 IDLECTLOUT 7827 CTLOUTCFG 7828-7829 (reserved) 782A GPIFADRL 782B (reserved) 782C AINTC 782D AOUTTC 782E ATRIG 782F (reserved) 7830 BINTC 7831 BOUTTC 7832 BTRIG 7833 (reserved) 7834 SGLDATH
Waveform Selector GPIF IDLE State control GPIF IDLE CTL states GPIF CTL Drive mode
SINGLEWR DONE IOE3 TRICTL 0 IOE2 0
SINGLERD 0 IOE1/ CTL5 CTL5 0 IOE0/ CTL4 CTL4 0
FIFOWR 0 CTL2 CTL2 0
FIFORD
IDLEDRV
CTL3 CTL3
CTL1 CTL1
CTL0 CTL0
GPIF Address
*
*
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
FIFO A In Transfer Count FIFO A Out Transfer Count Trigger a FIFO A RD/WR
FITC FITC * * * *
Transfer Count Transfer Count * * * *
FIFO B In Transfer Count FIFO B Out Transfer Count Trigger a FIFO B RD/WR
FITC FITC * * * *
Transfer Count Transfer Count * * * *
GPIF Data High
D15 D7 D7
D14 D6 D6
D13 D5 D5
D12 D4 D4
D11 D3 D3
D10 D2 D2
D9 D1 D1
D8 D0 D0
7835 SGLDATLTRIG GPIF Data Low and Trigger 7836 SGLDATLNTRIG 7837(reserved) 7838 READY 7839 ABORT 783A (reserved) 783B GENIE 783C GENIRQ 783D-7840 (reserved) IO Ports D, E 7841 OUTD 7842 PINSD 7843 OED 7844 (reserved) 7845 OUTE 7846 PINSE 7847 OEE 7848 (reserved) 7849 PORTSETUP 784A IFCONFIG 784B PORTACF2 Timer0 Clock source, Port-to-SFR mapping Select 8/16 bit data bus, configure buses (IF) Port A Configuration #2 Output Port E Input Port E pins Port E Output Enable Output Port D Input Port D pins Port D Output Enable GPIF/DMA Interrupt Enable GPIF/DMA Interrupt Request GPIF Ready flags Abort current GPIF cycle GPIF Data Low and No Trigger
INTRDY *
SAS *
RDY5 *
RDY4 *
RDY3 *
RDY2 *
RDY1 *
RDY0 *
0 0
0 0
0 0
0 0
0 0
DMADN DMADN
GPWR GPWR
GPDONE GPDONE
OUTD7 PIND7 0ED7
OUTD6 PIND6 0ED6
OUTD5 PIND5 0ED5
OUTD4 PIND4 0ED4
OUTD3 PIND3 0ED3
OUTD2 PIND2 0ED2
OUTD1 PIND1 0ED1
OUTD0 PIND0 0ED0
OUTE7 PINE7 OEE7
OUTE6 PINE6 OEE6
OUTE5 PINE5 OEE5
OUTE4 PINE4 OEE4
OUTE3 PINE3 OEE3
OUTE2 PINE2 OEE2
OUTE1 PINE1 OEE1
OUTE0 PINE0 OEE0
0 52ONE 0
0 0 0
0 0 SLRD
0 0 SLWR
0 GSTATE 0
0 BUS16 0
T0CLK IF1 0
SFRPORT
IF0 0
Document #: 38-08005 Rev. **
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4.0
Addr
Register Summary (continued)
Name Description Port C Configuration #2 D7 CTL5 D6 CTL4 D5 CTL3 D4 CTL1 D3 RDY3 D2 0 D1 RDY1 D0 RDY0
784C PORTCCF2 784D-784E (reserved) DMA Control 784F DMASRCH 7850 DMASRCL 7851 DMADESTH 7852 DMADESTL 7853 (reserved) 7854 DMALEN 7855 DMAGO 7856 (reserved) 7857 DMABURST 7858 DMAEXTFIFO 7859 - 785C (reserved) 785D INT4IVEC 785E INT4SETUP 785F-78FF (reserved) 7900- WFDESC 797F 7980-7B3F (reserved)
DMA Source H DMA Source L DMA Destination H DMA Destination L
A15 A7 A15 A7
A14 A6 A14 A6
A13 A5 A13 A5
A12 A4 A12 A4
A11 A3 A11 A3
A10 A2 A10 A2
A9 A1 A9 A1
A8 A0 A8 A0
DMA Transfer Length Start DMA Transfer
D7 DONE
D6 *
D5 *
D4 *
D3 *
D2 *
D1 *
D0 *
DMA Burst control Dummy data reg for using RAM as external FIFO
* n/a
* n/a
* n/a
DSTR2 n/a
DSTR1 n/a
DSTR0 n/a
RB n/a
WB n/a
Interrupt 4 Vector Interrupt 4 Set-up
0 0
1 0
I4V3 0
I4V2 0
I4V1 0
I4V0
INT4SFC
0
INTERNAL
0 AV4EN
GPIF Waveform Descriptors
Endpoint 0–7 Data Buffers 7B40 OUT7BUF 7B80 IN7BUF 7BC0 OUT6BUF 7C00 IN6BUF 7C40 OUT5BUF 7C80 IN5BUF 7CC0 OUT4BUF 7D00 IN4BUF 7D40 OUT3BUF 7D80 IN3BUF 7DC0 OUT2BUF 7E00 IN2BUF 7E40 OUT1BUF 7E80 IN1BUF 7EC0 OUT0BUF 7F00 IN0BUF 7F40-7F5F (reserved) Isochronous Data 7F60 OUT8DATA 7F61 OUT9DATA 7F62 OUT10DATA 7F63 OUT11DATA 7F64 OUT12DATA Endpoint 8 OUT Data Endpoint 9 OUT Data Endpoint 10 OUT Data Endpoint 11 OUT Data Endpoint 12 OUT Data d7 d7 d7 d7 d7 d6 d6 d6 d6 d6 d5 d5 d5 d5 d5 d4 d4 d4 d4 d4 d3 d3 d3 d3 d3 d2 d2 d2 d2 d2 d1 d1 d1 d1 d1 d0 d0 d0 d0 d0 (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) (64 bytes) d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0
Document #: 38-08005 Rev. **
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4.0
Addr
Register Summary (continued)
Name Description Endpoint 13 OUT Data Endpoint 14 OUT Data Endpoint 15 OUT Data Endpoint 8 IN Data Endpoint 9 IN Data Endpoint 10 IN Data Endpoint 11 IN Data Endpoint 12 IN Data Endpoint 13 IN Data Endpoint 14 IN Data Endpoint 15 IN Data D7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 D6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 D5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 D4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 D3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 D2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 D1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 D0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0
7F65 OUT13DATA 7F66 OUT14DATA 7F67 OUT15DATA 7F68 IN8DATA 7F69 IN9DATA 7F6A IN10DATA 7F6B IN11DATA 7F6C IN12DATA 7F6D IN13DATA 7F6E IN14DATA 7F6F IN15DATA
Isochronous Byte Counts 7F70 OUT8BCH 7F71 OUT8BCL 7F72 OUT9BCH 7F73 OUT9BCL 7F74 OUT10BCH 7F75 OUT10BCL 7F76 OUT11BCH 7F77 OUT11BCL 7F78 OUT12BCH 7F79 OUT12BCL 7F7A OUT13BCH 7F7B OUT13BCL 7F7C OUT14BCH 7F7D OUT14BCL 7F7E OUT15BCH 7F7F OUT15BCL 7F80-7F91 (reserved) CPU Registers 7F92 CPUCS 7F93 PORTACFG 7F94 PORTBCFG 7F95 PORTCCFG Control & Status Port A Configuration Port B Configuration Port C Configuration rv3
RxD1out
EP8 Out Byte Count H EP8 Out Byte Count L EP9 Out Byte Count H EP9 Out Byte Count L EP10 Out Byte Count H EP10 Out Byte Count L EP11 Out Byte Count H EP11 Out Byte Count L EP12 Out Byte Count H EP12 Out Byte Count L EP13 Out Byte Count H EP13 Out Byte Count L EP14 Out Byte Count H EP14 Out Byte Count L EP15 Out Byte Count H EP15 Out Byte Count L
0 d7 0 d7 0 d7 0 d7 0 d7 0 d7 0 d7 0 d7
0 d6 0 d6 0 d6 0 d6 0 d6 0 d6 0 d6 0 d6
0 d5 0 d5 0 d5 0 d5 0 d5 0 d5 0 d5 0 d5
0 d4 0 d4 0 d4 0 d4 0 d4 0 d4 0 d4 0 d4
0 d3 0 d3 0 d3 0 d3 0 d3 0 d3 0 d3 0 d3
0 d2 0 d2 0 d2 0 d2 0 d2 0 d2 0 d2 0 d2
d9 d1 d9 d1 d9 d1 d9 d1 d9 d1 d9 d1 d9 d1 d9 d1
d8 d0 d8 d0 d8 d0 d8 d0 d8 d0 d8 d0 d8 d0 d8 d0
rv2
RxD0out
rv1 FRD INT5 T1
rv0 FWR INT4 T0
24/48 CS TxD1 INT1
CLKINV OE RxD1 INT0
CLKOUT OE
8051RES
T1out T2EX TxD0
T0out T2 RxD0
T2OUT RD
INT6 WR
Input-Output Port Registers 7F96 OUTA 7F97 OUTB 7F98 OUTC 7F99 PINSA 7F9A PINSB 7F9B PINSC 7F9C OEA 7F9D OEB Output Register A Output Register B Output Register C Port Pins A Port Pins B Port Pins C Output Enable A Output Enable B OUTA7 OUTB7 OUTC7 PINA7 PINB7 PINC7 OEA7 OEB7 OUTA6 OUTB6 OUTC6 PINA6 PINB6 PINC6 OEA6 OEB6 OUTA5 OUTB5 OUTC5 PINA5 PINB5 PINC5 OEA5 OEB5 OUTA4 OUTB4 OUTC4 PINA4 PINB4 PINC4 OEA4 OEB4 OUTA3 OUTB3 OUTC3 PINA3 PINB3 PINC3 OEA3 OEB3 OUTA2 OUTB2 OUTC2 PINA2 PINB2 PINC2 OEA2 OEB2 OUTA1 OUTB1 OUTC1 PINA1 PINB1 PINC1 OEA1 OEB1 OUTA0 OUTB0 OUTC0 PINA0 PINB0 PINC0 OEA0 OEB0
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4.0
Addr
Register Summary (continued)
Name Description Output Enable C 230k Baud Configuration D7 OEC7 0 D6 OEC6 0 D5 OEC5 0 D4 OEC4 0 D3 OEC3 0 D2 OEC2 0 D1 OEC1 UART1 D0 OEC0 UART0
7F9E OEC 7F9F
UART230
Isochronous Control/Status Registers 7FA0 ISOERR 7FA1 ISOCTL 7FA2 ZBCOUT 7FA3 (reserved) 7FA4 (reserved) I2C Registers 7FA5 I2CS 7FA6 I2DAT 7FA7 I2CMODE Interrupts 7FA8 IVEC 7FA9 IN07IRQ 7FAA OUT07IRQ 7FAB USBIRQ 7FAC IN07IEN 7FAD OUT07IEN 7FAE USBIEN 7FAF USBBAV 7FB0 IBNID 7FB1 IBNMASK 7FB2 BPADDRH 7FB3 BPADDRL Interrupt Vector EPIN Interrupt Request EPOUT Interrupt Request USB Interrupt Request EP0–7IN Int Enables EP0–7OUT Int Enables USB Int Enables Breakpoint & Autovector IN-Bulk-NAK ID IN-Bulk-NAK Intr. mask Breakpoint Address H Breakpoint Address L 0 IN7IR OUT7IR 0 IN7IEN
OUT7IEN
ISO OUT Endpoint Error Isochronous Control Zero Byte Count bits
ISO15 ERR
ISO14 ERR
ISO13 ERR
ISO12 ERR
ISO11 ERR
ISO10 ERR
ISO9 ERR
ISO8 ERR
ISODISAB
* EP15
* EP14
* EP13
* EP12
PPSTAT EP11
0 EP10
0 EP9
EP8
Control & Status Data STOP Int Enable, I2C bus speed
START d7 0
STOP d6 0
LASTRD
ID1 d4 0
ID0 d3 0
BERR d2 0
ACK d1 STOPIE
DONE d0 400KHZ
d5 0
IV4 IN6IR OUT6IR 0 IN6IEN
OUT6IEN
IV3 IN5IR OUT5IR IBNIR IN5IEN
OUT5IEN
IV2 IN4IR OUT4IR URESIR IN4IEN
OUT4IEN
IV1 IN3IR OUT3IR SUSPIR IN3IEN
OUT3IEN
IV0 IN2IR OUT2IR
SUTOKIR
0 IN1IR OUT1IR SOFIR IN1IEN
OUT1IEN
0 IN0IR OUT0IR
SUDAVIR
IN2IEN
OUT2IEN SUTOKIE
BPPULSE
IN0IEN
OUT0IEN SUDAVIE
0 * EP7IN EP7IN A15 A7
0 * EP6IN EP6IN A14 A6
IBNIE * EP5IN EP5IN A13 A5
URESIE
INT2SFC
SUSPIE BREAK EP3IN EP3IN A11 A3
SOFIE BPEN EP1IN EP1IN A9 A1
AVEN EP0IN EP0IN A8 A0
EP4IN EP4IN A12 A4
EP2IN EP2IN A10 A2
Bulk Endpoints 0–7 7FB4 EP0CS 7FB5 IN0BC 7FB6 IN1CS 7FB7 IN1BC 7FB8 IN2CS 7FB9 IN2BC 7FBA IN3CS 7FBB IN3BC 7FBC IN4CS 7FBD IN4BC 7FBE IN5CS 7FBF IN5BC 7FC0 IN6CS 7FC1 IN6BC 7FC2 IN7CS 7FC3 IN7BC 7FC4 (reserved) Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count * * * * * * * * * * * * * * * * * d6 * d6 * d6 * d6 * d6 * d6 * d6 * d6 * d5 * d5 * d5 * d5 * d5 * d5 * d5 * d5 * d4 * d4 * d4 * d4 * d4 * d4 * d4 * d4
OUTBSY
INBSY d2 * d2 * d2 * d2 * d2 * d2 * d2 * d2
HSNAK d1 in1bsy d1 in2bsy d1 in3bsy d1 in4bsy d1 in5bsy d1 in6bsy d1 in7bsy d1
EP0STALL
d3 * d3 * d3 * d3 * d3 * d3 * d3 * d3
d0 in1stl d0 in2stl d0 in3stl d0 in4stl d0 in5stl d0 in6stl d0 in7stl d0
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4.0
Addr
Register Summary (continued)
Name Description Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Control & Status Byte Count Byte Count Control & Status D7 * * * * * * * * * * * * * * * * * D6 d6 * d6 * d6 * d6 * d6 * d6 * d6 * d6 d6 * D5 d5 * d5 * d5 * d5 * d5 * d5 * d5 * d5 d5 * D4 d4 * d4 * d4 * d4 * d4 * d4 * d4 * d4 d4 * D3 d3 * d3 * d3 * d3 * d3 * d3 * d3 * d3 d3 * D2 d2 * d2 * d2 * d2 * d2 * d2 * d2 * d2 d2 * D1 d1 out1bsy d1 out2bsy d1 out3bsy d1 out4bsy d1 out5bsy d1 out6bsy d1 out7bsy d1 d1 out1bsy D0 d0 out1stl d0 out2stl d0 out3stl d0 out4stl d0 out5stl d0 out6stl d0 out7stl d0 d0 out1stl
7FC5 OUT0BC 7FC6 OUT1CS 7FC7 OUT1BC 7FC8 OUT2CS 7FC9 OUT2BC 7FCA OUT3CS 7FCB OUT3BC 7FCC OUT4CS 7FCD OUt4BC 7FCE OUT5CS 7FCF OUT5BC 7FD0 OUT6CS 7FD1 OUT6BC 7FD2 OUT7CS 7FD3 OUT7BC 7FC5 OUT0BC 7FC6 OUT1CS
Global USB Registers 7FD4 SUDPTRH 7FD5 SUDPTRL 7FD6 USBCS 7FD7 TOGCTL 7FD8 USBFRAMEL 7FD9 USBFRAMEH 7FDA (reserved) 7FDB FNADDR 7FDC (reserved) 7FDD USBPAIR 7FDE IN07VAL 7FDF OUT07VAL 7FE0 INISOVAL 7FE1 OUTISOVAL 7FE2 FASTXFR 7FE3 AUTOPTRH 7FE4 AUTOPTRL 7FE5 AUTODATA 7FE6-7FE7 (reserved) Setup Data 7FE8 SETUPDAT 8 bytes of SETUP data d7 d6 d5 d4 d3 d2 d1 d0 Endpoint Control Input Endpoint 0–7 valid Output Endpoint 0–7 valid Input EP 8–15 valid Output EP 8–15 valid Fast Transfer Mode Auto-Pointer H Auto-Pointer L Auto Pointer Data
ISOsend0
Setup Data Ptr H Setup Data Ptr L USB Control & Status Toggle Control Frame Number L Frame Number H
A15 A7
WakeSRC
A14 A6 * S FC6 0
A13 A5 * R FC5 0
A12 A4 * IO FC4 0
A11 A3 DisCon 0 FC3 0
A10 A2 DiscOE EP2 FC2 FC10
A9 A1 ReNum EP1 FC1 FC9
A8 A0 SIGRSUME EP0 FC0 FC8
Q FC7 0
Function Address
0
FA6
FA5
FA4
FA3
FA2
FA1
FA0
* IN6VAL
OUT6VAL
PR6OUT
PR4OUT
PR2OUT
PR6IN IN2VAL
OUT2VAL
PR4IN IN1VAL
OUT1VAL
PR2IN 1 1 IN8VAL
OUT8VAL
IN7VAL
OUT7VAL
IN5VAL
OUT5VAL
IN4VAL
OUT4VAL
IN3VAL
OUT3VAL
IN15VAL
OUT15VAL
IN14VAL
OUT14VAL
IN13VAL
OUT13VAL
IN12VAL
OUT12VAL
IN11VAL
OUT11VAL
IN10VAL
OUT10VAL
IN9VAL
OUT9VAL
FISO A15 A7 D7
FBLK A14 A6 D6
RPOL A13 A5 D5
RMOD1 A12 A4 D4
RMOD0 A11 A3 D3
WPOL A10 A2 D2
WMOD1
WMOD0
A9 A1 D1
A8 A0 D0
Isochronous FIFO Sizes 7FF0 OUT8ADDR 7FF1 OUT9ADDR 7FF2 OUT10ADDR Endpt 8 OUT Start Addr Endpt 9 OUT Start Addr Endpt 10 OUT Start Addr A9 A9 A9 A8 A8 A8 A7 A7 A7 A6 A6 A6 A5 A5 A5 A4 A4 A4 0 0 0 0 0 0
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4.0
Addr
Register Summary (continued)
Name Description Endpt 11 OUT Start Addr Endpt 12 OUT Start Addr Endpt 13 OUT Start Addr Endpt 14 OUT Start Addr Endpt 15 OUT Start Addr Endpt 8 IN Start Addr Endpt 9 IN Start Addr Endpt 10 IN Start Addr Endpt 11 IN Start Addr Endpt 12 IN Start Addr Endpt 13 IN Start Addr Endpt 14 IN Start Addr Endpt 15 IN Start Addr D7 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 D6 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 D5 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 D4 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 D3 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 D2 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0
7FF3 OUT11ADDR 7FF4 OUT12ADDR 7FF5 OUT13ADDR 7FF6 OUT14ADDR 7FF7 OUT15ADDR 7FF8 IN8ADDR 7FF9 IN9ADDR 7FFA IN19ADDR 7FFB IN11ADDR 7FFC IN12ADDR 7FFD IN13ADDR 7FFE IN14ADDR 7FFF IN15ADDR
* - register bit is not used and undefined if read.
5.0
Input/Output Pin Special Consideration
The EZ-USB FX has a weak internal pull-up resistor that is present on the inputs and outputs when the external signal level is a high (above 1.3V). The weak internal pull-up is not present in the circuit when the voltage level of the external signal is low. Since the weak pull-up is only in the circuit when the external signal level is high, this means that if the last voltage level driven on the pin was a high, the pull-up resistor will keep it high. However, if the last voltage level driven on the pin was a low then the pull-up is turned off and the pad can float until it gets to a high logic level. This situation affects both inputs as well as outputs that are three-stated. Use a 25-KΩ or lower pull-down resistor to bring a pin to a low level if needed.
6.0
Absolute Maximum Ratings
Storage Temperature .......................................................................................................................................... –65°C to +150°C Ambient Temperature with Power Supplied ...............................................................................................................0°C to +70°C Supply Voltage on VCC relative to VSS.................................................................................................................... –0.5V to +4.0V DC Input Voltage............................................................................................................................................. –0.5V to VCC+0.5V DC Voltage Applied to Outputs in High Z State ............................................................................................... –0.5V to VCC+0.5V Power Dissipation ..............................................................................................................................................................500 mW Static Discharge Voltage................................................................................................................ >1000V (per JEDEC standard) Latch-up Current .............................................................................................................................................................. >200 mA Max Output Sink Current ..................................................................................................................................................... 10 mA
7.0
Operating Conditions
TA (Ambient Temperature Under Bias) ......................................................................................................................0°C to +70°C Supply Voltage ........................................................................................................................................................ +3.0V to +3.6V Ground Voltage .......................................................................................................................................................................... 0V FOSC (Oscillator or Crystal Frequency) ................................................................................................................ 12 MHz ± 0.25%
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8.0 DC Characteristics
Description Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Voltage High Output Low Voltage Input Pin Capacitance Suspend Current Supply Current Output Voltage High Output Low Voltage Output Impedance (HIGH state) Output Impedance (LOW state) Input Leakage Current Three-State Output OFF-State Current 8051 running, connected to USB IOUT = 1.6 mA IOUT = –1.6 mA Includes external 24Ω ±1% resistor Includes external 24Ω ±1% resistor VCC = 3.6V; VI = 5.5V or GND; not for IO pins VI = VIH or VIL; VO = VCC or GND 2.8 0.0 28 28 ±0.1 120 50 0< VIN < VCC IOUT = 1.6 mA IOUT = –1.6 mA 2.4 0.8 10 275
[2]
Parameter VCC VIH VIL II VOH VOL CIN ISUSP ICC VOH VOL RpH RpL Ii Ioz
Conditions
Min. 3.0 2 –0.5
Typ.
Max. 3.6 5.25 0.8 ±10
Unit V V V µA V V pF µA mA V V Ω Ω µA µA
TBD 3.6 0.3 44 44 ±5 ±10
USB Transceiver
Note: 2. Maximum suspend current is not guaranteed.
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9.0
9.1
AC Electrical Characteristics
USB Transceiver
Specified Conditions: Per Table 7-6 of Revision 1.1 of USB specification Parameter Trise Tfall tRFM Vcr Description Rise and Fall Times Full Speed Rise/Fall Time Matching Crossover Point Condition Min. 4 4 90 1.3 Max. 20 20 110 2.0 Unit ns ns % V
9.2
Program Memory Read
tCL
CLKOUT
Note 3
tAV
tAV
A[15..0]
tSTBL tSTBH
PSEN#
tACC1
[4]
tDSU data in
tDH
D[7..0]
f1_8051_pgmemrd.vsd
Parameter tCL tAV tSTBL tSTBH tDSU
Description 1/CLKOUT Frequency Delay from Clock to Valid Address Clock to PSEN Low Clock to PSEN High Data Set-up to Clock
Min.
Typ. 41.66 20.83
Max.
Unit ns ns
Notes 24 MHz 48 MHz
0 0 0 0
10 8 8 10
ns ns ns ns ns
Data Hold Time tDH Notes: 3. CLKOUT is shown with positive polarity. 4. tACC1 is computed from the above parameters as follows: tACC1(24 MHz) = 3*tCL – tAV –tDSU = 106 ns tACC1(48 Mhz) = 3*tCL – tAV – tDSU = 44 ns
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9.3 Data Memory Read
tCL
Stretch=0
CLKOUT
tAV tSTBL tSTBH tAV
A[15..0] RD#
tACC2
[5]
tDSU
data in
tDH
D[7..0]
tCL
Stretch=1
CLKOUT
tAV
A[15..0] RD#
tACC3
[5]
tDSU
data in
tDH
D[7..0]
f2_8051_datamemrd.vsd
Parameter tCL tAV tSTBL tSTBH tDSU
Description 1/CLKOUT Frequency Delay from Clock to Valid Address Clock to RD Low Clock to RD High Data Set-up to Clock
Min.
Typ. 41.66 20.83
Max.
Unit ns ns
Notes 24 MHz 48 MHz
0 0 0 0
10 8 8 10
ns ns ns ns ns
Data Hold Time tDH Note: 5. tACC2 and tACC3 are computed from the above parameters as follows: tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns tACC2(48 Mhz) = 3*tCL – tAV – tDSU = 44 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 188 ns tACC3(48 Mhz) = 5*tCL – tAV – tDSU = 85 ns
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9.4 Data Memory Write
tCL
Stretch=0
CLKOUT
tAV tSTBL tSTBH tAV
A[15..8]
WR#
tON1 tOFF1 data out
D[7..0]
tCL
Stretch=1
CLKOUT
tAV tAV
A[15..8] WR#
tON1 tOFF1 data out
data_memory_write.vsd
D[7..0]
Parameter tAV tSTBL tSTBH tON1 tOFF1
Description Delay from Clock to Valid Address Clock to WR Pulse Low Clock to WR Pulse High Clock to Data Turn-on Clock to Data Hold Time
Min. 0 0 0 0 –2
Max. 10 8 8 7 7
Unit ns ns ns ns ns
Notes
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9.5 DMA Read
tCL
non-burst
CLKOUT
tAV
A[15..0]
Note 6
RD#/FRD# CS#, OE#
Note 7
tSTBL
tSTBH
tDSU
in
tDH
in in
D[7..0]
tCL
burst
CLKOUT
tAV
A[15..0]
Note 6
RD#/FRD# CS#, OE# D[7..0]
tSTBL
tSTBH
tDSU
in
tDH
in in in in
f4_dmard.vsd
Parameter tAV tSTBL tSTBH tDSU
Description Delay from Clock to Valid Address Clock to Strobe Low Clock to Strobe High Data to Clock Set-up
Min. 0 0 0 0
Max. 10 8 8 10
Unit ns ns ns ns ns
Notes Non-burst Non-burst
Clock to Data Hold tDH Notes: 6. The address bus is not used in external FIFO transfers that use FRD#. 7. This is the maximum data rate. The strobes are programmable for longer access times.
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9.6 DMA Write
tCL
Non-Burst
CLKOUT
tAV
A[15..0]
Note 8
tSTBL
tSTBH tOFF1
WR#/FWR# CS#, OE#
Note 9
tON1
tDA
D[7..0]
tCL
Burst
CLKOUT
tAV
A[15..0]
Note 8
WR#/FWR# CS#, OE# D[7..0]
tSTBL tDA
tSTBH
f5_dmawr.vsd
Parameter tAV tSTBL tSTBH tDA tON1
Description Clock to Address Valid Clock to Strobe Low Clock to Strobe High Clock to Valid Data Clock to Data Turn-on
Min. 0 0 0 0
Max. 10 8 8 12 7 7
Unit ns ns ns ns ns ns
Notes Non-burst Non-burst
Clock to Data Hold Time –2 tOFF1 Notes: 8. The address bus in not used in external FIFO transfers (FWR# strobe). 9. This is the maximum data rate. The WR/FWR pulses are programmable for longer access times.
9.7
Slave FIFOs—Output Enables
AOE BOE AFI [7..0] BFI [7..0]
Parameter tON tOFF
tON tOFF
f6_fifo_sync_oe.vsd
Description FIFO Data Bus Turn-on Time FIFO Data Bus Turn-off Time
Min. 0 0
Max. 10 10
Unit ns ns
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9.8 Slave FIFOs—Synchronous Read
tCL
XCLK
tSUX tXH
ASEL/BSEL SLRD
tXDA
AFI/BFI [7..0]
tXFLAG
FLAGS
f7_fifo_sync_read.vsd
Parameter tSUX tXH tXDA tXFLAG
Description Strobe & Sel to External Clock Set-up Time External Clock to Strobe & Sel Hold Time Clock to A/B FIFO data Clock to FIFO flag
Min. 6
Max. 9 13 2tCL+11
Unit ns ns ns ns
9.9
Slave FIFOs—Synchronous Write
tCL
XCLK
tSUX tXH
ASEL/BSEL SLWR AFI/BFI [7..0] FLAGS
f8_fifo_sync_write.vsd
valid
tXFLAG
Parameter tCL tSUX tXH tXFLAG CLKOUT Period
Description
Min.
Typ. 41.66 20.83
Max.
Unit ns ns
Sel, Strobe & Data Set-up to External Clock External Clock to Sel, Strobe & Data Hold Time External Clock to FIFO Flag 2
9 2tCL+11
ns ns ns
Document #: 38-08005 Rev. **
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CY7C64601/603/613
9.10 Slave FIFOs—Asynchronous Read[10, 11]
Note 12
ASEL/BSEL
tRDL tRDH
SLRD
tACCA
AFI/BFI [7..0]
tAFLAG
FLAGS
f9_fifo_async_read.vs
Parameter tRDL tRDH tACCA tAFLAG
Description SLRD strobe active SLRD strobe inactive Read active to FIFO data valid SLRD inactive to FIFO flag
Min. 30
Max. 70 90 40 95
Unit ns ns ns ns ns
Notes
double byte mode
9.11
Slave FIFOs—Asynchronous Write[10, 11]
Note 12
ASEL/BSEL
tWRL tWRH
SLWR
tSUA tHA
AFI/BFI [7..0]
tAFLAG
FLAGS
f10_fifo_async_write.vsd
Parameter tWRL tWRH tSUA tHA tAFLAG
Description Slave Write Strobe Active Slave Write Strobe Inactive Async Data Set-up Time to Write Strobe Inactive Async Data Hold Time to Write Strobe Inactive Async Write Strobe Inactive to FIFO Flag Valid
Min. 30 70 10 5
Max.
Unit ns ns ns ns
95
ns
Notes: 10. The timing diagram assumes OEA/OEB is active. 11. The read operation begins when both A/BSEL and SLRD are active, and ends when either is inactive. 12. The polarities of ASEL/BSEL and SLRD are programmable. Active-LOW is shown.
Document #: 38-08005 Rev. **
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9.12 GPIF Signals (Internally Clocked)
tCL
XCLK (output)
tSRY tRYH
RDYn
GD[15..0] (input) CTLn and GD[15..0] (output)
Parameter tSRY tRYH tXGD
valid
tXGD
Description RDYn and GPIF Data to External Clock Set-up Time External Clock to RDYn and GPIF Data Hold Time Clock to GPIF Data and CTLn output
Min. 2
Max. 9 13
Unit ns ns ns
9.13
GPIF Signals (Externally Clocked)
tCL
XCLK (input)
tSRX tRYX
RDYn
GD[15..0] (input) CTLn and GD[15..0] (output)
Parameter tSRX tRYX tXGX
valid
tXGX
Description RDYn and GPIF Data to External Clock Set-up Time External Clock to RDYn and GPIF Data Hold Time Clock to GPIF Data and CTLn output
Min. 2
Max. 9 13
Unit ns ns ns
Note: 13. tcl for an XCLK input must be greater than 20.83 ns.
Document #: 38-08005 Rev. **
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10.0 Ordering Information
Part Number CY7C64601-52NC CY7C64603-52NC CY7C64613-52NC CY7C64603-80NC CY7C64613-80NC CY7C64603-128NC CY7C64613-128NC EZ-USB FX Xcelerator Development Kit Package Type 52 PQFP 52 PQFP 52 PQFP 80 PQFP 80 PQFP 128 PQFP 128 PQFP CY3671 RAM Size 4K 8K 8K 8K 8K 8K 8K Burst I/O Rate (Bytes/sec) 48 Mbytes 48 Mbytes 48 Mbytes 96 Mbytes 96 Mbytes 96 Mbytes 96 Mbytes # Prog I/Os 16 16 16 32 32 40 40 Dataport 8-bit 8-bit 8-bit 16-bit 16-bit 16-bit + Addr 16-bit + Addr Isochronous Support No No Yes No Yes No Yes
11.0
11.1
Package Diagrams
52 PQFP
13.20 BSC 10.0 BSC 7.8 REF. 1.1 REF. 52 40 SQ.
1
39
0.65 BSC
52 PQFP
13
27
14
26
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CY7C64601/603/613
8 Places 12/16o
2.35 MAX See Lead Detail
0.22/0.33
With Lead Finish
0.13/0.23
~
0.13/0.17
Base Metal
0.22/0.38
0.40 M IN
0.13 R. M IN. Base Plane
0.13/ 0.30 R.
Seating Plane
0.10 0.25
0.73 1.03
0 - 7o
1.60 R EF
52-Pin Lead Detail
Document #: 38-08005 Rev. **
0 .2 5 G a ge P lane
0o M IN 1.95 2.10
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CY7C64601/603/613
11.2 80 PQFP
17.20 BSC. 14.00 BSC. 12.00 BSC. 1.00 Ref.
80 61
1
60
0.65 BSC.
80 PQ FP
20
41
21
40
3.00 MAX
See Lead Detail
0.22/0.33
With Lead Finish
0.13/0.23
~
0.13/0.17
Base Metal
0.22/0.38
Document #: 38-08005 Rev. **
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CY7C64601/603/613
0.40 MIN. 0D MIN.
2.55 2.75 0.13 R. MIN. Base Plane
0.13/0.30 R.
GAGE PLANE
0.25 Seating Plane 0.10 0.25
0.73 1.03 1.60 REF.
0-7D
80-Pin Lead Detail
Document #: 38-08005 Rev. **
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CY7C64601/603/613
11.3 128 PQFP
23.2 BS . C
20.0 BS C.
18.5 R EF 0.75 R EF.
102 65
103
64
17.20 B S C.
14.0 B S C .
14.0 BA SIC
12.5 R E F
0.50 BSC .
128 PQFP
128
39
1
38
0.75 R E F.
8 Places 12/16o See Lead Detail
3.40 MAX
0.13/0.28
With Lead Finish
0.11/0.23
~
0.11/0.19
Base Metal
0.13/0.25
Document #: 38-08005 Rev. **
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CY7C64601/603/613
0.40 M IN
0.13 R. M IN. Base Plane
0.13/ 0.30 R .
Seating Plane
0.25 0.50
0.73 1.03
0 - 7o
1.60 R EF
128-Pin Lead Detail
Document #: 38-08005 Rev. **
0.2 5 G ag e P lane
0o M IN 2 .57 2 .87
Page 41 of 42
CY7C64601/603/613
Document Title: CY7C64601/CY7C64603/CY7C64613 EZ USB FX USB Microcontroller Document Number: 38-08005 REV. ** ECN NO. 110206 Issue Date 11/11/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00903 to 38-08005
Document #: 38-08005 Rev. **
Page 42 of 42
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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