CY7C68003-20FNXI

CY7C68003 MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver Features The Cypress MoBL-USB™ TX2UL is a low voltage high speed (HS) USB 2.0 UTMI+ Low Pin Interface (ULPI) Transceiver. The TX2UL is specifically designed for mobile handset applications by offering tiny package options and low power consumption. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ UART Pass Through Mode ESD Compliance: ❐ JESD22-A114D 8 kV Contact Human Body Model (HBM) for DP, DM, and VSS Pins ❐ IEC61000 - 4-2 8 kV Contact Discharge ❐ IEC61000 - 4-2 15 kV Air Discharge Support for Industrial Temperature Range: (-40°C to 85°C) Low Power Consumption for Mobile Applications: ❐ 5 uA Nominal Sleep Mode ❐ 30 mA Nominal Active HS Transfer Small Package for Mobile Applications: ❐ 2.14 x 1.76 mm 20-pin WLCSP 0.4 mm Pitch ❐ 4 x 4 mm 24-pin QFN USB 2.0 Full Speed and High Speed Compliant Transceiver Multi Range (1.8V to 3.3V) I/O Voltages Fully Compliant ULPI Link Interface 8-bit SDR ULPI Data Path UTMI+ Level 0 Support Support USB Device Mode only Integrated Oscillator Integrated Phase Locked Loop (PLL) – 13, 19.2, 24, or 26 MHz Reference Integrated USB Pull Up and Termination Resistors 3.0V to 5.775V VBATT Input Chip Select Pin Single Ended Device RESET Input ■ ■ ■ Applications ■ ■ ■ ■ ■ Mobile Phones PDAs Portable Media Players (PMPs) DTV Applications Portable GPS Units TX2UL Block Diagram TX2UL ULPI Block CLOCK DATA[7:0] DIR STP NXT IO Control/ Data Logic Operational mode tracking interrupt Registers Block ULPI Wrapper Tx/Rx Core UTMI+ Level0 DP USB FS/HS PHY DM RXD TXD RESET_N CS_N (3.0 – 5.775V) VBATT VCC (1.8V) XI XO Global Control Block Reset / Clock / Power / Misc. Control POR PLL 3.3V Regulator Block 1.8V Bandgap 13/19.2/ 24/26 MHz XOSC Cypress Semiconductor Corporation Document Number: 001-15775 Rev. *I ‚Ä¢ 198 Champion Court ‚Ä¢ San Jose, CA 95134-1709 ‚Ä¢ 408-943-2600 Revised September 22, 2010 [+] Feedback CY7C68003 Contents Features............................................................................. 1 TX2UL Block Diagram ...................................................... 1 Applications ...................................................................... 1 Contents ............................................................................ 2 Functional Overview ........................................................ 3 UTMI+ Low Pin Interface (ULPI) ................................. 3 Oscillator (OSC) .......................................................... 3 Phase Locked Loop (PLL)........................................... 3 Power On Reset (POR)............................................... 3 Reset (RESET_N) ....................................................... 3 DP and DM pins .......................................................... 3 Chip Select (CS_N) ..................................................... 3 USB2 Transceiver Macrocell Interface (UTMI+).......... 3 Global Control ............................................................. 3 Full Speed and High Speed USB Transceivers (FS/HS) .................................................. 3 USB Pull up and Intr Detect, Termination Resistors (Pull up/TERM)............................................................ 3 UART Pass Through Mode ......................................... 3 Clocking....................................................................... 4 Power Domains ........................................................... 4 Operation Modes......................................................... 5 VID and PID ................................................................ 6 Pinouts .............................................................................. 7 Synchronous Operation Modes ...................................... 9 ULPI Transmit Command Byte (TX CMD) .................. 9 ULPI Receive Command Byte (RX CMD) ................... 9 USB Data Transmit (NOPID)..................................... 10 USB Data Transmit (PID) .......................................... 11 USB Packet Receive ................................................. 11 Immediate Register Read and Write ......................... 12 Immediate Register Read and Write Aborted by USB Receive .............................................................. 13 Back to Back Immediate Register Read and Write and USB Receive ............................................................. 14 Configuration Mode........................................................ 16 Configuration Mode in 20-pin CSP package ............. 16 Configuration Mode in 24-pin QFN package ............. 16 Power On Reset (POR)............................................. 16 Register ..................................................................... 16 Register Map ............................................................. 16 Immediate Register Set............................................. 17 Function Control Register.......................................... 17 Interface Control Register ......................................... 18 Debug Register ......................................................... 18 Scratch Register........................................................ 18 Carkit Control Register .............................................. 18 Drive Strength and Slew Rate Configuration Register ............................................... 19 USB Interface Control Register ................................. 19 Absolute Maximum Ratings .......................................... 20 Operating Conditions..................................................... 20 DC Characteristics ......................................................... 21 AC Characteristics ......................................................... 21 Ordering Information...................................................... 24 Package Diagram............................................................ 24 Document History Page ................................................. 26 Sales, Solutions, and Legal Information ...................... 27 Worldwide Sales and Design Support....................... 27 Products .................................................................... 27 PSoC Solutions ......................................................... 27 Document Number: 001-15775 Rev. *I Page 2 of 27 [+] Feedback CY7C68003 Functional Overview UTMI+ Low Pin Interface (ULPI) This block conforms to the ULPI Specification. It supports the 8-bit wide SDR data path. The primary I/Os of this block support multi-range LVCMOS signaling from 1.8V to 3.3V (±5%). The level used is automatically selected by the voltage applied to VCCIO and is set at any voltage between 1.8V and 3.3V. When the CS_N pin is deasserted (high), all the pins in the ULPI interface are tristated. USB2 Transceiver Macrocell Interface (UTMI+) This block conforms to the UTMI+ Level 0 standard. It performs all the UTMI to USB translation. Global Control This block is the digital control logic that ties the blocks of the device together. Its functions include pull up control, over current protect control, and more. Oscillator (OSC) This block meets the requirements of both the on-chip PLL and the USB-IF requirements for clock parameters. It is a fundamental mode parallel resonant oscillator with a maximum ESR of 60Ω. It supports the following: ■ ■ Full Speed and High Speed USB Transceivers (FS/HS) The FS and HS Transceivers comply fully with the USB 2.0 specifications. Integrated Crystal Oscillator – 13, 19.2, 24, or 26 MHz crystal 13, 19.2, 24, or 26 MHz LVCMOS single ended input clock on XI Phase Locked Loop (PLL) The PLL meets all clock stability requirements imposed by this device and the USB standard. It supports all requirements to make the device compliant to the USB 2.0 specifications. It also has a fractional multiplier that enables it to supply the correct frequency to the device when it is presented with a 13, 19.2, 24, or 26 MHz reference clock. USB Pull up and Intr Detect, Termination Resistors (Pull up/TERM) These blocks contain the USB pull up and termination resistors as specified by the USB 2.0 specification. UART Pass Through Mode TX2UL supports Carkit UART Pass Through Mode. When the Carkit Mode bit in the Interface Control register is set, it enables the Link to communicate through the DP/DM to a remote system using UART signaling. By default, the clock is powered down when the TX2UL enters Carkit Mode. Entering and exiting the Carkit Mode is identical to the Serial Mode. Table 1, Table 2, and Figure 1 show the UART Signal Mapping between the DP/DM and DATA[1:0] at ULPI interface. Table 1. UART Signal Mapping at ULPI Interface Signal txd rxd Reserved Maps to DATA[0] DATA[1] DATA[7:2] Direction IN OUT Description UART TXD signal routed to DM pin UART RXD signal routed to DP pin Reserved Power On Reset (POR) This block provides a POR signal (internal) based on the input supply. An internal POR is generated when VCC input rises above VPOR(trip). Reset (RESET_N) The three major functions of RESET_N pin are as follows: ■ ■ ■ Reset TX2UL Place TX2UL into Sleep Mode Place TX2UL into Configuration Mode When the RESET_N pin is asserted (low) for tSTATE (tSTATE is specified in Table 21 on page 21), the TX2UL enters either Sleep Mode or Configuration Mode depending on the CS_N state. When RESET_N is asserted while CS_N is asserted, TX2UL enters Sleep Mode. When RESET_N is asserted for tSTATE while CS_N is deasserted, TX2UL enters Configuration Mode. In these modes, all the pins in the ULPI interface are tristated. If the RESET_N pin is not used, it must be pulled high. For information about different modes of configuration, see Table 5 on page 5. Table 2. UART Signal Mapping at USB Interface Signal TXD RXD Maps to DM DP Direction OUT INT Description UART TXD signal UART RXD signal DP and DM pins The DP and DM pins are the differential pins for the USB. They must be connected to the corresponding DP and DM pins of the USB receptacle. Figure 1. UART Signal Mapping in Pass Through Mode ULPI INTERFACE txd rxd DATA[0] DATA[1] USB INTERFACE Chip Select (CS_N) This signal pin is available only in 24-pin QFN package. The two major functions of CS_N are as follows: ■ ■ TX2UL DM TXD DP RXD Tristate the ULPI bus output pins Associate with RESET_N to place TX2UL in the Sleep mode Document Number: 001-15775 Rev. *I Page 3 of 27 [+] Feedback CY7C68003 Clocking TX2UL supports external crystal and clock inputs at the 13, 19.2, 24, and 26 MHz frequencies. The internal PLL applies the proper clock multiply option depending on the input frequency. For applications that use an external clock source to drive XI, the XO pin (in the 24-pin QFN package) is left floating. TX2UL has an on-chip oscillator circuit that uses an external 13, 19.2, 24, or 26 MHz (±100 ppm) crystal with the following characteristics: ■ ■ ■ ■ ■ The selection between input clock source and frequency on the XI pin is determined by the Chip Configuration register loaded through the RESET_N during Configuration Mode. The external clock source requirements are shown in Figure 3 on page 5. Figure 2. Crystal Configuration Parallel Resonant Fundamental Mode 750 mW Drive Level 12 pF (5 percent tolerance) Load Capacitors 150 ppm LVCMOS square wave clock input driven on the XI pin Crystal generated sine wave clock on the XI and XO pins TX2UL XI XTAL PLL XO 12 pf 12 pf TX2UL operates on one of two primary clock sources: ■ ■ * 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four layer FR4 PCA Table 3. External Clock Requirements Parameter Vn PN_100 PN_1k PN_10k PN_100k PN_1M Description Supply Voltage Noise at frequencies < 50 MHz Input Phase Noise at 100 Hz Input Phase Noise at 1 kHz offset Input Phase Noise at 10 kHz offset Input Phase Noise at 100 kHz offset Input Phase Noise at 1 MHz offset Duty Cycle Maximum Frequency Deviation 30 Specification Min Max 20 75 104 120 128 130 70 150 VBATT This is the battery input supply that powers the 3.3V regulator block. It can range anywhere from 3.0 to 5.775V during actual operation. Voltage Regulator The internal 3.3V regulator block regulates the VBATT supply to the internal 3.3V supply for the USBIO and XOSC blocks. If the supply voltage at VBATT is below 3.3V, the regulator block switches the VBATT supply directly for the USBIO and XOSC blocks. Power Supply Sequence TX2UL does not require a power supply sequence. All power supplies are independently sequenced without damaging the part. All supplies are up and stable for the device to function properly. The analog block contains circuitry that senses the power supply to determine when all supplies are valid. Unit mV p-p dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz % ppm Power Domains The TX2UL has three power supply domains: ■ ■ ■ VCC VIO VBATT VSS VSSBATT TX2UL has two grounds: ■ ■ VCC This is the core 1.8V power supply for the TX2UL. It can range anywhere from 1.7V to 1.9V during actual operation. VIO This is the 1.8V to 3.3V multi range supply to the I/O ring. It can range anywhere from 1.7V to 3.6V during actual operation. Document Number: 001-15775 Rev. *I Page 4 of 27 [+] Feedback CY7C68003 Operation Modes There are six operation modes available in TX2UL. They are: ■ ■ ■ ■ ■ ■ Normal Operation Mode Configuration Mode ULPI Low Power Mode Sleep Mode Carkit UART Pass Through Mode Tristate ULPI Interface Output Mode (only available in 24-pin QFN package) ULPI low power mode to Sleep mode, TX2UL changes to normal operation mode first, and then to Sleep mode. The Mode Change State diagram in Figure 3 shows the mode change path of TX2UL. The entries of the six operations modes (20-pin CSP package has five operation modes) are listed in Table 4 and Table 5. There are three mode change transactions that require the RESET_N assert or deassert with tSTATE (see Table 21 on page 21 for tSTATE). The three mode change transactions are: ■ ■ ■ Change from Normal Operation Mode to Configuration Mode; RESET_N is required to assert with tSTATE Change from Configuration Mode to Normal Operation Mode; RESET_N is required to de-assert with tSTATE Change from Normal Operation Mode to Sleep Mode; RESET_N is required to assert with tSTATE When changing the operation modes, if the current and changing modes are not the normal operation Mode, TX2UL first changes to the normal operation mode. For example, to change from Figure 3. Mode Change State Diagram Sleep Mode Carkit UART Pass Through Mode Tri-State ULPI Interface Output Mode (available in 24pin QFN package only) Normal Operation Mode Configuration Mode ULPI Low Power Mode Table 4. TX2UL 20-Pin CPS Package Operation Modes RESET_N 0 (Low) 1 (High) 1 (High) 1 (High) Sleep Mode Normal Operation Mode Enter into ULPI Low Power Mode by setting SuspendM register bit (in Function Control Register) to 0 during the Normal Operation Mode. Enter into Carkit UART Pass Through Mode by setting Carkit Mode register bit (in Interface Control Register) to 1 during the Normal Operation Mode. Mode Table 5. TX2UL 24-Pin QFN Package Operation Modes CS_N 0 (Low) 0 (Low) 0 (Low) RESET_N 0 (Low) 1 (High) 1 (High) Sleep Mode Normal Operation Mode Enter into ULPI Low Power Mode by setting SuspendM register bit (in Function Control Register) to 0 during the Normal Operation Mode. Enter into Carkit UART Pass Through Mode by setting Carkit Mode register bit (in Interface Control Register) to 1 during the Normal Operation Mode. Configuration Mode Tristate ULPI Interface output pins Mode 0 (Low) 1 (High) 0 (Low) Enter into Configuration Mode when Power On (VCC On) 1 (High) 1 (High) 0 (Low) 1 (High) Document Number: 001-15775 Rev. *I Page 5 of 27 [+] Feedback CY7C68003 The operation and configuration modes are described in the sections Operation Modes on page 5 and Configuration Mode on page 16 respectively. The ULPI low power mode and Sleep mode are described in the following sections. ULPI Low Power Mode In this mode, the link optionally places the TX2UL in low power mode when the USB is suspended. TX2UL powers down all the circuitry except for the interface pins and full speed receiver. To enter low power mode, the link must set SuspendM in the Function Control register to 0b. The TX2UL clock is stopped for a minimum of five cycles after TX2UL accepts the register write. To exit low power mode, the link signals TX2UL to exit the mode by asynchronously asserting a signal, STP. The TX2UL wakes up its internal circuitry and when it meets the ULPI timing requirements, it deasserts DIR. The SuspendM register is set to 1b. Sleep Mode Sleep mode is entered by asserting RESET_N during the Normal Operation Mode. When RESET_N is driven low for tSTATE (see Table 21 on page 21 for tSTATE requirement) while CS_N is low, TX2UL enters Sleep Mode. VCC must remain supplied (ON) during the sleep mode. This mode powers down all internal circuitry except the RESET_N pin and the chip_config register. The ULPI interface bus is tristated. During the Sleep Mode ensure that: ■ ■ ■ The ULPI interface I/Os are either floating or driven high by the link DP and DM are either floating or pull to 0V Deassert RESET_N to exit the Sleep Mode. VID and PID The VID and PID are hard coded into Product ID and Vendor ID registers (read only) as shown in Table 6. Table 6. Immediate Register Values for VID and PID Field Name Vendor ID (VID) Low Vendor ID (VID) High Product ID (PID) Low Product ID (PID) High Size (bit) 8 8 8 8 Address (6 bits) Rd 00h 01h 02h 03h Wr Set Clr Value B4h 04h 03h 68h Document Number: 001-15775 Rev. *I Page 6 of 27 [+] Feedback CY7C68003 Pinouts TX2UL is available in 20-ball WLCSP and 24-pin QFN package. The pin assignment is shown in Figure 4 and Figure 5 Figure 4. Pin Assignment - TX2UL 20-Ball WLCSP (Top View) 1 2 3 4 5 A A1 VCC A2 XI A3 DP A4 DM A5 VBATT B B1 NXT B2 RESET_N B3 VSS B4 DATA[4] B5 VCC C C1 DIR C2 STP C3 DATA[6] C4 DATA[2] C5 DATA[0] D D1 CLOCK D2 DATA[7] D3 DATA[5] D4 DATA[3] D5 DATA[1] Table 7. Pin Definitions - TX2UL 20-Ball WLCSP Name DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] CLOCK NXT STP DIR USB DP DM Miscellaneous RESET_N B2 I 1.8V Global Reset. When RESET_N is asserted during the VCC power on, TX2UL enters into Configuration Mode. During Normal Operation Mode, asserting RESET_N resets the TX2UL and enter into the power saving mode. LVCMOS single ended clock of frequency 13, 19.2, 24, or 26 MHz Low voltage supply for the digital core and I/O High voltage supply for USB Common Ground A3 A4 I/O I/O USB USB USB D-plus Signal USB D-minus Signal Ball No. Type C5 D5 C4 D4 B4 D3 C3 D2 D1 B1 C2 C1 I/O I/O I/O I/O I/O I/O I/O I/O O O I O Voltage 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Clock ULPI Next Signal ULPI Stop Signal ULPI Direction Description ULPI Link Interface XI VCC VBATT VSS A2 I 1.8V 1.8V 3.0 - 5.775V 0V POWER and GROUND B5, A1 Power A5 B3 Power GND Document Number: 001-15775 Rev. *I Page 7 of 27 [+] Feedback CY7C68003 Figure 5. Pin Assignment - TX2UL 24-Pin QFN (Top View) VBATT VCC 19 DM 24 23 22 21 VSSBATT NC VCC DATA[0] DATA[1] DATA[2] 1 2 3 4 5 6 VSS (GND) Exposed die pad 20 XO DP XI 18 17 16 RESET_N NXT STP DIR CLOCK DATA[7] TX2UL 15 14 13 10 11 CS_N DATA[3] DATA[4] VIO DATA[5] Table 8. Pin Definitions - TX2UL 24-Pin QFN Name Pin No. ULPI Link Interface DATA[0] 4 DATA[1] 5 DATA[2] 6 DATA[3] 8 DATA[4] 9 DATA[5] 11 DATA[6] 12 DATA[7] 13 CLOCK 14 NXT 17 STP 16 DIR 15 USB DP 22 DM 23 Misc CS_N 7 RESET_N 18 Type I/O I/O I/O I/O I/O I/O I/O I/O O O I O I/O I/O I I Voltage 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V 1.8 - 3.3V USB USB 1.8 - 3.3V 1.8 - 3.3V 1.8V 1.8 - 3.3V 1.8V 1.8 - 3.3V 3.0 - 5.775V 0 0 ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Data to/from Link ULPI Clock ULPI Next Signal ULPI Stop Signal ULPI Direction USB D-plus Signal USB D-minus Signal When CS_N is de-asserted, all pins at ULPI interface are tri-stated Device Chip Global Reset. When RESET_N is asserted, TX2UL is in reset and enters into the power saving mode. Crystal or LVCMOS single ended clock of frequency 13, 19.2, 24, or 26 MHz Crystal No Connect Low voltage supply for the digital core Power for multi-range I/Os High voltage supply for USB USB Ground Digital Ground (Core and I/O) Page 8 of 27 Description XI 21 I XO 20 O NC 2 POWER and GROUND VCC 3, 19 Power VIO 10 Power VBATT 24 Power VSSBATT 1 GND VSS Die Paddle GND Document Number: 001-15775 Rev. *I DATA[6] 12 8 7 9 [+] Feedback CY7C68003 Synchronous Operation Modes This section describes the Synchronous Mode of TX2UL ULPI Interface protocol. ULPI Transmit Command Byte (TX CMD) The Link initiates transfers to TX2UL by sending the Transmit Command Byte as shown in Table 9. TX CMD byte consists of a 2-bit command code and a 6-bit payload. Table 9. Transmit Command (TX CMD) Byte Format Byte Name Special Command Code Data (7:6) 00b Command Payload Data (5:0) 000000b XXXXXXb Transmit 01b 000000b (NOOP) (RSVD) (NOPID) Command Description No operation. 00h is the idle value of the data bus. The Link drives NOOP by default. Reserved command space. Values other than those mentioned give undefined behavior. Transmit USB data that does not have a PID, such as chirp and resume signalling. The TX2UL starts transmitting on the USB beginning with the next byte. Transmit USB packet. data (3:0) indicates USB packet identifier PID (3:0) Reserved Command space. Values other than those mentioned give undefined behavior. Extended register write command. 8-bit address available in the next cycle. Register write command with 6-bit immediate address. Extended register read command. 8-bit address available in the next cycle. Register read command with 6-bit immediate address. 00XXXXb XXXXXXb (PID) (RSVD) RegWrite 10b 101111b XXXXXXb (EXTW) (REGW) (EXTR) (REGR) RegRead 11b 101111b XXXXXXb ULPI Receive Command Byte (RX CMD) The Receive Command Byte, as shown in Table 10, is sent by TX2UL to update the link with LineState and USB receive information. The USB receive information includes LineState, RxActive, and RxError. After a USB transmit, TX2UL sends RX CMD with LineState indicating EOP to the link. For High Speed, EOP is the squelch to squelch transition on LineState. Figure 7 on page 10 shows how TX2UL sends RX CMD information to the link. The first packet shows a single RX CMD. If back to back changes are detected, TX2UL keeps DIR asserted and sends back to back RX CMDs as shown in the second packet. Table 10. Receive Command (RX CMD) Byte Format Data 1:0 3:2 5:4 Name LineState Reserved RxEvent Encoded UTMI event signals Value 00 01 11 10 7:6 Reserved RxActive 0 1 1 X RxError 0 0 1 X Description and Value ULPI LineState signals. DATA[0] = LineState (0) DATA[1] = LineState (1) Document Number: 001-15775 Rev. *I Page 9 of 27 [+] Feedback CY7C68003 Figure 6. Sending RX CMD CLOCK DATA[7:0] Turn around RX CMD Turn around Turn around RX CMD RX CMD Turn around DIR STP NXT USB Data Transmit (NOPID) In this mode, the Link transmits data on the USB without a Packet Identifier (PID) by sending a TX CMD byte of the NOPID type. TX2UL asserts NXT (see Figure 8 on page 11) in the first cycle of TX CMD and deasserts NXT when it detects STP to be high. Because this command does not contain PID data, TX2UL waits for the next data byte before beginning transmission on the USB. When the last byte is transferred by the TX2UL, the link asserts STP for one cycle and drives data to 00h if no transmit errors occur. The link does not assert STP before the first byte is transferred by the TX2UL. Figure 7. USB Data Transmit (NOPID) CLOCK DATA[7:0] TX CMD (NOPID) D0 D1 D2 DIR STP NXT Document Number: 001-15775 Rev. *I Page 10 of 27 [+] Feedback CY7C68003 USB Data Transmit (PID) In this mode, the link transmits data on the USB with a Packet Identifier (PID). The link first drives a TX CMD byte as illustrated in Figure 9 on page 11 to transmit a USB packet. The link sets the Command Code to 01b (Transmit) and places the USB Packet Identifier (PID) on DATA[3:0] (see Table 9 on page 9). TX2UL throttles the data using NXT such that the link provides the next byte in the cycle after NXT is detected as high. Figure 8. USB Data Transmit (PID) CLOCK DATA[7:0] TX CMD (PID) D1 D2 D3 DIR STP NXT USB Packet Receive As shown in Figure 10 on page 12, when TX2UL receives the USB data it gains ownership of the data bus by asserting DIR. The DIR is previously either high or low. If DIR is low (see Figure 9), TX2UL asserts both DIR and NXT so that the link knows immediately that this is a USB receive packet. If DIR is high (see Figure 10 on page 12), TX2UL deasserts NXT and drives an RX CMD with the RxEvent field set to the RxActive state. The TX2UL starts driving data in the following cycle or outputs RX CMD until USB data is available. Valid USB packet data is presented to the link by asserting NXT and placing a byte on the bus. When NXT is low, TX2UL drives the RX CMD byte. All RX CMD changes during the USB packet receive are signaled when NXT is low. If NXT is never low during the packet receive, all RX CMD changes are replaced with a single RX CMD update. This update is sent at the end of the USB packet receive, when the ULPI bus is available. The RX CMD update always conveys the current RX CMD values and not the previous one. Figure 9. USB Receive While DIR is Previously Low CLOCK DATA[7:0] Turn around RX CMD PID D1 RX CMD D2 D3 Turn around DIR STP NXT Document Number: 001-15775 Rev. *I Page 11 of 27 [+] Feedback CY7C68003 Figure 10. USB Receive While DIR is Previously High CLOCK RX CMD (RxActive) DATA[7:0] Previous RX CMD PID D1 RX CMD D2 D3 Turn around DIR STP NXT Immediate Register Read and Write An immediate register is accessed by sending the TX CMD byte first (see Figure 11 and Figure 12 on page 13). This byte is sent as a regread or regwrite command, depending on the intended operation. For a register write (see Figure 11), the link first sends a register write TX CMD byte and waits for NXT to assert. After NXT asserts, the link sends the register write data and waits for NXT to assert again. After the second assertion is detected, the link asserts STP in the following cycle to complete the operation. The TX2UL detects this STP assertion before it can accept another transmit command. If the TX2UL aborts rewrite by asserting DIR, the link repeats the entire process again when the bus is idle. For a register read (see Figure 12 on page 13), the link sends a register read command and waits for NXT to assert. In the cycle after NXT asserts, the TX2UL asserts DIR to gain control of the data bus. In the cycle, after DIR asserts the TX2UL returns the register read data. The TX2UL does not assert NXT when DIR is asserted during the register read operation, even during the cycle when the register read data is returned. If the TX2UL aborts the regread by asserting DIR earlier than shown in Figure 12 on page 13, the link retries the regread when the bus is idle. Figure 11. Register Write CLOCK DATA[7:0] TX CMD (RegWrite) Data DIR STP NXT Document Number: 001-15775 Rev. *I Page 12 of 27 [+] Feedback CY7C68003 Figure 12. Register Read CLOCK TX CMD (RegRead) DATA[7:0] Turn around Data Turn around DIR STP NXT Immediate Register Read and Write Aborted by USB Receive A register read is the only instance where ULPI does not use NXT to acquire data. The NXT signal is asserted only during USB receive to distinguish this type of receive from other types of data transfers. Register read and write operations are aborted when the TX2UL sends a RX CMD, except during the cycle where register read data is returned to the link. TX2UL asserts both DIR and NXT whenever a register read or write is aborted by a USB receive during the initial Transmit Command byte or in the same cycle that the register read data returned to the link. Figure 13. Register Read or Write Aborted by USB Receive During TX CMD Byte RegRead or RegWrite USB Receive CLOCK TX CMD (Reg) DATA[7:0] Turn around RX CMD PID D1 D2 D3 DIR STP NXT Document Number: 001-15775 Rev. *I Page 13 of 27 [+] Feedback CY7C68003 Back to Back Immediate Register Read and Write and USB Receive When a USB receive occurs in the same cycle that the register read data is returned to the link, the TX2UL first returns the register read data, not a RX CMD byte (see Figure 14). When a USB receive occurs in the cycle immediately after a register read completes, the TX2UL places the USB receive data back-to-back with the register read (see Figure 15). The link accepts back-to-back packets where DIR does not deassert between packets. If DIR asserts during the same cycle that STP is asserted at the end of a register write, then the TX2UL considers the register write to have successfully executed (see Figure 16 on page 15). When a USB receive starts in the cycle after the register read data is returned to the link, it results in two cycles of bus turnaround when DIR deasserts for a single cycle (see Figure 17 on page 15). Figure 14. USB Receive in Same Cycle as Register Read Data. USB Receive is Delayed RegRead USB Receive CLOCK TX CMD (RegReg) DATA[7:0] Turn around Reg Data RX CMD (RxActive) PID D1 D2 DIR STP NXT Figure 15. Register Read Followed Immediately by a USB Receive RegRead USB Receive CLOCK TX CMD (RegReg) DATA[7:0] Turn around Reg Data RX CMD (RxActive) PID D1 D2 DIR STP NXT Document Number: 001-15775 Rev. *I Page 14 of 27 [+] Feedback CY7C68003 Figure 16. Register Write Followed Immediately by a USB Receive During STP Assertion RegWrite USB Receive CLOCK TX CMD (RegReg) DATA[7:0] Data Turn around RX CMD (RxActive) PID D1 D2 DIR STP NXT Figure 17. Register Read Followed by a USB Receive RegRead USB Receive CLOCK TX CMD (RegReg) DATA[7:0] Turn around Reg Data Turn around Turn around PID D1 DIR STP NXT Document Number: 001-15775 Rev. *I Page 15 of 27 [+] Feedback CY7C68003 Configuration Mode TX2UL is configured in the input clock type and frequency for the XI and XO in Configuration Mode. The 20-pin CSP package and 24-pin QFN package have different procedures to enter the Configuration Mode. options are listed in Table 11. The TX2UL is defaulted to 26 MHz with single end clock input (to XI). Table 11. TX2UL Configuration Options Number of Pulses at RESET_N Pin during Configuration Mode 0 pulses 1 pulses 2 pulses 3 pulses 4 pulses 5 pulses 6 pulses 7 pulses Configuration Description 26 MHz clock input on XI (default) 19.2 MHz clock input on XI 24.0 MHz clock input on XI 13.0 MHz clock input on XI 26 MHz crystal on XI/XO 19.2 MHz crystal on XI/XO 24.0 MHz crystal on XI/XO 13.0 MHz crystal on XI/XO Configuration Mode in 20-Pin CSP package To enter the Configuration Mode keep the RESET_N low during VCC Power On for tSTATE (see Figure 19 on page 22 for the timing diagraming and Table 21 on page 21 for the tSTATE timing requirement). When TX2UL enters the Configuration Mode, the Peripheral Controller (Link device) generates the pulses (falling edge) at the RESET_N pin to configure TX2UL. TX2UL configures its internal oscillator base on number of received pulses at the RESET_N pin. When the configuration is completed, deassert RESET_N (high) for tSTATE to exit the Configuration. If the TX2UL needs to enter the Configuration Mode again, it must go through the following power cycle: VCC Off ℜ→ RESET_N Low ℜ→ VCC On. Configuration Mode in 24-Pin QFN package To enter the Configuration Mode keep the RESET_N pin pulled low for tSTATE (see Figure 20 on page 22 for the timing diagraming and Table 21 on page 21 for the tSTATE timing requirement) while deasserting CS_N (high). When TX2UL enters the Configuration Mode, the Peripheral Controller (Link device) generates the pulses (falling edge) at the RESET_N pin to configure TX2UL. TX2UL configures its internal oscillator base on number of received pulses at the RESET_N pin. When the configuration is completed, assert the CS_N (low) for tSTATE (see Figure 21 on page 21 for the timing) to exit the Configuration Mode. Figure 19 on page 22 shows the timing diagram of entering and exiting the Configuration Mode. The configuration Power On Reset (POR) TX2UL has an internal Power On Reset (POR) block that provides power on reset and Power Management Control functionality. This POR function complies with all the parameters required by the ULPI specification. Register TX2UL provides an immediate register set that is defined by the ULPI specification for control and configuration functions. Register Map The ULPI specifications define an immediate register set with a 6-bit address that forms a part of the Transmit Command Byte,as shown in shown in Table 12. Table 12. Register Map Field Name Immediate Register Set Vendor ID Low Vendor ID High Product ID Low Product ID High Function Control Interface Control Debug Scratch Register Carkit Control (Optional) Vendor Specific Register Set Drive Strength and Slew Rate USB Interface Control Register 8 8 31h 35h 31h 35h 8 8 8 8 8 8 8 8 8 00h 01h 02h 03h 04-06h 07-09h 15h 16-18h 19-1Bh 04h 07h 16h 19h 05h 08h 17h 1Ah 06h 09h 18h 1Bh Size (bits) Rd Address (6bits) Wr Set Clr Document Number: 001-15775 Rev. *I Page 16 of 27 [+] Feedback CY7C68003 Table 13 to Table 17 on page 18 define the read, write, set, and clear register options. The following are the conventions: ■ ■ ■ ■ Rd or rd = Read Wr or wr = Write Set or s = Set Clr or c = Clear Immediate Register Set The details of all immediate registers of TX2UL are shown in Table 6 on page 6, Table 18 on page 19, and Table 20 on page 21. Function Control Register Control ULPI Function Setting of TX2UL Table 13. Function Control Register (Address: 04h - 06h [read], 04h [write], 05h [set], 06h [clear]) Bit 1:0 Field Name XcvrSelect Description Selects the required transceiver speed. 00b: Enable HS transceiver 01b: Enable FS transceiver 10b: Reserved 11b: Enable FS transceiver for LS packets. Controls the internal 1.5K pull up resistor and 45 HS terminations. Access rd/wr/s/c Reset Value 01b 2 4:3 TermSelect OpMode rd/wr/s/c 0b 00b Selects the required bit encording style during transmit. rd/wr/s/c 00b: Normal operation 01b: Non-driving 10b: Disable bit stuff and NRZI encoding 11b: Do not automatically add SYNC and EOP when transmitting. It is used only for HS packets. Active high transceiver reset. After the link sets this bit, TX2UL asserts rd/wr/s/c DIR and resets ULPI core. When the reset is completed, DIR is de-asserted and automatically clears this bit. After de-asserting DIR, TX2UL re-asserts DIR and sends and RX CMD update to the link. The link waits for DIR to de-assert before using ULPI bus. It does not reset the ULPI interface or ULPI register set. Active low. Put TX2UL into Low Power Mode. TX2UL powers down all rd/wr/s/c blocks except the full speed receiver and ULPI interface pins. TX2UL sets this bit to ‚Äú1‚Äù when exits from Low Power Mode. 0b: Enter into Low Power Mode 1b: Normal Operation Mode rd 5 Reset 0b 6 SuspendM 1b 7 Reserved x Document Number: 001-15775 Rev. *I Page 17 of 27 [+] Feedback CY7C68003 Interface Control Register This register enables alternative interface and TX2UL features. Table 14. Interface Control Register (Address: 07h - 09h [read], 07h [write], 08h [set], 09h [clear]) Bit 1:0 2 Field Name Reserved CarkitMode Description Access rd Changes the ULPI interface to carkit interface that support UART pass rd/wr/s/c through mode. This bit is cleared when it exits from carkit UART pass through mode. 0b: Disable serial carkit mode 1b: Enable serial carkit mode rd Controls circuitry built into TX2UL for protecting the ULPI interface when rd/wr/s/c the link tristates STP and DATA[7:0]. Any pull ups or pull downs employed by this feature are disabled 0b: Enable the Interface Protect Circuit 1b: Disable the Interface Protect Circuit Reset Value xxb 0b 6:3 7 Reserved Interface Protect Disable xxxxb 0b Debug Register This register indicates the current value of various signals useful for debugging. Table 15. Debug Register (Address: 15h [read only]) Bit 0 1 7:2 Field Name LineState0 LineState1 Reserved Description Contains the current value of LineState(0) Contains the current value of LineState(1) Access rd rd rd Reset Value 0b 0b 000000b Scratch Register This register is for testing purpose only. The link can read, write, set and clear this register. Table 16. Scratch Register (Address: 16h - 18h [read], 16h [write], 17h [set], 18h [clear]) Bit 7:0 Field Name Scratch Description Access Reset Value 00000000b Empty register byte for testing purposes. The link software reads, writes, rd/wr/s/c sets, and clears this register. Carkit Control Register This register controls the TXD and RXD in carkit UART pass through mode. It has no control function if the CarkitMode bit in Interface Control Register is not set. Table 17. Carkit Control Register (Address: 19h - 1Bh [read], 19h [write], 1Ah [set], 1Bh [clear]) Bit 1:0 2 3 7:4 Field Name Reserved TxdEn RxdEn Reserved Routes TXD signal from DATA[0] pin to DM pin Routes RXD signal from DP pin to DATA[1] pin Description Access rd rd/wr/s/c rd/wr/s/c rd Reset Value xxb 0b 0b xxxxb Document Number: 001-15775 Rev. *I Page 18 of 27 [+] Feedback CY7C68003 Drive Strength and Slew Rate Configuration Register This register is mapped to the vendor specific registers address. This register configures the drive strength and slew rate of the outputs. Table 18. Drive Strength and Slew Rate Configuration Register (Address: 31h [read], 31h [write]) Bit 1:0 Field Name DriveStrength Description Configure the drive strength on the output pins 00b: Full drive strength 01b: Three quarter drive strength 10b: half drive strength 11b: Quarter drive strength Configure the slew rate on the output pins 0b: slow slew rate 1b: fast slew rate Access rd/wr Reset Value 00b 2 SlewRate rd/wr 0b 7:3 Reserved rd 00000b USB Interface Control Register This register is mapped to the vendor specific registers address. This register enables or disables the USB interface. Table 19. USB Interface Control Register (Address: 35h [read], 35h [write]) Bit 1:0 2 7:3 Field Name Reserved UsbEnable Reserved USB Interface Control 0b: Disable USB interface 1b: Enable USB interface When write to this register, this field must be filled in 0s Description When write to this register, this field must be filled in 0s Access rd rd/wr rd Reset Value 00b 0b 00000b Document Number: 001-15775 Rev. *I Page 19 of 27 [+] Feedback CY7C68003 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature .................................... 65°C to +150°C Ambient Temperature with Power Supplied (Industrial) ............................ 40°C to +85°C Supply Voltage to Ground Potential VCC ..................................................................0.5V to +2.0V VIO ...................................................................0.5V to +4.0V VBATT ..........................................................0.5V to +5.775V DC Input Voltage to Any Input Pin ....................1.89V to 3.6V Depends on I/O supply voltage. Inputs are not over voltage tolerant. DC Voltage Applied to Outputs in High Z State ............................ 0.5V to VCC+0.5V Static Discharge Voltage (ESD) from JESD22-A114> 2000 V Latch Up Current .................................................... > 200 mA Maximum Output Short Circuit Current for all I/O Configurations. (Vout = 0V)........................ 100 mA Operating Conditions TA (Ambient Temperature Under Bias) Industrial ......................................................... 40°C to +85°C VCC Supply Voltage ...........................................1.7V to 1.9V VIO Supply Voltage ............................................1.7V to 3.6V VBATT Supply Voltage ...................................3.0V to 5.775V Document Number: 001-15775 Rev. *I Page 20 of 27 [+] Feedback CY7C68003 DC Characteristics Table 20. DC Specifications for All Voltage Supplies Parameter VCC VIO Description Core Voltage Supply ULPI Interface I/O Voltage Supply (this I/O supply is not available on 20-Ball WLCSP package) Crystal Voltage Supply Power on reset trip Voltage Input HIGH Voltage 1 Input HIGH Voltage 2 Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Supply Current IOH(MAX) = 0.1 mA IOL(MIN) = 0.1 mA All I/O signals held at VDDQ All I/O signals held at VDDQ Continuous Receive Continuous Transmit ULPI Low Power Mode (Suspend) VCC = 1.8 V Sleep Mode - ULPI interface bus is either Hz or drive High - DP and DM must be Hz or pull Low IPU IPD Pull up current Pull down current Interface protect enabled; STP pin only; VI = 0V Interface protect enabled; DATA[7:0] only; VI = VIO -13 16 1 1 30 30 300 All ports except USB, 2.0V < VIO < 3.6V All ports except USB, 1.7V < VIO < 2.0V Conditions Min 1.7 1.7 Typ 1.8 1.8, 2.5, 3.3 Max 1.9 3.6 Unit V V VBATT VPOR(trip) VIH1 VIH2 VIL VOH VOL IIX IOZ ICC 3.0 1.0 0.625*VIO VIO‚ 0.4 0.3 0.9*VIO 5.775 1.5 VIO + 0.3 VIO + 0.3 0.25*VIO 0.1*VIO 1 1 65 65 750 V V V V V V V μA μA mA mA μA 5 40 μA -80 90 μA μA AC Characteristics Table 21. ULPI Timing Parameters Parameter tCS tDS tCH tDH tCD tDD tSTATE tPW Setup time for control input Setup time for data input Hold time for control input Hold time for data input Output delay time for control output Output delay time for data output Mode state change time Pulse width Description Min 5.8 5.8 0 0 7.6 7.6 500 200 10000 9.0 9.0 Max Unit ns ns ns ns ns ns μs ns Document Number: 001-15775 Rev. *I Page 21 of 27 [+] Feedback CY7C68003 Figure 18. ULPI Timing Diagram CLOCK tCS tCH Control In (STP) tDS tDH DATA[7:0] In tCD tCD Control out (DIR, NXT) tDD tDD DATA [7:0] Out Figure 19. 20-Pin CSP Package Configuration Mode Entry Timing Diagram Exiting From Entering into Configuration Configuration Mode Mode Configuration Mode tSTATE VCC tPW tPW RESET_N tPW tSTATE Normal Operation Mode Configuration Pulses (falling edge) Figure 20. 24-Pin QFN Package Configuration Mode Entry Timing Diagram VCC Entering into Configuration Mode tSTATE Configuration Mode Exiting From Configuration Normal Operation Mode Mode tSTATE CS_N tPW tPW RESET_N Configuration Pulses (falling edge) Document Number: 001-15775 Rev. *I Page 22 of 27 [+] Feedback CY7C68003 Figure 21. AC Test Loads and Waveforms Figure 22. Connecting 20-Ball WLCSP Package TX2UL with a Standard Peripheral Controller with External Clock 1.8V 3.3 – 5.775V VBATT B5 A5 Peripheral Controller CLOCK DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DIR NXT STP RESET_N CLOCK DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DIR NXT STP RESET_N D1 C5 D5 C4 D4 B4 D3 C3 D2 C1 B1 C2 B2 VCC A1 USB Connector A4 DM A3 DP TX2UL CSP Package DM 2 DP 3 4 A2 XI 13/19.2/24/26 MHz External Clock B3 VSS Document Number: 001-15775 Rev. *I Page 23 of 27 [+] Feedback CY7C68003 Ordering Information Ordering Code CY7C68003-20FNXI CY7C68003-24LQXI CY7C68003-24LQXIT Package Type 20-Ball WLCSP 24-Pin QFN 24-Pin QFN Tape and Reel Support Clock Input Frequencies (MHz) 13, 19.2, 24, 26 13, 19.2, 24, 26 13, 19.2, 24, 26 Package Diagram Figure 23. 20-Pin WLCSP Package Outline 001-13856 *B Document Number: 001-15775 Rev. *I Page 24 of 27 [+] Feedback CY7C68003 Figure 24. 24-Pin QFN Package Outline 001-13937 *C Document Number: 001-15775 Rev. *I Page 25 of 27 [+] Feedback CY7C68003 Document History Page Document Title: CY7C68003 MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver Document Number: 001-15775 Revision ** *A ECN 1094246 1188703 Orig. of Change VSO, XVA VSO Submission Date See ECN See ECN Initial Release Update the tSTATE min requirement (from 200 us to 500us) in Table 21 Section Sleep Mode add (see Table 21 for tSTATE requirement) Section of Operating Conditions (page 19), the second VCC corrected to VIO. Table 19, the reference voltage for the VIH1, VIH2, VIL, VOH, and VOL has corrected from VCC to VIO. Change in Ordering Information. Update the ESD description in the features list. Updated the description of section ‚ÄúPower Supply Sequence‚Äù Updated the section of Chip Section (CS_N) Updated the section of Operation Modes - tri-state mode only available in 24-pin QFN package Updated Figure 3. Added Table 4. Updated Figure 4 and Table 7 (CSP pin assignment has been changed) Updated the section of Configuration Mode Correct the hyper link section of Immediate Register Description of Change *B *C 1505863 2081867 VSO/AESA VSO/AESA See ECN See ECN Set Correct the word of ‚ÄúReserved‚Äù in Table 14 Updated ULPI Timing Parameters table (table-21) Updated ULPI Timing Diagram (figure 18) Added Figure 19. Removed USB Interface Control Register section and table in page 19 Updated Figure 22. *D 2552066 VSO 08/13/2008 In the first page, feature list, update the CSP dimension from ‚Äú2.2 x 1.8 mm‚Äù to ‚Äú2.14 x 1.76 mm‚Äù. Updated Table 12 Add USB Interface Control Register section Removed PRELIMINARY in master pages (turn into Final data sheet). Updated data sheet template. Updated Ordering Information table. In the Clocking section, added a bullet ‚Äò150 ppm‚Äô. Table 3: ❐ changed PN_DC to PN_100 ❐ changed DC to 100 ❐ change the unit of dB to dBc/Hz ❐ added a row of ‚ÄúMaximum Frequency Deviation‚Äù Updated Suspend current in Table 20 (clarified VCC = 1.8V). Changed all TX3, TX3LP18 to TX2UL Posting to external web. Added “Suport USB Device Mode only” in the Feature section. Added table of conetnts. Updated links in Sales, Solutions, and Legal Information. Page 26 of 27 *E 2597682 VSO/AESA 10/28/2008 *F 2671871 VSO/PYRS 03/13/2009 *G *H 2765711 2920278 TIK/RADH VSO/AESA 09/18/2009 04/21/2010 Document Number: 001-15775 Rev. *I [+] Feedback CY7C68003 Document History Page (continued) Document Title: CY7C68003 MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver Document Number: 001-15775 Revision *I ECN 3035786 Orig. of Change HBM Submission Date 09/22/2010 Description of Change Post to external web. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress‚Äô product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-15775 Rev. *I Revised September 22, 2010 Page 27 of 27 MoBL-USB is a trademark of Cypress Semiconductor. All other products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback