CY7C68003
MoBL-USB™ TX2UL USB 2.0
ULPI Transceiver
MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver
Features
■
UART pass through mode
The Cypress MoBL-USB™ TX2UL is a low voltage high speed
(HS) USB 2.0 UTMI+ Low Pin Interface (ULPI) Transceiver. The
TX2UL is specifically designed for mobile handset applications
by offering tiny package options and low power consumption.
■
ESD compliance:
❐ JESD22-A114D 8 kV Contact human body model (HBM) for
DP, DM, and VSS pins
❐ IEC61000 - 4-2 8 kV contact discharge
❐ IEC61000 - 4-2 15 kV air discharge
■
Support for industrial temperature range: (-40 °C to 85 °C)
■
Low power consumption for mobile applications:
❐ 5 µA nominal sleep mode
❐ 30 mA nominal active HS transfer
■
Small package for mobile applications:
❐ 2.14 x 1.76 mm 20-pin WLCSP 0.4 mm pitch
❐ 4 x 4 mm 24-pin QFN
■
USB 2.0 Full Speed and High Speed compliant transceiver
■
Multi range (1.8 V to 3.3 V) I/O voltages
■
Fully compliant ULPI link interface
■
8-bit SDR ULPI data path
■
UTMI+ level 0 support
■
Support USB device mode only
■
Integrated oscillator
■
Integrated phase locked loop (PLL) – 13, 19.2, 24, or 26 MHz
reference
■
Applications
■
Mobile phones
Integrated USB pull-up and termination resistors
■
PDAs
■
3.0 V to 5.775 V VBATT input
■
Portable media players (PMPs)
■
Chip select pin
■
DTV applications
■
Single ended device RESET input
■
Portable GPS units
TX2UL Block Diagram
TX2UL
ULPI Block
CLOCK
DATA[7:0]
DIR
STP
I/O
Control/
Data
Logic
Operational
mode
tracking
interrupt
Tx/Rx
Core
UTMI+
Level0
Registers
Block
ULPI Wrapper
NXT
DP
USB
FS/HS
PHY
DM
RXD
TXD
RESET_N
CS_N
(3.0 –
5.775 V)
13/19.2/
24/26 MHz
Global Control Block
Reset / Clock / Power /
Misc. Control
3.3 V
Regulator
Block
VBATT
VCC
(1.8 V)
POR
XI
XO
Cypress Semiconductor Corporation
Document Number: 001-15775 Rev. *O
XOSC
•
1.8 V
Bandgap
PLL
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 30, 2017
CY7C68003
Contents
Functional Overview ........................................................ 3
UTMI+ Low Pin Interface (ULPI) ................................. 3
Oscillator (OSC) .......................................................... 3
Phase Locked Loop (PLL) ........................................... 3
Power On Reset (POR) ............................................... 3
Reset (RESET_N) ....................................................... 3
DP and DM pins .......................................................... 3
Chip Select (CS_N) ..................................................... 3
USB2 Transceiver Macrocell Interface (UTMI+) .......... 3
Global Control ............................................................. 3
Full Speed
and High Speed USB Transceivers (FS/HS) ...................... 3
USB Pull up and Intr Detect,
Termination Resistors (Pull up/TERM) ............................... 3
UART Pass Through Mode ......................................... 3
Clocking ....................................................................... 4
Power Domains ........................................................... 4
Operation Modes ......................................................... 5
VID and PID ................................................................ 6
Pinouts .............................................................................. 7
Synchronous Operation Modes ...................................... 9
ULPI Transmit Command Byte (TX CMD) .................. 9
ULPI Receive Command Byte (RX CMD) ................... 9
USB Data Transmit (NOPID) ..................................... 10
USB Data Transmit (PID) .......................................... 11
USB Packet Receive ................................................. 11
Immediate Register Read and Write ......................... 12
Immediate Register Read and Write
Aborted by USB Receive .................................................. 13
Back to Back Immediate Register Read and Write
and USB Receive ............................................................. 14
Document Number: 001-15775 Rev. *O
Configuration Mode ........................................................ 16
Configuration Mode in 20-Pin CSP package ............. 16
Configuration Mode in 24-Pin QFN package ............. 16
Power On Reset (POR) ............................................. 16
Register ..................................................................... 16
Register Map ............................................................. 16
Immediate Register Set ............................................. 17
Function Control Register .......................................... 17
Interface Control Register ......................................... 18
Debug Register ......................................................... 18
Scratch Register ........................................................ 18
Carkit Control Register .............................................. 18
Drive Strength
and Slew Rate Configuration Register ............................. 19
USB Interface Control Register ................................. 19
Absolute Maximum Ratings .......................................... 20
Operating Conditions ..................................................... 20
DC Characteristics ......................................................... 21
AC Characteristics ......................................................... 21
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagrams .......................................................... 25
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC® Solutions ...................................................... 30
Cypress Developer Community ................................. 30
Technical Support ..................................................... 30
Page 2 of 30
CY7C68003
Functional Overview
USB2 Transceiver Macrocell Interface (UTMI+)
UTMI+ Low Pin Interface (ULPI)
This block conforms to the UTMI+ Level 0 standard. It performs
all the UTMI to USB translation.
This block conforms to the ULPI specification. It supports the
8-bit wide SDR data path. The primary I/Os of this block support
multi-range LVCMOS signaling from 1.8 V to 3.3 V (±5%). The
level used is automatically selected by the voltage applied to
VCCIO and is set at any voltage between 1.8 V and 3.3 V.
Oscillator (OSC)
This block meets the requirements of both the on-chip PLL and
the USB-IF requirements for clock parameters. It is a
fundamental mode parallel resonant oscillator with a maximum
ESR of 60 Ω. It supports the following:
■
Integrated Crystal Oscillator – 13, 19.2, 24, or 26 MHz crystal
■
13, 19.2, 24, or 26 MHz LVCMOS single ended input clock on XI
Phase Locked Loop (PLL)
The PLL meets all clock stability requirements imposed by this
device and the USB standard. It supports all requirements to
make the device compliant to the USB 2.0 specifications. It also
has a fractional multiplier that enables it to supply the correct
frequency to the device when it is presented with a 13, 19.2, 24,
or 26 MHz reference clock.
Power On Reset (POR)
This block provides a POR signal (internal) based on the input
supply. An internal POR is generated when VCC input rises
above VPOR(trip).
Reset (RESET_N)
The three major functions of RESET_N pin are as follows:
■
Reset TX2UL
■
Place TX2UL into Sleep Mode
■
Place TX2UL into Configuration Mode
When the RESET_N pin is asserted (low) for tSTATE (tSTATE is
specified in Table 21 on page 21), the TX2UL enters either Sleep
Mode or Configuration Mode depending on the CS_N state.
When RESET_N is asserted while CS_N is asserted, TX2UL
enters Sleep Mode. When RESET_N is asserted for tSTATE
while CS_N is deasserted, TX2UL enters Configuration Mode. In
these modes, all the pins in the ULPI interface are tristated. If the
RESET_N pin is not used, it must be pulled high. For information
about different modes of configuration, see Table 5 on page 5.
DP and DM pins
The DP and DM pins are the differential pins for the USB. They
must be connected to the corresponding DP and DM pins of the
USB receptacle.
Chip Select (CS_N)
Global Control
This block is the digital control logic that ties the blocks of the
device together. Its functions include pull up control, over current
protect control, and more.
Full Speed and High Speed USB Transceivers (FS/HS)
The FS and HS Transceivers comply fully with the USB 2.0
specifications.
USB Pull up and Intr Detect, Termination Resistors
(Pull up/TERM)
These blocks contain the USB pull-up and termination resistors
as specified by the USB 2.0 specification.
UART Pass Through Mode
TX2UL supports Carkit UART Pass Through Mode. When the
Carkit Mode bit in the Interface Control register is set, it enables
the Link to communicate through the DP/DM to a remote system
using UART signaling. By default, the clock is powered down
when the TX2UL enters Carkit Mode. Entering and exiting the
Carkit Mode is identical to the Serial Mode. Table 1, Table 2, and
Figure 1 show the UART Signal Mapping between the DP/DM
and DATA[1:0] at ULPI interface.
Table 1. UART Signal Mapping at ULPI Interface
Signal
Maps to
Direction
txd
DATA[0]
IN
UART TXD signal
routed to DM pin
Description
rxd
DATA[1]
OUT
UART RXD signal
routed to DP pin
Reserved
DATA[7:2]
-
Reserved
Table 2. UART Signal Mapping at USB Interface
Signal
Maps to
Direction
Description
TXD
DM
OUT
UART TXD signal
RXD
DP
INT
UART RXD signal
Figure 1. UART Signal Mapping in Pass Through Mode
USB
INTERFACE
ULPI
INTERFACE
txd
rxd
DATA[0]
DATA[1]
TX2UL
DM
TXD
DP RXD
This signal pin is available only in 24-pin QFN package. The two
major functions of CS_N are as follows:
■
Tristate the ULPI bus output pins
■
Associate with RESET_N to place TX2UL in the Sleep mode
When the CS_N pin is deasserted (high), all the pins in the ULPI
interface are tristated.
Document Number: 001-15775 Rev. *O
Page 3 of 30
CY7C68003
Clocking
TX2UL supports external crystal and clock inputs at the 13, 19.2,
24, and 26 MHz frequencies. The internal PLL applies the proper
clock multiply option depending on the input frequency. For applications that use an external clock source to drive XI, the XO pin
(in the 24-pin QFN package) is left floating. TX2UL has an
on-chip oscillator circuit that uses an external 13, 19.2, 24, or
26 MHz (±100 ppm) crystal with the following characteristics:
■
Parallel resonant
Fundamental mode
■
750 µW drive level
■
The selection between input clock source and frequency on the
XI pin is determined by the Chip Configuration register loaded
through the RESET_N during Configuration Mode. The external
clock source requirements are shown in Figure 3 on page 5.
Figure 2. Crystal Configuration
TX2UL
XI
XTAL
■
12 pF (5 percent tolerance) load capacitors
■
150 ppm
PLL
XO
12 pf
12 pf
TX2UL operates on one of two primary clock sources:
■
■
LVCMOS square wave clock input driven on the XI pin
Crystal generated sine wave clock on the XI and XO pins
* 12 pF capacitor values assumes a trace capacitance of
3 pF per side on a four layer FR4 PCA
Table 3. External Clock Requirements
Parameter
Description
Specification
Min
Max
Unit
Vn
Supply voltage noise at frequencies < 50 MHz
–
20
mV p-p
PN_100
Input phase noise at 100 Hz
–
75
dBc/Hz
PN_1k
Input phase noise at 1 kHz offset
–
104
dBc/Hz
PN_10k
Input phase noise at 10 kHz offset
–
120
dBc/Hz
PN_100k
Input phase noise at 100 kHz offset
–
128
dBc/Hz
PN_1M
Input phase noise at 1 MHz offset
–
130
dBc/Hz
Duty cycle
30
70
%
Maximum frequency deviation
–
150
ppm
Power Domains
VBATT
The TX2UL has three power supply domains:
■
VCC
This is the battery input supply that powers the 3.3 V regulator
block. It can range anywhere from 3.0 to 5.775 V during actual
operation.
■
VIO
Voltage Regulator
■
VBATT
TX2UL has two grounds:
■
VSS
■
VSSBATT
VCC
This is the core 1.8 V power supply for the TX2UL. It can range
anywhere from 1.7 V to 1.9 V during actual operation.
VIO
This is the 1.8 V to 3.3 V multi range supply to the I/O ring. It can
range anywhere from 1.7 V to 3.6 V during actual operation.
Document Number: 001-15775 Rev. *O
The internal 3.3 V regulator block regulates the VBATT supply to
the internal 3.3 V supply for the USBIO and XOSC blocks. If the
supply voltage at VBATT is below 3.3 V, the regulator block
switches the VBATT supply directly for the USBIO and XOSC
blocks.
Power Supply Sequence
TX2UL does not require a power supply sequence. All power
supplies are independently sequenced without damaging the
part. All supplies are up and stable for the device to function
properly. The analog block contains circuitry that senses the
power supply to determine when all supplies are valid.
Page 4 of 30
CY7C68003
Operation Modes
There are six operation modes available in TX2UL. They are:
■
Normal operation mode
■
Configuration mode
■
ULPI low power mode
■
Sleep mode
■
Carkit UART pass through mode
■
Tristate ULPI interface output mode (only available in 24-pin
QFN package)
When changing the operation modes, if the current and changing
modes are not the normal operation Mode, TX2UL first changes
to the normal operation mode. For example, to change from
ULPI low power mode to Sleep mode, TX2UL changes to normal
operation mode first, and then to Sleep mode. The Mode Change
State diagram in Figure 3 shows the mode change path of
TX2UL. The entries of the six operations modes (20-pin CSP
package has five operation modes) are listed in Table 4 and
Table 5. There are three mode change transactions that require
the RESET_N assert or deassert with tSTATE (see Table 21 on
page 21 for tSTATE). The three mode change transactions are:
■
Change from normal operation mode to configuration mode;
RESET_N is required to assert with tSTATE
■
Change from configuration mode to normal operation mode;
RESET_N is required to de-assert with tSTATE
■
Change from normal operation mode to sleep mode; RESET_N
is required to assert with tSTATE
Figure 3. Mode Change State Diagram
Carkit UART Pass Through
Mode
Sleep Mode
Tristate ULPI Interface Output
Mode (available in 24-pin QFN
package only)
Normal Operation Mode
Configuration Mode
Table 4. TX2UL 20-Pin CPS Package Operation Modes
RESET_N
Mode
ULPI Low Power Mode
Table 5. TX2UL 24-Pin QFN Package Operation Modes
CS_N
RESET_N
0 (Low)
Sleep mode
0 (Low)
0 (Low)
1 (High)
Normal operation mode
0 (Low)
1 (High)
Normal operation mode
1 (High)
Enter into ULPI low power mode by setting
SuspendM register bit (in Function Control
Register) to 0 during the normal operation mode.
0 (Low)
1 (High)
1 (High)
Enter into Carkit UART pass through mode by
setting Carkit mode register bit (in Interface Control
Register) to 1 during the normal operation mode.
Enter into ULPI low power mode by
setting SuspendM register bit (in
Function Control Register) to 0
during the normal operation mode.
0 (Low)
1 (High)
Enter into Carkit UART pass
through mode by setting Carkit
Mode register bit (in Interface
Control Register) to 1 during the
normal operation mode.
Enter into Configuration Mode
0 (Low)
when
Power On
(VCC On)
Document Number: 001-15775 Rev. *O
Mode
Sleep mode
1 (High)
0 (Low)
Configuration mode
1 (High)
1 (High)
Tristate ULPI interface output pins
Page 5 of 30
CY7C68003
The operation and configuration modes are described in the
sections Operation Modes on page 5 and Configuration Mode on
page 16 respectively. The ULPI low power mode and Sleep
mode are described in the following sections.
ULPI Low Power Mode
In this mode, the link optionally places the TX2UL in low power
mode when the USB is suspended. TX2UL powers down all the
circuitry except for the interface pins and full speed receiver. To
enter low power mode, the link must set SuspendM in the
Function Control register to 0b. The TX2UL clock is stopped for
a minimum of five cycles after TX2UL accepts the register write.
To exit low power mode, the link signals TX2UL to exit the mode
by asynchronously asserting a signal, STP. The TX2UL wakes
up its internal circuitry and when it meets the ULPI timing requirements, it deasserts DIR. The SuspendM register is set to 1b.
Table 21 on page 21 for tSTATE requirement) while CS_N is low,
TX2UL enters Sleep Mode. VCC must remain supplied (ON)
during the sleep mode. This mode powers down all internal
circuitry except the RESET_N pin and the chip_config register.
The ULPI interface bus is tristated.
During the Sleep Mode ensure that:
■
The ULPI interface I/Os are either floating or driven high by the
link
■
DP and DM are either floating or pull to 0 V
■
Deassert RESET_N to exit the Sleep Mode
Sleep Mode
Sleep mode is entered by asserting RESET_N during the Normal
Operation Mode. When RESET_N is driven low for tSTATE (see
VID and PID
The VID and PID are hard coded into Product ID and Vendor ID registers (read only) as shown in Table 6.
Table 6. Immediate Register Values for VID and PID
Field Name
Size (bit)
Address (6 bits)
Rd
Wr
Set
Clr
Value
Vendor ID (VID) Low
8
00h
-
-
-
B4h
Vendor ID (VID) High
8
01h
-
-
-
04h
Product ID (PID) Low
8
02h
-
-
-
03h
Product ID (PID) High
8
03h
-
-
-
68h
Document Number: 001-15775 Rev. *O
Page 6 of 30
CY7C68003
Pinouts
TX2UL is available in 20-ball WLCSP and 24-pin QFN package. The pin assignment is shown in Figure 4 and Figure 5
Figure 4. Pin Assignment - TX2UL 20-Ball WLCSP (Top View)
1
2
3
4
5
A
A1
VCC
A2
XI
A3
DP
A4
DM
A5
VBATT
B
B1
NXT
B2
RESET_N
B3
VSS
B4
DATA[4]
B5
VCC
C
C1
DIR
C2
STP
C3
DATA[6]
C4
DATA[2]
C5
DATA[0]
D
D1
CLOCK
D2
DATA[7]
D3
DATA[5]
D4
DATA[3]
D5
DATA[1]
Table 7. Pin Definitions - TX2UL 20-Ball WLCSP
Name
Ball No. Type
Voltage
Description
ULPI Link Interface
DATA[0]
C5
I/O
1.8 V
ULPI data to/from link
DATA[1]
D5
I/O
1.8 V
ULPI data to/from link
DATA[2]
C4
I/O
1.8 V
ULPI data to/from link
DATA[3]
D4
I/O
1.8 V
ULPI data to/from link
DATA[4]
B4
I/O
1.8 V
ULPI data to/from link
DATA[5]
D3
I/O
1.8 V
ULPI data to/from link
DATA[6]
C3
I/O
1.8 V
ULPI data to/from link
DATA[7]
D2
I/O
1.8 V
ULPI data to/from link
CLOCK
D1
O
1.8 V
ULPI clock
NXT
B1
O
1.8 V
ULPI next signal
STP
C2
I
1.8 V
ULPI stop signal
DIR
C1
O
1.8 V
ULPI direction
USB
DP
A3
I/O
USB
USB D-plus signal
DM
A4
I/O
USB
USB D-minus signal
RESET_N
B2
I
1.8 V
Global reset. When RESET_N is asserted during the VCC power on, TX2UL enters
configuration mode. During normal operation mode, asserting RESET_N resets the
TX2UL and enter into the power saving mode.
XI
A2
I
1.8 V
LVCMOS single ended clock of frequency 13, 19.2, 24, or 26 MHz
1.8 V
Low voltage supply for the digital core and I/O
Miscellaneous
POWER and GROUND
VCC
B5, A1 Power
VBATT
A5
VSS
B3
Power 3.0 - 5.775 V High voltage supply for USB
GND
Document Number: 001-15775 Rev. *O
0V
Common ground
Page 7 of 30
CY7C68003
VSSBATT
VBATT
DM
DP
XI
XO
VCC
24
23
22
21
20
19
Figure 5. Pin Assignment - TX2UL 24-Pin QFN (Top View)
1
NC
2
VCC
3
VSS (GND)
Exposed die pad
TX2UL
18
RESET_N
17
NXT
16
STP
10
11
12
DATA[6]
DATA[7]
VIO
13
DATA[5]
6
9
DATA[2]
8
CLOCK
DATA[4]
DIR
14
DATA[3]
15
5
7
4
DATA[1]
CS_N
DATA[0]
Table 8. Pin Definitions - TX2UL 24-Pin QFN
Name
Pin No.
ULPI Link Interface
DATA[0]
4
DATA[1]
5
DATA[2]
6
DATA[3]
8
DATA[4]
9
DATA[5]
11
DATA[6]
12
DATA[7]
13
CLOCK
14
NXT
17
STP
16
DIR
15
USB
DP
22
DM
23
Misc
CS_N
7
RESET_N
18
Type
Voltage
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
O
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
1.8 - 3.3 V
I/O
I/O
USB
USB
I
I
1.8 - 3.3 V
1.8 - 3.3 V
XI
21
I
XO
20
O
NC
2
POWER and GROUND
VCC
3, 19
Power
VIO
10
Power
VBATT
24
Power
VSSBATT
1
GND
VSS
Die Paddle GND
1.8 V
1.8 - 3.3 V
1.8 V
1.8 - 3.3 V
3.0 - 5.775 V
0
0
Document Number: 001-15775 Rev. *O
Description
ULPI data to/from link
ULPI data to/from link
ULPI data to/from link
ULPI data to/from link
ULPI data to/from link
ULPI data to/from link
ULPI data to/from link
ULPI data to/from link
ULPI clock
ULPI next signal
ULPI stop signal
ULPI direction
USB D-plus signal
USB D-minus signal
When CS_N is de-asserted, all pins at ULPI interface are tristated
Device chip global reset. When RESET_N is asserted, TX2UL is in reset and
enters into the power saving mode.
Crystal or LVCMOS single ended clock of frequency 13, 19.2, 24, or 26 MHz
Crystal
No connect
Low voltage supply for the digital core
Power for multi-range I/Os
High voltage supply for USB
USB ground
Digital ground (core and I/O)
Page 8 of 30
CY7C68003
Synchronous Operation Modes
This section describes the synchronous mode of TX2UL ULPI interface protocol.
ULPI Transmit Command Byte (TX CMD)
The Link initiates transfers to TX2UL by sending the Transmit Command Byte as shown in Table 9. TX CMD byte consists of a 2-bit
command code and a 6-bit payload.
Table 9. Transmit Command (TX CMD) Byte Format
Byte Name
Command Code Data (7:6)
Special
00b
Transmit
RegWrite
RegRead
01b
10b
11b
Command Payload Data (5:0)
Command Description
000000b
(NOOP)
No operation. 00h is the idle value of the data
bus. The Link drives NOOP by default.
XXXXXXb
(RSVD)
Reserved command space. Values other than
those mentioned give undefined behavior.
000000b
(NOPID)
Transmit USB data that does not have a PID,
such as chirp and resume signalling. The
TX2UL starts transmitting on the USB
beginning with the next byte.
00XXXXb
(PID)
Transmit USB packet. data (3:0) indicates
USB packet identifier PID (3:0)
XXXXXXb
(RSVD)
Reserved Command space. Values other
than those mentioned give undefined
behavior.
101111b
(EXTW)
Extended register write command. 8-bit
address available in the next cycle.
XXXXXXb
(REGW)
Register write command with 6-bit immediate
address.
101111b
(EXTR)
Extended register read command. 8-bit
address available in the next cycle.
XXXXXXb
(REGR)
Register read command with 6-bit immediate
address.
ULPI Receive Command Byte (RX CMD)
The Receive Command Byte, as shown in Table 10, is sent by TX2UL to update the link with LineState and USB receive information.
The USB receive information includes LineState, RxActive, and RxError. After a USB transmit, TX2UL sends RX CMD with LineState
indicating EOP to the link. For High Speed, EOP is the squelch to squelch transition on LineState. Figure 7 on page 10 shows how
TX2UL sends RX CMD information to the link. The first packet shows a single RX CMD. If back to back changes are detected, TX2UL
keeps DIR asserted and sends back to back RX CMDs as shown in the second packet.
Table 10. Receive Command (RX CMD) Byte Format
Data
Name
Description and Value
1:0
LineState
ULPI LineState signals.
DATA[0] = LineState (0)
DATA[1] = LineState (1)
3:2
Reserved
5:4
RxEvent
7:6
Encoded UTMI event signals
Value
RxActive
RxError
00
0
0
01
1
0
11
1
1
10
X
X
Reserved
Document Number: 001-15775 Rev. *O
Page 9 of 30
CY7C68003
Figure 6. Sending RX CMD
CLOCK
DATA[7:0]
Turn around
RX CMD
Turn around
Turn around
RX CMD
RX CMD
Turn around
DIR
STP
NXT
USB Data Transmit (NOPID)
In this mode, the Link transmits data on the USB without a Packet Identifier (PID) by sending a TX CMD byte of the NOPID type.
TX2UL asserts NXT (see Figure 8 on page 11) in the first cycle of TX CMD and deasserts NXT when it detects STP to be high. Because
this command does not contain PID data, TX2UL waits for the next data byte before beginning transmission on the USB. When the
last byte is transferred by the TX2UL, the link asserts STP for one cycle and drives data to 00h if no transmit errors occur. The link
does not assert STP before the first byte is transferred by the TX2UL.
Figure 7. USB Data Transmit (NOPID)
CLOCK
DATA[7:0]
TX CMD (NOPID)
D0
D1
D2
DIR
STP
NXT
Document Number: 001-15775 Rev. *O
Page 10 of 30
CY7C68003
USB Data Transmit (PID)
In this mode, the link transmits data on the USB with a PID. The link first drives a TX CMD byte as illustrated in Figure 9 on page 11
to transmit a USB packet. The link sets the Command Code to 01b (Transmit) and places the USB Packet Identifier (PID) on DATA[3:0]
(see Table 9 on page 9). TX2UL throttles the data using NXT such that the link provides the next byte in the cycle after NXT is detected
as high.
Figure 8. USB Data Transmit (PID)
CLOCK
DATA[7:0]
TX CMD (PID)
D1
D2
D3
DIR
STP
NXT
USB Packet Receive
As shown in Figure 10 on page 12, when TX2UL receives the USB data it gains ownership of the data bus by asserting DIR. The DIR
is previously either high or low. If DIR is low (see Figure 9), TX2UL asserts both DIR and NXT so that the link knows immediately that
this is a USB receive packet. If DIR is high (see Figure 10 on page 12), TX2UL deasserts NXT and drives an RX CMD with the RxEvent
field set to the RxActive state. The TX2UL starts driving data in the following cycle or outputs RX CMD until USB data is available.
Valid USB packet data is presented to the link by asserting NXT and placing a byte on the bus. When NXT is low, TX2UL drives the
RX CMD byte. All RX CMD changes during the USB packet receive are signaled when NXT is low. If NXT is never low during the
packet receive, all RX CMD changes are replaced with a single RX CMD update. This update is sent at the end of the USB packet
receive, when the ULPI bus is available. The RX CMD update always conveys the current RX CMD values and not the previous one.
Figure 9. USB Receive While DIR is Previously Low
CLOCK
DATA[7:0]
Turn around
RX CMD
PID
D1
RX CMD
D2
D3
Turn around
DIR
STP
NXT
Document Number: 001-15775 Rev. *O
Page 11 of 30
CY7C68003
Figure 10. USB Receive While DIR is Previously High
CLOCK
DATA[7:0]
Previous
RX CMD
(RxActive)
RX CMD
PID
D1
RX CMD
D2
D3
Turn around
DIR
STP
NXT
Immediate Register Read and Write
An immediate register is accessed by sending the TX CMD byte first (see Figure 11 and Figure 12 on page 13). This byte is sent as
a regread or regwrite command, depending on the intended operation.
For a register write (see Figure 11), the link first sends a register write TX CMD byte and waits for NXT to assert. After NXT asserts,
the link sends the register write data and waits for NXT to assert again. After the second assertion is detected, the link asserts STP
in the following cycle to complete the operation. The TX2UL detects this STP assertion before it can accept another transmit command.
If the TX2UL aborts rewrite by asserting DIR, the link repeats the entire process again when the bus is idle.
For a register read (see Figure 12 on page 13), the link sends a register read command and waits for NXT to assert. In the cycle after
NXT asserts, the TX2UL asserts DIR to gain control of the data bus. In the cycle, after DIR asserts the TX2UL returns the register
read data. The TX2UL does not assert NXT when DIR is asserted during the register read operation, even during the cycle when the
register read data is returned. If the TX2UL aborts the regread by asserting DIR earlier than shown in Figure 12 on page 13, the link
retries the regread when the bus is idle.
Figure 11. Register Write
CLOCK
DATA[7:0]
TX CMD
(RegWrite)
Data
DIR
STP
NXT
Document Number: 001-15775 Rev. *O
Page 12 of 30
CY7C68003
Figure 12. Register Read
CLOCK
TX CMD
DATA[7:0]
(RegRead)
Turn around
Data
Turn around
DIR
STP
NXT
Immediate Register Read and Write Aborted by USB Receive
A register read is the only instance where ULPI does not use NXT to acquire data. The NXT signal is asserted only during USB receive
to distinguish this type of receive from other types of data transfers.
Register read and write operations are aborted when the TX2UL sends a RX CMD, except during the cycle where register read data
is returned to the link.
TX2UL asserts both DIR and NXT whenever a register read or write is aborted by a USB receive during the initial transmit command
byte or in the same cycle that the register read data returned to the link.
Figure 13. Register Read or Write Aborted by USB Receive During TX CMD Byte
RegRead or RegWrite
USB Receive
CLOCK
DATA[7:0]
TX CMD
(Reg)
Turn around
RX CMD
PID
D1
D2
D3
DIR
STP
NXT
Document Number: 001-15775 Rev. *O
Page 13 of 30
CY7C68003
Back to Back Immediate Register Read and Write and USB Receive
When a USB receive occurs in the same cycle that the register read data is returned to the link, the TX2UL first returns the register
read data, not a RX CMD byte (see Figure 14).
When a USB receive occurs in the cycle immediately after a register read completes, the TX2UL places the USB receive data
back-to-back with the register read (see Figure 15). The link accepts back-to-back packets where DIR does not deassert between
packets. If DIR asserts during the same cycle that STP is asserted at the end of a register write, then the TX2UL considers the register
write to have successfully executed (see Figure 16 on page 15).
When a USB receive starts in the cycle after the register read data is returned to the link, it results in two cycles of bus turnaround
when DIR deasserts for a single cycle (see Figure 17 on page 15).
Figure 14. USB Receive in Same Cycle as Register Read Data. USB Receive is Delayed
RegRead
USB Receive
CLOCK
DATA[7:0]
TX CMD
(RegReg)
Turn around
Reg Data
RX CMD
(RxActive)
PID
D1
D2
D1
D2
DIR
STP
NXT
Figure 15. Register Read Followed Immediately by a USB Receive
RegRead
USB Receive
CLOCK
DATA[7:0]
TX CMD
(RegReg)
Turn around
Reg Data
RX CMD
(RxActive)
PID
DIR
STP
NXT
Document Number: 001-15775 Rev. *O
Page 14 of 30
CY7C68003
Figure 16. Register Write Followed Immediately by a USB Receive During STP Assertion
RegWrite
USB Receive
CLOCK
DATA[7:0]
TX CMD
(RegReg)
Data
Turn around
RX CMD
PID
(RxActive)
D1
D2
DIR
STP
NXT
Figure 17. Register Read Followed by a USB Receive
RegRead
USB Receive
CLOCK
DATA[7:0]
TX CMD
(RegReg)
Turn around
Reg Data
Turn around
Turn around
PID
D1
DIR
STP
NXT
Document Number: 001-15775 Rev. *O
Page 15 of 30
CY7C68003
Configuration Mode
Table 11. The TX2UL is defaulted to 26 MHz with single end
clock input (to XI).
TX2UL is configured in the input clock type and frequency for the
XI and XO in Configuration Mode. The 20-pin CSP package and
the 24-pin QFN package have different procedures to enter
configuration mode.
Table 11. TX2UL Configuration Options
Configuration Mode in 20-Pin CSP package
To enter configuration mode, keep the RESET_N low during VCC
Power On for tSTATE (see Figure 19 on page 22 for the timing
diagraming and Table 21 on page 21 for the tSTATE timing
requirement). When TX2UL enters configuration mode, the
peripheral controller (link device) generates the pulses (falling
edge) at the RESET_N pin to configure TX2UL. TX2UL
configures its internal oscillator base on number of received
pulses at the RESET_N pin. When the configuration is
completed, deassert RESET_N (high) for tSTATE to exit the
Configuration. If the TX2UL needs to enter the Configuration
Mode again, it must go through the following power cycle:
VCC Off ℜ→ RESET_N Low ℜ→ VCC On.
Number of Pulses at
RESET_N Pin during
Configuration Mode
Configuration Description
0 pulses
26 MHz clock input on XI (default)
1 pulses
19.2 MHz clock input on XI
2 pulses
24.0 MHz clock input on XI
3 pulses
13.0 MHz clock input on XI
4 pulses
26 MHz crystal on XI/XO
5 pulses
19.2 MHz crystal on XI/XO
6 pulses
24.0 MHz crystal on XI/XO
7 pulses
13.0 MHz crystal on XI/XO
Power On Reset (POR)
Configuration Mode in 24-Pin QFN package
TX2UL has an internal power on reset (POR) block that provides
power on reset and power management control functionality.
This POR function complies with all the parameters required by
the ULPI specification.
To enter configuration mode keep the RESET_N pin pulled low
for tSTATE (see Figure 20 on page 22 for the timing diagraming
and Table 21 on page 21 for the tSTATE timing requirement)
while deasserting CS_N (high). When TX2UL enters configuration mode, the peripheral controller (link device) generates the
pulses (falling edge) at the RESET_N pin to configure TX2UL.
TX2UL configures its internal oscillator base on number of
received pulses at the RESET_N pin. When the configuration is
completed, assert the CS_N (low) for tSTATE (see Figure 21 on
page 21 for the timing) to exit the configuration mode. Figure 19
on page 22 shows the timing diagram of entering and exiting
configuration mode. The configuration options are listed in
Register
TX2UL provides an immediate register set that is defined by the
ULPI specification for control and configuration functions.
Register Map
The ULPI specifications define an immediate register set with a
6-bit address that forms a part of the transmit command byte,as
shown in shown in Table 12.
Table 12. Register Map
Field Name
Size (bits)
Address (6bits)
Rd
Wr
Set
Clr
Immediate Register Set
Vendor ID Low
8
00h
-
-
-
Vendor ID High
8
01h
-
-
-
Product ID Low
8
02h
-
-
-
Product ID High
8
03h
-
-
-
Function Control
8
04-06h
04h
05h
06h
Interface Control
8
07-09h
07h
08h
09h
Debug
8
15h
-
-
-
Scratch Register
8
16-18h
16h
17h
18h
Carkit Control (Optional)
8
19-1Bh
19h
1Ah
1Bh
Drive Strength and Slew Rate
8
31h
31h
-
-
USB Interface Control Register
8
35h
35h
-
-
Vendor Specific Register Set
Document Number: 001-15775 Rev. *O
Page 16 of 30
CY7C68003
Table 13 to Table 17 on page 18 define the read, write, set, and clear register options. The following are the conventions:
■
Rd or rd = Read
■
Wr or wr = Write
■
Set or s = Set
■
Clr or c = Clear
Immediate Register Set
The details of all immediate registers of TX2UL are shown in Table 6 on page 6, Table 18 on page 19, and Table 20 on page 21.
Function Control Register
Control ULPI Function Setting of TX2UL
Table 13. Function Control Register (Address: 04h - 06h [read], 04h [write], 05h [set], 06h [clear])
Description
Access
Reset Value
1:0
Bit
XcvrSelect
Selects the required transceiver speed.
00b: Enable HS transceiver
01b: Enable FS transceiver
10b: Reserved
11b: Enable FS transceiver for LS packets.
rd/wr/s/c
01b
2
TermSelect
Controls the internal 1.5 K pull up resistor and 45 HS terminations.
rd/wr/s/c
0b
OpMode
Selects the required bit encording style during transmit.
rd/wr/s/c
00b: Normal operation
01b: Non-driving
10b: Disable bit stuff and NRZI encoding
11b: Do not automatically add SYNC and EOP when transmitting. It is used
only for HS packets.
00b
5
Reset
Active high transceiver reset. After the link sets this bit, TX2UL asserts DIR rd/wr/s/c
and resets ULPI core. When the reset is completed, DIR is de-asserted
and automatically clears this bit. After de-asserting DIR, TX2UL re-asserts
DIR and sends and RX CMD update to the link. The link waits for DIR to
de-assert before using ULPI bus. It does not reset the ULPI interface or
ULPI register set.
0b
6
SuspendM
Active low. Put TX2UL into Low Power Mode. TX2UL powers down all
rd/wr/s/c
blocks except the full speed receiver and ULPI interface pins. TX2UL sets
this bit to ‘1’ when it exits from low power mode.
0b: Enter into low power mode
1b: Normal operation mode
1b
7
Reserved
4:3
Field Name
Document Number: 001-15775 Rev. *O
rd
x
Page 17 of 30
CY7C68003
Interface Control Register
This register enables alternative interface and TX2UL features.
Table 14. Interface Control Register (Address: 07h - 09h [read], 07h [write], 08h [set], 09h [clear])
Bit
1:0
2
6:3
7
Field Name
Description
Reserved
CarkitMode
Changes the ULPI interface to carkit interface that support UART pass
through mode. This bit is cleared when it exits from carkit UART pass
through mode.
0b: Disable serial carkit mode
1b: Enable serial carkit mode
Reserved
Interface Protect
Disable
Access
Reset Value
rd
xxb
rd/wr/s/c
0b
rd
xxxxb
Controls circuitry built into TX2UL for protecting the ULPI interface when rd/wr/s/c
the link tristates STP and DATA[7:0]. Any pull ups or pull downs employed
by this feature are disabled
0b: Enable the interface Protect Circuit
1b: Disable the Interface Protect Circuit
0b
Debug Register
This register indicates the current value of various signals useful for debugging.
Table 15. Debug Register (Address: 15h [read only])
Bit
Field Name
Description
Access
Reset Value
0
LineState0
Contains the current value of LineState(0)
rd
0b
1
LineState1
Contains the current value of LineState(1)
rd
0b
7:2
Reserved
rd
000000b
Description
Access
Reset Value
Empty register byte for testing purposes. The link software reads, writes,
sets, and clears this register.
rd/wr/s/c
00000000b
Scratch Register
This register is for testing purpose only. The link can read, write, set and clear this register.
Table 16. Scratch Register (Address: 16h - 18h [read], 16h [write], 17h [set], 18h [clear])
Bit
7:0
Field Name
Scratch
Carkit Control Register
This register controls the TXD and RXD in carkit UART pass through mode. It has no control function if the CarkitMode bit in Interface
Control Register is not set.
Table 17. Carkit Control Register (Address: 19h - 1Bh [read], 19h [write], 1Ah [set], 1Bh [clear])
Bit
1:0
Field Name
Description
Reset Value
rd
xxb
2
TxdEn
Routes TXD signal from DATA[0] pin to DM pin
rd/wr/s/c
0b
3
RxdEn
Routes RXD signal from DP pin to DATA[1] pin
rd/wr/s/c
0b
rd
xxxxb
7:4
Reserved
Access
Reserved
Document Number: 001-15775 Rev. *O
Page 18 of 30
CY7C68003
Drive Strength and Slew Rate Configuration Register
This register is mapped to the vendor specific registers address. This register configures the drive strength and slew rate of the outputs.
Table 18. Drive Strength and Slew Rate Configuration Register (Address: 31h [read], 31h [write])
Bit
Access
Reset Value
DriveStrength
Configure the drive strength on the output pins
00b: Full drive strength
01b: Three quarter drive strength
10b: half drive strength
11b: Quarter drive strength
rd/wr
00b
2
SlewRate
Configure the slew rate on the output pins
0b: slow slew rate
1b: fast slew rate
rd/wr
0b
7:3
Reserved
rd
00000b
1:0
Field Name
Description
USB Interface Control Register
This register is mapped to the vendor specific registers address. This register enables or disables the USB interface.
Table 19. USB Interface Control Register (Address: 35h [read], 35h [write])
Bit
1:0
2
7:3
Field Name
Description
Reserved
When write to this register, this field must be filled in 0s
UsbEnable
USB interface control
0b: Disable USB interface
1b: Enable USB interface
Reserved
When write to this register, this field must be filled in 0s
Document Number: 001-15775 Rev. *O
Access
Reset Value
rd
00b
rd/wr
0b
rd
00000b
Page 19 of 30
CY7C68003
Absolute Maximum Ratings
DC voltage applied to
outputs in high Z state ........................ –0.5 V to VCC + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage (ESD)
from JESD22-A114.................................................. > 2000 V
Storage temperature................................. –65 °C to +150 °C
Latch up current...................................................... > 200 mA
Ambient temperature with
power supplied (Industrial) ......................... –40 °C to +85 °C
Maximum output short circuit current
for all I/O configurations. (Vout = 0 V) ..................... –100 mA
Supply voltage to ground potential
VCC ...............................................................–0.5 V to +2.0 V
VIO ................................................................–0.5 V to +4.0 V
VBATT ........................................................–0.5 V to +5.775 V
DC input voltage to any input pin....................1.89 V to 3.6 V
Depends on I/O supply voltage. Inputs are not over voltage
tolerant.
Document Number: 001-15775 Rev. *O
Operating Conditions
Ambient temperature under bias (TA)
Industrial ..................................................... –40 °C to +85 °C
VCC supply voltage ...........................................1.7 V to 1.9 V
VIO supply voltage ............................................1.7 V to 3.6 V
VBATT supply voltage ....................................3.0 V to 5.775 V
Page 20 of 30
CY7C68003
DC Characteristics
Table 20. DC Specifications for All Voltage Supplies
Min
Typ
Max
Unit
VCC
Parameter
Core voltage supply
Description
Conditions
1.7
1.8
1.9
V
VIO
ULPI interface I/O voltage supply
(this I/O supply is not available on
20-Ball WLCSP package)
1.7
1.8, 2.5,
3.3
3.6
V
VBATT
Crystal voltage supply
3.0
–
5.775
V
VPOR(trip)
Power on reset trip voltage
1.0
–
1.5
V
VIH1
Input HIGH voltage 1
All ports except USB,
2.0 V < VIO < 3.6 V
0.625 × VIO
–
VIO + 0.3
V
VIH2
Input HIGH voltage 2
All ports except USB,
1.7 V < VIO < 2.0 V
VIO‚ 0.4
–
VIO + 0.3
V
VIL
Input LOW voltage
–0.3
–
0.25 × VIO
V
VOH
Output HIGH voltage
IOH(MAX) = 0.1 mA
0.9 × VIO
–
–
V
VOL
Output LOW voltage
IOL(MIN) = 0.1 mA
–
–
0.1 × VIO
V
IIX
Input leakage current
All I/O signals held at VDDQ
1
–
1
μA
IOZ
Output leakage current
All I/O signals held at VDDQ
1
–
1
μA
ICC
Supply current
Continuous Receive
–
30
65
mA
Continuous Transmit
–
30
65
mA
ULPI Low Power Mode
(Suspend)
VCC = 1.8 V
–
300
750
μA
Sleep Mode
- ULPI interface bus is either Hz
or drive High
- DP and DM must be Hz or pull
low
–
5
40
μA
IPU
Pull up current
Interface protect enabled;
STP pin only; VI = 0 V
–13
–
–80
μA
IPD
Pull down current
Interface protect enabled;
DATA[7:0] only;
VI = VIO
16
–
90
μA
AC Characteristics
Table 21. ULPI Timing Parameters
Parameter
Description
Min
Max
Unit
tCS
Setup time for control input
5.8
–
ns
tDS
Setup time for data input
5.8
–
ns
tCH
Hold time for control input
0
–
ns
tDH
Hold time for data input
0
–
ns
tCD
Output delay time for control output
7.6
9.0
ns
tDD
Output delay time for data output
7.6
9.0
ns
tSTATE
Mode state change time
500
–
μs
tPW
Pulse width
200
10000
ns
Document Number: 001-15775 Rev. *O
Page 21 of 30
CY7C68003
Figure 18. ULPI Timing Diagram
CLOCK
tCS
tCH
Control In
(STP)
tDS
tDH
DATA[7:0] In
tCD
tCD
tDD
tDD
Control out
(DIR, NXT)
DATA [7:0] Out
Figure 19. 20-Pin CSP Package Configuration Mode Entry Timing Diagram
Exiting From
Entering into
Configuration
Configuration
Mode
Mode
Configuration Mode
tSTATE
tSTATE
Normal Operation Mode
VCC
tPW
tPW
tPW
RESET_N
Configuration Pulses (falling edge)
Figure 20. 24-Pin QFN Package Configuration Mode Entry Timing Diagram
VCC
Entering into
Configuration
Mode
Configuration Mode
tSTATE
Exiting From
Configuration
Normal Operation Mode
Mode
tSTATE
CS_N
tPW
tPW
RESET_N
Configuration Pulses (falling edge)
Document Number: 001-15775 Rev. *O
Page 22 of 30
CY7C68003
Figure 21. AC Test Loads and Waveforms
Figure 22. Connecting 20-Ball WLCSP Package TX2UL with a Standard Peripheral Controller with External Clock
3.3 – 5.775V
VCC
VBATT
1.8V
Peripheral
Controller
A1
CLOCK
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DIR
NXT
STP
RESET_N
CLOCK
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DIR
NXT
STP
RESET_N
B5
A5
D1
C5
USB
Connector
D5
C4
A4 DM
A3 DP
D4
B4
D3
TX2UL
CSP Package
DM 2
DP 3
4
C3
D2
C1
B1
A2
C2
XI
13/19.2/24/26 MHz
External Clock
B2
VSS
B3
Document Number: 001-15775 Rev. *O
Page 23 of 30
CY7C68003
Ordering Information
Ordering Code
Package Type
Support Clock Input Frequencies (MHz)
CY7C68003-20FNXIT
20-ball WLCSP – Tape and Reel
13, 19.2, 24, 26
CY7C68003-24LQXI
24-pin QFN
13, 19.2, 24, 26
CY7C68003-24LQXIT
24-pin QFN – Tape and Reel
13, 19.2, 24, 26
Ordering Code Definitions
CY 7 C 68
XXX - FNX/LQX (I)
(T)
Tape and Reel
Thermal Rating :
I = Industrial
Package type: FNX - WLCSP Pb-free
LQX - QFN Pb-free
Part Number
Family Code : 68 = USB
Technology Code: C = CMOS
Marketing Code: 7 = Cypress Products
Company ID: CY = Cypress
Document Number: 001-15775 Rev. *O
Page 24 of 30
CY7C68003
Package Diagrams
Figure 23. 20-Pin WLCSP Package Outline
001-13856 *D
Document Number: 001-15775 Rev. *O
Page 25 of 30
CY7C68003
Figure 24. 24-pin QFN Package Outline
001-13937 *F
Document Number: 001-15775 Rev. *O
Page 26 of 30
CY7C68003
Acronyms
Document Conventions
Table 22. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 23. Units of Measure
ASIC
application specific integrated circuit
CPU
central processing unit
KHz
kilohertz
DID
device identifier
Mbytes
megabytes
DSP
digital signal processor
MHz
megahertz
EEPROM
electrically erasable programmable read only
memory
µA
microampere
µs
microseconds
EPP
enhanced parallel port
µW
microwatts
ECC
error correction code
mA
milliampere
FIFO
first in first out
mW
milliwatts
GPIF
general programmable interface
ns
nanoseconds
GPIO
general purpose input / output
ppm
parts per million
HBM
human body model
pF
picofarads
I/O
input output
V
volts
PDA
personal digital assistant
PLL
phase lock loop
PID
product identifier
SIE
serial interface engine
SOF
start of frame
USB
universal serial bus
VID
vendor identifier
WLCSP
wafer level chip scale package
ULPI
UTMI+ low pin interface
Document Number: 001-15775 Rev. *O
Symbol
Unit of Measure
Page 27 of 30
CY7C68003
Document History Page
Document Title: CY7C68003, MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver
Document Number: 001-15775
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
1094246
VSO / XVA
See ECN
Initial Release
*A
1188703
VSO
See ECN
Update the tSTATE min requirement (from 200 us to 500us) in Table 21
Section Sleep Mode add (see Table 21 for tSTATE requirement)
Section of Operating Conditions (page 19), the second VCC corrected to VIO.
Table 19, the reference voltage for the VIH1, VIH2, VIL, VOH, and VOL has
corrected from VCC to VIO.
*B
1505863
VSO /
AESA
See ECN
Change in Ordering Information.
*C
2081867
VSO /
AESA
See ECN
Update the ESD description in the features list.
Updated the description of section “Power Supply Sequence”
Updated the section of Chip Section (CS_N)
Updated the section of Operation Modes - tri-state mode only available in
24-pin QFN package
Updated Figure 3.
Added Table 4.
Updated Figure 4 and Table 7 (CSP pin assignment has been changed)
Updated the section of Configuration Mode
Correct the hyper link section of Immediate Register Set
Correct the word of “Reserved” in Table 14
Updated ULPI Timing Parameters table (table-21)
Updated ULPI Timing Diagram (figure 18)
Added Figure 19.
Removed USB Interface Control Register section and table in page 19
Updated Figure 22.
*D
2552066
VSO
08/13/2008
In the first page, feature list, update the CSP dimension from “2.2 x 1.8
mm” to “2.14 x 1.76 mm”.
Updated Table 12
Add USB Interface Control Register section
*E
2597682
VSO /
AESA
10/28/2008
Removed PRELIMINARY in master pages (turn into Final data sheet).
Updated data sheet template.
Updated Ordering Information table.
In the Clocking section, added a bullet ‘150 ppm’.
Table 3:
❐ changed PN_DC to PN_100
❐ changed DC to 100
❐ change the unit of dB to dBc/Hz
❐ added a row of ‚ÄúMaximum Frequency Deviation‚Äù
*F
2671871
VSO /
PYRS
03/13/2009
Updated Suspend current in Table 20 (clarified VCC = 1.8 V).
Changed all TX3, TX3LP18 to TX2UL
*G
2765711
TIK / RADH
09/18/2009
Posting to external web.
*H
2920278
VSO /
AESA
04/21/2010
Added “Suport USB Device Mode only” in the Feature section.
Added table of conetnts.
Updated links in Sales, Solutions, and Legal Information.
*I
3035786
HBM
09/22/2010
Post to external web.
*J
3305013
ODC
07/07/2011
Corrected crystal drive level requirement.
Corrected VIL min value.
Format updates based on the template and style guide.
Added ordering code definition diagram.
Added acronyms and units of measure.
Document Number: 001-15775 Rev. *O
Page 28 of 30
CY7C68003
Document History Page (continued)
Document Title: CY7C68003, MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver
Document Number: 001-15775
Revision
ECN
Orig. of
Change
Submission
Date
*K
3493857
VSO
01/17/2012
No technical updates.
Completing Sunset Review.
*L
3941477
KHIG
03/22/2013
Updated Absolute Maximum Ratings.
Updated Package Diagrams:
spec 001-13856 – Changed revision from *B to *C.
spec 001-13937 – Changed revision from *C to *E.
*M
4281294
SAMT
02/14/2014
Updated Ordering Information (Updated part numbers).
Updated to new template.
*N
4623579
NIKL
01/14/2015
No technical updates.
Completing Sunset Review.
*O
5755554
HPPC
05/30/2017
Updated Package Diagrams:
spec 001-13856 – Changed revision from *C to *D.
spec 001-13937 – Changed revision from *E to *F.
Updated to new template.
Document Number: 001-15775 Rev. *O
Description of Change
Page 29 of 30
CY7C68003
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Products
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Automotive
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cypress.com/iot
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Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
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cypress.com/support
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cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-15775 Rev. *O
MoBL-USB is a trademark of Cypress Semiconductor Corporation.
Revised May 30, 2017
Page 30 of 30
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