Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
EZ-USB FX2LP USB Microcontroller
High-Speed USB Peripheral Controller
EZ-USB FX2LP USB Microcontroller High-Speed USB Peripheral Controller
Features
■
USB 2.0 USB IF Hi-Speed certified (TID # 40460272)
■
Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
■
Fit-, form-, and function-compatible with the FX2
❐ Pin-compatible0
❐ Object-code-compatible
❐ Functionally compatible (FX2LP is a superset)
■
Ultra-low power: ICC no more than 85 mA in any mode
❐ Ideal for bus- and battery-powered applications
■
Software: 8051 code runs from:
❐ Internal RAM, which is downloaded through USB
❐ Internal RAM, which is loaded from EEPROM
❐ External memory device (128-pin package)
■
3.3-V operation with 5-V tolerant inputs
■
Vectored USB interrupts and GPIF/FIFO interrupts
■
Separate data buffers for the setup and data portions of a
CONTROL transfer
■
Integrated I2C controller; runs at 100 or 400 kHz[1]
■
Four integrated FIFOs
❐ Integrated glue logic and FIFOs lower system cost
❐ Automatic conversion to and from 16-bit buses
❐ Master or slave operation
❐ Uses external clock or asynchronous strobes
❐ Easy interface to ASIC and DSP ICs
■
Available in commercial and industrial temperature grades (all
packages except VFBGA)
Features (CY7C68013A/14A only)
■
16 KB of on-chip code/data RAM
■
■
Four programmable BULK, INTERRUPT, and
ISOCHRONOUS endpoints
❐ Buffering options: Double, triple, and quad
CY7C68014A: Ideal for battery-powered applications
❐ Suspend current: 100 A (typ)
■
CY7C68013A: Ideal for nonbattery-powered applications
❐ Suspend current: 300 A (typ)
■
Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
■
■
8-bit or 16-bit external data interface
■
Smart media standard ECC generation
Available in five Pb-free packages with up to 40 GPIOs
❐ 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin
VFBGA (24 GPIOs)
■
GPIF™ (general programmable interface)
❐ Enables direct connection to most parallel interfaces
❐ Programmable waveform descriptors and configuration
registers to define waveforms
❐ Supports multiple ready (RDY) inputs and control (CTL)
outputs
■
Integrated, industry-standard, enhanced 8051
❐ 48-MHz, 24-MHz, or 12-MHz CPU operation
❐ Four clocks per instruction cycle
❐ Two USARTs
❐ Three counter/timers
❐ Expanded interrupt system
❐ Two data pointers
Features (CY7C68015A/16A only)
■
CY7C68016A: Ideal for battery-powered applications
❐ Suspend current: 100 A (typ)
■
CY7C68015A: Ideal for nonbattery-powered applications
❐ Suspend current: 300 A (typ)
■
Available in Pb-free 56-pin QFN package (26 GPIOs)
■
Two more GPIOs than CY7C68013A/14A enabling additional
features in the same footprint
Functional Description
For a complete list of related resources, click here.
Notes
1. The actual I2C clock frequency will be different. The measured I2C clock frequency when set for 100 kHz and 400 kHz is around 85 kHz and 300 kHz respectively.
2. For information on silicon errata, see “Errata” on page 68. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-08032 Rev. AD
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 30, 2021
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the application note AN65209 - Getting
Started with FX2LP.
■
Overview: USB Portfolio, USB Roadmap
EZ-USB FX2LP Development Kit
■
USB 2.0 Product Selectors: FX2LP, AT2LP, NX2LP-Flex, SX2
The CY3684 EZ-USB FX2LP Development Kit is a complete
development resource for FX2LP.
Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to
advanced level. Recommended application notes for getting
started with FX2LP are:
❐ AN65209 - Getting Started with FX2LP
®
❐ AN15456 - Guide to Successful EZ-USB FX2LP™ and
EZ-USB FX1™ Hardware Design and Debug
®
❐ AN50963 - EZ-USB FX1™/FX2LP™ Boot Options
®
❐ AN66806 - EZ-USB FX2LP™ GPIF Design Guide
❐ AN61345 - Implementing an FX2LP™- FPGA Interface
❐ AN57322 - Interfacing SRAM with FX2LP over GPIF
❐ AN4053 - Streaming Data through Isochronous/Bulk Endpoints on EZ-USB® FX2 and EZUSB FX2LP
®
❐ AN63787 - EZ-USB FX2LP™ GPIF and Slave FIFO Configuration Examples using 8-bit Asynchronous Interface
For complete list of Application notes, click here.
■
■
Code Examples:
❐ USB Hi-Speed
■
Technical Reference Manual (TRM):
❐ EZ-USB FX2LP Technical Reference Manual
■
Reference Designs:
❐ CY4661 - External USB Hard Disk Drives (HDD) with
Fingerprint Authentication Security
❐ FX2LP DMB-T/H TV Dongle reference design
■
Models: IBIS
Document Number: 38-08032 Rev. AD
The CY3689 EZ-USB FX2LP Discovery Kit is a newly designed
kit that helps beginners and experienced users to implement
different applications using FX2LP
The development kit contains collateral materials for the
firmware, hardware, and software aspects of a design using
FX2LP.
GPIF™ Designer
FX2LP™ General Programmable Interface (GPIF) provides an
independent hardware unit, which creates the data and control
signals required by an external interface. FX2LP GPIF Designer
allows users to create and modify GPIF waveform descriptors for
EZ-USB FX2/ FX2LP family of chips using a graphical user
interface. Extensive discussion of general GPIF discussion and
programming using GPIF Designer is included in FX2LP
Technical Reference Manual and GPIF Designer User Guide,
distributed with GPIF Designer. AN66806 - Getting Started with
EZ-USB® FX2LP™ GPIF can be a good starting point.
Page 2 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Logic Block Diagram
High-performance micro
using standard tools
with lower-power options
VCC
x20
PLL
/0.5
/1.0
/2.0
Data (8)
Address (16)
FX2LP
I2C
8051 Core
12/24/48 MHz,
four clocks/cycle
Master
1.5k
connected for
full speed
D+
D–
USB
2.0
XCVR
Integrated
full speed and
high speed
XCVR
CY
Smart
USB
1.1/2.0
Engine
16 KB
RAM
Address (16) / Data Bus (8)
24 MHz
Ext. XTAL
“Soft Configuration”
Easy firmware changes
Cypress’s EZ-USB® FX2LP™ (CY7C68013A/14A) is a
low-power version of the EZ-USB FX2™(CY7C68013), which is
a highly integrated, low-power USB 2.0 microcontroller. By
integrating the USB 2.0 transceiver, serial interface engine (SIE),
enhanced 8051 microcontroller, and a programmable peripheral
interface in a single chip, Cypress has created a cost-effective
solution that provides superior time-to-market advantages with
low power to enable bus-powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second (the maximum allowable
USB 2.0 bandwidth), while still using a low-cost 8051
microcontroller in a package as small as a 56 VFBGA (5 mm ×
5 mm). Because it incorporates the USB 2.0 transceiver, the
FX2LP is more economical, providing a smaller-footprint solution
than a USB 2.0 SIE or external transceiver implementations.
Document Number: 38-08032 Rev. AD
RDY (6)
CTL (6)
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
8/16
Up to 96 MBytes/s
burst rate
ADDR (9)
GPIF
ECC
4 kB
FIFO
Enhanced USB core
Simplifies 8051 code
Abundant I/O
including two USARTs
Additional I/Os (24)
FIFO and endpoint memory
(master or slave operation)
With EZ-USB FX2LP, the Cypress Smart SIE handles most of
the USB 1.1 and 2.0 protocol in hardware, freeing the embedded
microcontroller for application-specific functions and decreasing
the development time to ensure USB compatibility.
The general programmable interface (GPIF) and Master/Slave
Endpoint FIFO (8-bit or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form, and function
compatible with the 56-, 100-, and 128-pin FX2.
Five packages are defined for the family: 56-ball VFBGA, 56-pin
SSOP, 56-pin QFN, 100-pin TQFP, and 128-pin TQFP.
Page 3 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Contents
Applications ...................................................................... 5
Functional Overview ........................................................ 5
USB Signaling Speed .................................................. 5
8051 Microprocessor ................................................... 5
I2C Bus ........................................................................ 5
Buses .......................................................................... 5
USB Boot Methods ...................................................... 6
ReNumeration ............................................................. 6
Bus-Powered Applications .......................................... 6
Interrupt System .......................................................... 6
Reset and Wakeup ...................................................... 9
Program/Data RAM ................................................... 10
Register Addresses ................................................... 12
Endpoint RAM ........................................................... 13
External FIFO Interface ............................................. 15
GPIF .......................................................................... 15
ECC Generation ........................................................ 16
USB Uploads and Downloads ................................... 16
Autopointer Access ................................................... 16
I2C Controller ............................................................. 16
Compatible with Previous Generation
EZ-USB FX2 .............................................................. 17
CY7C68013A/14A and CY7C68015A/16A
Differences ................................................................ 17
Pin Assignments ............................................................ 18
CY7C68013A/15A Pin Descriptions .......................... 25
Register Summary .......................................................... 34
Absolute Maximum Ratings .......................................... 41
Operating Conditions ..................................................... 41
Thermal Characteristics ................................................. 41
DC Electrical Characteristics ........................................ 42
USB Transceiver ....................................................... 42
AC Electrical Characteristics ........................................ 43
USB Transceiver ....................................................... 43
Program Memory Read ............................................. 43
Document Number: 38-08032 Rev. AD
Data Memory Read ..................................................................44
Data Memory Write ..................................................................45
PORTC Strobe Feature Timings ............................... 46
GPIF Synchronous Signals ....................................... 47
Slave FIFO Synchronous Read ................................. 48
Slave FIFO Asynchronous Read ............................... 49
Slave FIFO Synchronous Write ................................. 50
Slave FIFO Asynchronous Write ............................... 51
Slave FIFO Synchronous Packet End Strobe ........... 52
Slave FIFO Asynchronous Packet End Strobe ......... 54
Slave FIFO Output Enable ........................................ 54
Slave FIFO Address to Flags/Data ............................ 54
Slave FIFO Synchronous Address ............................ 55
Slave FIFO Asynchronous Address .......................... 55
Sequence Diagram .................................................... 56
Ordering Information ...................................................... 60
Ordering Code Definitions ......................................... 60
Package Diagrams .......................................................... 61
PCB Layout Recommendations .................................... 65
Quad Flat Package No Leads (QFN) Package
Design Notes ................................................................... 66
Acronyms ........................................................................ 67
Document Conventions ................................................. 67
Units of Measure ....................................................... 67
Errata ............................................................................... 68
Part Numbers Affected .............................................. 68
CY7C68013A/14A/15A/16A Qualification Status ...... 68
CY7C68013A/14A/15A/16A Errata Summary ........... 68
Document History Page ................................................. 69
Sales, Solutions, and Legal Information ...................... 74
Worldwide Sales and Design Support ....................... 74
Products .................................................................... 74
PSoC® Solutions ....................................................... 74
Cypress Developer Community ................................. 74
Technical Support ..................................................... 74
Page 4 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Applications
Figure 1. Crystal Configuration
C1 24 MHz C2
■
Portable video recorder
■
MPEG/TV conversion
■
DSL modems
■
ATA interface
■
Memory card readers
■
Legacy conversion devices
■
Cameras
■
Scanners
■
Wireless LAN
■
MP3 players
The CLKOUT pin, which can be three-stated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.
■
Networking
USARTs
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Visit
www.cypress.com for more information.
Functional Overview
USB Signaling Speed
FX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
■
Full speed, with a signaling bit rate of 12 Mbps
■
High speed, with a signaling bit rate of 480 Mbps
FX2LP does not support the Low Speed signaling mode of
1.5 Mbps.
8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
8051 Clock Frequency
FX2LP has an on-chip oscillator circuit that uses an external
24-MHz (±100 ppm) crystal with the following characteristics:
■
Parallel resonant
■
Fundamental mode
■
500-W drive level
■
12-pF (5% tolerance) load capacitors
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz,
as required by the transceiver/PHY; internal counters divide it
down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
12 pF
12 pF
20 × PLL
12-pF capacitor values assume a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
FX2LP contains two standard 8051 USARTs, addressed through
Special Function Register (SFR) bits. The USART interface pins
are available on separate I/O pins, and are not multiplexed with
port pins.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and
12 MHz) such that it always presents the correct frequency for
the 230-KBaud operation[3].
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX2LP functions. These SFR additions are
shown in Table 1 on page 6. Bold type indicates nonstandard,
enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit-addressable registers. The four I/O ports A to
D use the SFR addresses used in the standard 8051 for ports 0
to 3, which are not implemented in FX2LP. Because of the faster
and more efficient SFR addressing, the FX2LP I/O ports are not
addressable in external RAM space (using the MOVX
instruction).
I2C Bus
FX2LP supports the I2C bus as a master only at 100/400 kHz[4].
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3 V, even if no I2C
device is connected.
Buses
All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,
multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
Notes
3. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
4. The actual I2C clock frequency will be different.The measured I2C clock frequency when set for 100 kHz and 400 kHz is around 85 kHz and 300 kHz respectively.
Document Number: 38-08032 Rev. AD
Page 5 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 1. Special Function Registers
x
8x
9x
Ax
Bx
Cx
Dx
Ex
Fx
0
IOA
1
SP
IOB
IOC
IOD
SCON1
PSW
ACC
B
EXIF
INT2CLR
IOE
SBUF1
–
–
–
2
DPL0
3
DPH0
MPAGE
INT4CLR
OEA
–
–
–
–
–
–
OEB
–
–
–
–
4
5
DPL1
–
–
OEC
–
–
–
–
DPH1
–
–
OED
–
–
–
–
6
DPS
–
–
OEE
–
–
–
–
7
PCON
–
–
–
–
–
–
–
8
TCON
SCON0
IE
IP
T2CON
EICON
EIE
EIP
9
TMOD
SBUF0
–
–
–
–
–
–
A
TL0
AUTOPTRH1
EP2468STAT
EP01STAT
RCAP2L
–
–
–
B
TL1
AUTOPTRL1
EP24FIFOFLGS
GPIFTRIG
RCAP2H
–
–
–
TL2
–
–
–
GPIFSGLDATH
TH2
–
–
–
C
TH0
reserved
EP68FIFOFLGS
D
TH1
AUTOPTRH2
–
E
CKCON
AUTOPTRL2
–
GPIFSGLDATLX
–
–
–
–
F
–
reserved
AUTOPTRSET-UP
GPIFSGLDATLNOX
–
–
–
–
USB Boot Methods
During the power-up sequence, internal logic checks the I2C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
in place of the internally stored values (0xC0), or it boot-loads the
EEPROM contents into internal RAM (0xC2). If no EEPROM is
detected, FX2LP enumerates using internally stored descriptors.
The default ID values for FX2LP are VID/PID/DID (0x04B4,
0x8613, 0xAxxx where xxx = Chip revision)[5].
Table 2. Default ID Values for FX2LP
Default VID/PID/DID
Vendor ID
0x04B4 Cypress Semiconductor
Product ID
0x8613
Device release
Depends on chip revision
0xAnnn (nnn = chip revision where first
silicon = 001)
EZ-USB FX2LP
Two control bits in the USBCS (USB Control and Status) register
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0, the
Default USB Device handles device requests; if RENUM = 1, the
firmware services the requests.
Bus-Powered Applications
The FX2LP fully supports bus-powered designs by enumerating
with less than 100 mA as required by the USB 2.0 specification.
Interrupt System
INT2 Interrupt Request and Enable Registers
ReNumeration
FX2LP implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.
Because the FX2LP’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
USB Interrupt Autovectors
When first plugged into USB, the FX2LP enumerates
automatically and downloads firmware and USB descriptor
tables over the USB cable. Next, the FX2LP enumerates again,
this time as a device defined by the downloaded information.
This patented two step process called ReNumeration™ happens
instantly when the device is plugged in, without a hint that the
initial download step has occurred.
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that is required to identify the
individual USB interrupt source, the FX2LP provides a second
level of interrupt vectoring, called Autovectoring. When a USB
interrupt is asserted, the FX2LP pushes the program counter to
its stack, and then jumps to the address 0x0043 where it expects
to find a “jump” instruction to the USB interrupt service routine.
Note
5. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document Number: 38-08032 Rev. AD
Page 6 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
The FX2LP jump instruction is encoded as follows:
Table 3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority
INT2VEC Value
Source
Notes
1
00
SUDAV
Setup data available
2
04
SOF
Start of frame (or microframe)
3
08
SUTOK
Setup token received
4
0C
SUSPEND
USB suspend request
5
10
USB RESET
Bus reset
6
14
HISPEED
Entered high speed operation
7
18
EP0ACK
FX2LP ACK’d the CONTROL Handshake
8
1C
9
20
EP0-IN
EP0-IN ready to be loaded with data
10
24
EP0-OUT
EP0-OUT has USB data
reserved
11
28
EP1-IN
EP1-IN ready to be loaded with data
12
2C
EP1-OUT
EP1-OUT has USB data
13
30
EP2
IN: buffer available. OUT: buffer has data
14
34
EP4
IN: buffer available. OUT: buffer has data
15
38
EP6
IN: buffer available. OUT: buffer has data
16
3C
EP8
IN: buffer available. OUT: buffer has data
17
40
IBN
18
44
IN-Bulk-NAK (any IN endpoint)
reserved
19
48
EP0PING
EP0 OUT was pinged and it NAK’d
20
4C
EP1PING
EP1 OUT was pinged and it NAK’d
21
50
EP2PING
EP2 OUT was pinged and it NAK’d
22
54
EP4PING
EP4 OUT was pinged and it NAK’d
23
58
EP6PING
EP6 OUT was pinged and it NAK’d
24
5C
EP8PING
EP8 OUT was pinged and it NAK’d
25
60
ERRLIMIT
Bus errors exceeded the programmed limit
26
64
–
–
27
68
–
Reserved
28
6C
–
Reserved
29
70
EP2ISOERR
ISO EP2 OUT PID sequence error
30
74
EP4ISOERR
ISO EP4 OUT PID sequence error
31
78
EP6ISOERR
ISO EP6 OUT PID sequence error
32
7C
EP8ISOERR
ISO EP8 OUT PID sequence error
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high
byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs
the jump to the correct address out of the 27 addresses within the page.
Document Number: 38-08032 Rev. AD
Page 7 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual
FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring.
Table 4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
Source
Notes
1
80
EP2PF
Endpoint 2 programmable flag
2
84
EP4PF
Endpoint 4 programmable flag
3
88
EP6PF
Endpoint 6 programmable flag
4
8C
EP8PF
Endpoint 8 programmable flag
5
90
EP2EF
Endpoint 2 empty flag [6]
6
94
EP4EF
Endpoint 4 empty flag
7
98
EP6EF
Endpoint 6 empty flag
8
9C
EP8EF
Endpoint 8 empty flag
9
A0
EP2FF
Endpoint 2 full flag
10
A4
EP4FF
Endpoint 4 full flag
11
A8
EP6FF
Endpoint 6 full flag
12
AC
EP8FF
Endpoint 8 full flag
13
B0
GPIFDONE
14
B4
GPIFWF
GPIF operation complete
GPIF waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the FX 2LP substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX2LP
pushes the program counter to its stack then jumps to address
0x0053, where it expects to find a “jump” instruction to the
interrupt service routine (ISR).
Note
6. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first
transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see
the Errata on page 68.
Document Number: 38-08032 Rev. AD
Page 8 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Reset and Wakeup
Reset Pin
The input pin, RESET#, resets the FX2LP when asserted. This
pin has hysteresis and is active LOW. When a crystal is used with
the CY7C680xxA, the reset period must enable stabilization of
the crystal and the PLL. This reset period must be approximately
5 ms after VCC reaches 3.0 V. If the crystal input pin is driven by
a clock signal, the internal PLL stabilizes in 200 s after VCC has
reached 3.0 V[7].
Figure 2 shows a power-on reset condition and a reset applied
during operation. A power-on reset is defined as the time reset
that is asserted while power is being applied to the circuit. A
powered reset is when the FX2LP is powered on and operating
and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power-on reset implementation. For more
information about reset implementation for the FX2 family of
products, visit http://www.cypress.com.
Figure 2. Reset Timing Plots
RESET#
VIL
RESET#
VIL
3.3V
3.0V
3.3V
VCC
VCC
0V
0V
TRESET
TRESET
Power on Reset
Powered Reset
Wakeup Pins
Table 5. Reset Timing Values
Condition
TRESET
Power-on reset with crystal
5 ms
Power-on reset with external
clock
200 s + clock stability time
Powered reset
200 s
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts after the PLL stabilizes, and the 8051 receives a wakeup
interrupt. This applies irrespective of whether FX2LP is
connected to the USB.
The FX2LP exits the power-down (USB suspend) state by using
one of the following methods:
■
USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
■
External logic asserts the WAKEUP pin
■
External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a
general-purpose I/O pin. This enables a simple external R-C
network to be used as a periodic wakeup source. WAKEUP is by
default active LOW.
Document Number: 38-08032 Rev. AD
Page 9 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Program/Data RAM
suppressed for memory spaces that exist inside the chip. This
enables the user to connect a 64 KB memory without requiring
address decodes to keep clear of internal memory spaces.
Size
The FX2LP has 16 KB of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to enable the 8051 to
access it as both program and data memory. No USB control
registers appears in this space.
■
USB download
Two memory maps are shown in the following diagrams:
■
USB upload
Figure 3 shows the Internal Code Memory, EA = 0.
■
Setup data pointer
■
I2C interface boot load
Figure 4 on page 11 shows the External Code Memory, EA = 1.
Only the internal 16 KB and scratch pad 0.5 KB RAM spaces
have the following access:
Internal Code Memory, EA = 0
External Code Memory, EA = 1
This mode implements the internal 16 KB block of RAM (starting
at 0) as combined code and data memory. When external RAM
or ROM is added, the external read and write strobes are
The bottom 16 KB of program memory is external and therefore
the bottom 16 KB of internal RAM is accessible only as a data
memory.
Figure 3. Internal Code Memory, EA = 0
Inside FX2LP
Outside FX2LP
FFFF
7.5 KB
USB regs and
4K FIFO buffers
(RD#,WR#)
E200
E1FF 0.5 KB RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KB
External
Data
Memory
(RD#,WR#)
48 KB
External
Code
Memory
(PSEN#)
3FFF
16 KB RAM
Code and Data
(PSEN#,RD#,WR#)*
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
0000
Data
Code
*SUDPTR, USB upload/download, I2C interface boot access
Note
7. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 s.
Document Number: 38-08032 Rev. AD
Page 10 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 4. External Code Memory, EA = 1
Inside FX2LP
Outside FX2LP
FFFF
7.5 KB
USB regs and
4K FIFO buffers
(RD#,WR#)
E200
E1FF
0.5 KB RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KB
External
Data
Memory
(RD#,WR#)
64 KB
External
Code
Memory
(PSEN#)
3FFF
16 KB
RAM
Data
(RD#,WR#)*
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
0000
Data
Code
*SUDPTR, USB upload/download, I2C interface boot access
Document Number: 38-08032 Rev. AD
Page 11 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Register Addresses
FFFF
4 KB EP2-EP8
buffers
(8 x 512)
F000
EFFF
2 KB RESERVED
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E3FF
E200
E1FF
64 BEP1IN
64 Bytes EP1OUT
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
(512)
Reserved (128)
128 Bytes GPIF Waveforms
Reserved (512)
512 Bytes
E000
Document Number: 38-08032 Rev. AD
8051 xdata RAM
Page 12 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Endpoint RAM
Setup Data Buffer
Size
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
■
3 × 64 bytes
(Endpoints 0 and 1)
■
8 × 512 bytes
(Endpoints 2, 4, 6, 8)
Endpoint Configurations (Hi-Speed Mode)
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT.
Organization
■
EP0
■
Bidirectional endpoint zero, 64-byte buffer
■
EP1IN, EP1OUT
■
64 byte buffers, bulk or interrupt
■
EP2, 4, 6, 8
■
Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered; EP2 and 6 can be either double,
triple, or quad buffered. For Hi-Speed endpoint configuration
options, see Figure 5.
The endpoint buffers can be configured in any 1 of the 12
configurations shown in the vertical columns. When operating in
the Full-Speed BULK mode, only the first 64 bytes of each buffer
are used. For example, in Hi-Speed mode, the max packet size
is 512 bytes, but in Full-Speed mode, it is 64 bytes. Even though
a buffer is configured to a 512-byte buffer, in Full-Speed mode,
only the first 64 bytes are used. The unused endpoint buffer
space is not available for other operations. An example endpoint
configuration is the EP2–1024 double-buffered; EP6–512
quad-buffered (column 8).
Figure 5. Endpoint Configuration
EP0 IN&OUT
64
64
64
EP1 IN
64
64
64
EP1 OUT
64
64
64
EP2
EP2
EP2
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP2
EP2
EP2
EP2
EP2
EP2
EP2
512
512
512
512
512
512
512
512
512
512
512
512
EP4
EP4
512
512
512
512
512
512
512
512
512
512
512
512
EP6
EP6
EP6
EP6
EP6
EP6
512
512
512
512
512
512
512
512
EP8
1024
512
512
512
1
2
1024
3
Document Number: 38-08032 Rev. AD
1024
1024
1024
1024
512
1024
512
512
512
512
4
5
1024
6
EP6
1024
512
EP6
EP6
512
512
512
512
EP6
512
1024
512
EP8
EP8
512
1024
1024
512
EP4
1024
1024
EP2 EP2
512
512
512
512
512
7
8
1024
9
1024
1024
EP8
EP8
512
512
512
512
10
11
1024
1024
1024
12
Page 13 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Default Full-Speed Alternate Settings
Table 6. Default Full Speed Alternate Settings[8, 9]
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
0
64 bulk
64 int
64 int
ep1in
0
64 bulk
64 int
64 int
ep2
0
64 bulk out (2×)
64 int out (2×)
64 iso out (2×)
ep4
0
64 bulk out (2×)
64 bulk out (2×)
64 bulk out (2×)
ep6
0
64 bulk in (2×)
64 int in (2×)
64 iso in (2×)
ep8
0
64 bulk in (2×)
64 bulk in (2×)
64 bulk in (2×)
Default High Speed Alternate Settings
Table 7. Default Hi-Speed Alternate Settings[8, 9]
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
0
512 bulk[10]
64 int
64 int
ep1in
0
512
bulk[10]
64 int
64 int
ep2
0
512 bulk out (2×)
512 int out (2×)
512 iso out (2×)
ep4
0
512 bulk out (2×)
512 bulk out (2×)
512 bulk out (2×)
ep6
0
512 bulk in (2×)
512 int in (2×)
512 iso in (2×)
ep8
0
512 bulk in (2×)
512 bulk in (2×)
512 bulk in (2×)
Notes
8. “0” means “not implemented.”
9. “2×” means “double buffered.”
10. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Document Number: 38-08032 Rev. AD
Page 14 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
External FIFO Interface
Architecture
The FX2LP slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals and the slave FIFO interface for externally
controlled transfers.
Master/Slave Control Signals
The FX2LP endpoint FIFOs are implemented as eight physically
distinct 25616 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domains, the USB (SIE) domain and
the 8051-I/O Unit domain. This switching is done virtually
instantaneously, giving essentially zero transfer time between
“USB FIFOs” and “Slave FIFOs.” Because they are physically
the same memory, no bytes are actually transferred between
buffers.
At any time, some RAM blocks are filling/emptying with the USB
data under SIE control, while other RAM blocks are available to
the 8051, the I/O control unit, or both. The RAM blocks operates
as single-port in the USB domain, and dual-port in the 8051-I/O
domain. The blocks can be configured as single-, double-, triple-,
or quad-buffered as previously shown.
The I/O control unit implements either an internal master (M for
Master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) can be used as flag inputs
from an external FIFO or other logic if desired. The GPIF can be
run from either an internally derived clock or externally supplied
clock (IFCLK), at a rate that transfers data up to 96 MBytes/s
(48 Hz IFCLK with 16-bit interface).
In the Slave (S) mode, FX2LP accepts either an internally
derived clock or externally supplied clock (IFCLK, max frequency
48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
from external logic. When using an external IFCLK, the external
clock must be present before switching to the external clock with
the IFCLKSRC bit. Each endpoint can individually be selected
for byte or word operation by an internal configuration bit and a
Slave FIFO Output Enable signal (SLOE) that enables data of
the selected width. External logic must ensure that the output
enable signal is inactive when writing data to a slave FIFO. The
slave interface can also operate asynchronously, where the
SLRD and SLWR signals act directly as strobes, rather than a
clock qualifier as in synchronous mode. The signals SLRD,
SLWR, SLOE, and PKTEND are gated by the signal SLCS#.
GPIF and FIFO Clock Rates
Alternatively, an externally supplied clock of 5 MHz–48 MHz
feeding the IFCLK pin can be used as the interface clock. IFCLK
can be configured to function as an output clock when the GPIF
and FIFOs are internally clocked. An output enable bit in the
IFCONFIG register turns this clock output off, if desired. Another
bit within the IFCONFIG register inverts the IFCLK signal
whether internally or externally sourced.
GPIF
The GPIF is a flexible 8-bit or 16-bit parallel interface driven by
a user-programmable finite state machine. It enables the
CY7C68013A/15A to perform local bus mastering and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF
vector defines the state of the control outputs, and determines
what state a ready input (or multiple inputs) must be before
proceeding. The GPIF vector can be programmed to advance a
FIFO to the next data value, advance an address, etc. A
sequence of the GPIF vectors make up a single waveform that
is executed to perform the desired data move between the
FX2LP and the external device.
Six Control OUT Signals
The 100-pin and 128-pin packages bring out all six Control
Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to
define the CTL waveforms. The 56-pin package brings out three
of these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock
(20.8 ns using a 48-MHz clock).
Six Ready IN Signals
The 100-pin and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out two
of these signals, RDY0–1.
Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100-pin and 128-pin
packages, GPIFADR[8..0]. The GPIF address lines enable
indexing through up to a 512-byte block of RAM. If more address
lines are needed, then I/O port pins are used.
Long Transfer Mode
In the master mode, the 8051 appropriately sets GPIF
transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,
or GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz.
Document Number: 38-08032 Rev. AD
Page 15 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
ECC Generation
[11]
The EZ-USB can calculate ECCs (Error Correcting Codes) on
data that passes across its GPIF or Slave FIFO interfaces. There
are two ECC configurations: Two ECCs, each calculated over
256 bytes (SmartMedia Standard); and one ECC calculated over
512 bytes.
The ECC can correct any one-bit error or detect any two-bit error.
ECC Implementation
The two ECC configurations are selected by the ECCM bit:
ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of data.
This configuration conforms to the SmartMedia Standard.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 256 bytes of data
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values
in the ECCx registers do not change until ECCRESET is written
again, even if more data is subsequently passed across the
interface.
ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 bytes of data
is calculated and stored in ECC1; ECC2 is unused. After the
ECC is calculated, the values in ECC1 do not change even if
more data is subsequently passed across the interface, till
ECCRESET is written again.
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16-KB RAM and of the internal 512-byte scratch pad
RAM via a vendor-specific command. This capability is normally
used when soft downloading the user code and is available only
to and from the internal RAM, only when the 8051 is held in reset.
The available RAM spaces are 16 KB from 0x0000–0x3FFF
(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad
data RAM)[12].
Autopointer Access
FX2LP provides two identical autopointers. They are similar to
the internal 8051 data pointers but with an additional feature:
they can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. Autopointers are available in external FX2LP registers
under the control of a mode bit (AUTOPTRSET-UP.0). Using the
external FX2LP autopointer access (at 0xE67B–0xE67C)
enables the autopointer to access all internal and external RAM
to the part.
Also, autopointers can point to any FX2LP register or endpoint
buffer space. When the autopointer access to external memory
is enabled, locations 0xE67B and 0xE67C in XDATA and code
space cannot be used.
I2C Controller
FX2LP has one I2C port that is driven by two internal controllers,
the one that automatically operates at boot time to load
VID/PID/DID and configuration information, and another that the
8051 uses when running to control external I2C devices. The I2C
port operates in master mode only.
I2C Port Pins
The I2C pins SCL and SDA must have external 2.2-k pull-up
resistors even if no EEPROM is connected to the FX2LP.
External EEPROM device address pins must be configured
properly. See Table 8 for configuring the device address pins.
Table 8. Strap Boot EEPROM Address Lines to These Values
Bytes
Example EEPROM
A2
A1
A0
16
24LC00[13]
N/A
N/A
N/A
128
24LC01
0
0
0
256
24LC02
0
0
0
4K
24LC32
0
0
1
8K
24LC64
0
0
1
16K
24LC128
0
0
1
I2C Interface Boot Load Access
At power-on reset, the I2C interface boot loader loads the
VID/PID/DID configuration bytes and up to 16 KB of
program/data. The available RAM spaces are 16 KB from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is in reset. I2C interface boot loads only occur after power-on
reset.
I2C Interface General-Purpose Access
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DAT registers. FX2LP provides I2C master
control only; it is never an I2C slave.
Notes
11. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
12. After the data is downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.
13. This EEPROM does not have address pins.
Document Number: 38-08032 Rev. AD
Page 16 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Compatible with Previous Generation EZ-USB FX2
CY7C68013A/14A and CY7C68015A/16A Differences
The EZ-USB FX2LP is form-, fit-, and with minor exceptions,
functionally-compatible with its predecessor, the EZ-USB FX2.
This makes for an easy transition for designers wanting to
upgrade their systems from the FX2 to the FX2LP. The pinout
and package selection are identical and a vast majority of
firmware previously developed for the FX2 functions in the
FX2LP.
CY7C68013A is identical to CY7C68014A in form, fit, and
functionality. CY7C68015A is identical to CY7C68016A in form,
fit, and functionality. CY7C68014A and CY7C68016A have a
lower suspend current than CY7C68013A and CY7C68015A
respectively and are ideal for power-sensitive battery
applications.
For designers migrating from the FX2 to the FX2LP, a change in
the bill of material and review of the memory allocation (due to
increased internal memory) is required. For more information
about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the
application note titled Migrating from EZ-USB FX2 to EZ-USB
FX2LP available in the Cypress web site.
Table 9. Part Number Conversion Table
EZ-USB FX2
Part Number
CY7C68013-56PVC
EZ-USB FX2LP
Part Number
Package
Description
CY7C68013A-56PVXC or 56-pin
CY7C68014A-56PVXC
SSOP
56-pin
CY7C68013A-56PVXCT or SSOP –
CY7C68013-56PVCT
CY7C68014A-56PVXCT Tape and
Reel
CY7C68013-56LFC
CY7C68013A-56LFXC or
56-pin QFN
CY7C68014A-56LFXC
CY7C68013-100AC
CY7C68013A-100AXC or 100-pin
CY7C68014A-100AXC
TQFP
CY7C68013-128AC
CY7C68013A-128AXC or 128-pin
CY7C68014A-128AXC
TQFP
Document Number: 38-08032 Rev. AD
CY7C68015A and CY7C68016A are available in 56-pin QFN
package only. Two additional GPIO signals are available on the
CY7C68015A and CY7C68016A to provide more flexibility when
neither IFCLK or CLKOUT are needed in the 56-pin package.
USB developers wanting to convert their FX2 56-pin application
to a bus-powered system directly benefit from these additional
signals. The two GPIOs give developers the signals they need
for the power-control circuitry of their bus-powered application
without pushing them to a high-pincount version of FX2LP.
The CY7C68015A is only available in the 56-pin QFN package
Table 10. CY7C68013A/14A and CY7C68015A/16A
Pin Differences
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
IFCLK
PE0
CLKOUT
PE1
Page 17 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Pin Assignments
Figure 6 on page 19 identifies all signals for the five package
types. The following pages illustrate the individual pin diagrams,
plus a combination diagram showing which of the full set of
signals are available in the 128-pin, 100-pin, and 56-pin
packages.
The signals on the left edge of the 56-pin package in Figure 6
on page 19 are common to all versions in the FX2LP family with
the noted differences between the CY7C68013A/14A and the
CY7C68015A/16A.
Three modes are available in all package versions: Port, GPIF
master, and Slave FIFO. These modes define the signals on the
right edge of the diagram. The 8051 selects the interface mode
using the IFCONFIG[1:0] register bits. Port mode is the power on
default configuration.
The 100-pin package adds functionality to the 56-pin package by
adding these pins:
■
PORTC or alternate GPIFADR[7:0] address signals
■
PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
■
Three GPIF Control signals
■
Four GPIF Ready signals
■
Nine 8051 signals (two USARTs, three timer inputs, INT4, and
INT5#)
■
BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version.
In the 100-pin and 128-pin versions, an 8051 control bit can be
set to pulse the RD# and WR# pins when the 8051 reads
from/writes to PORTC. This feature is enabled by setting the
PORTCSTB bit in the CPUCS register.
PORTC Strobe Feature Timings on page 46 displays the timing
diagram of the read and write strobing function on accessing
PORTC.
Document Number: 38-08032 Rev. AD
Page 18 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 6. Signal
Port
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
56
**PE0 replaces IFCLK
& PE1 replaces CLKOUT
on CY7C68015A/16A
**PE0
**PE1
IFCLK
CLKOUT
DPLUS
DMINUS
GPIF Master
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
100
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
128
Document Number: 38-08032 Rev. AD
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
RDY0
RDY1
SLRD
SLWR
CTL0
CTL1
CTL2
FLAGA
FLAGB
FLAGC
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
T1
T0
RD#
WR#
CS#
OE#
PSEN#
D7
D6
D5
D4
D3
D2
D1
D0
EA
Slave FIFO
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Page 19 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 7. CY7C68013A/CY7C68014A 128-Pin TQFP Pin Assignment
27
28
29
30
31
32
33
34
35
36
37
38
103
26
104
25
105
24
106
23
107
22
108
21
109
20
110
19
111
18
112
17
113
16
114
15
115
14
116
13
117
12
118
11
119
10
120
9
121
8
122
7
123
6
124
5
125
4
126
3
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
2
127
128
1
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
CY7C68013A/CY7C68014A
128-pin TQFP
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
* denotes programmable polarity
Document Number: 38-08032 Rev. AD
Page 20 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 8. CY7C68013A/CY7C68014A 100-Pin TQFP Pin Assignment
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
SCL
SDA
CY7C68013A/CY7C68014A
100-pin TQFP
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
* denotes programmable polarity
Document Number: 38-08032 Rev. AD
Page 21 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 9. CY7C68013A/CY7C68014A 56-Pin SSOP Pin Assignment
CY7C68013A/CY7C68014A
56-pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* denotes programmable polarity
Document Number: 38-08032 Rev. AD
Page 22 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 10. CY7C68013A/14A/15A/16A 56-Pin QFN Pin Assignment
GND
VCC
CLKOUT/**PE1
GND
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RDY0/*SLRD
1
42
RESET#
RDY1/*SLWR
2
41
GND
AVCC
3
40
PA7/*FLAGD/SLCS#
XTALOUT
4
39
PA6/*PKTEND
XTALIN
5
38
PA5/FIFOADR1
AGND
6
37
PA4/FIFOADR0
AVCC
7
36
PA3/*WU2
DPLUS
8
35
PA2/*SLOE
DMINUS
9
34
PA1/INT1#
AGND
10
33
PA0/INT0#
VCC
11
32
VCC
GND
12
31
CTL2/*FLAGC
*IFCLK/**PE0
13
30
CTL1/*FLAGB
RESERVED
14
29
CTL0/*FLAGA
CY7C68013A/CY7C68014A
&
CY7C68015A/CY7C68016A
56-pin QFN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
GND
VCC
GND
* denotes programmable polarity
** denotes CY7C68015A/CY7C68016A pinout
Document Number: 38-08032 Rev. AD
Page 23 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment – Top View
1
2
3
4
5
6
7
8
A
1A
2A
3A
4A
5A
6A
7A
8A
B
1B
2B
3B
4B
5B
6B
7B
8B
C
1C
2C
3C
4C
5C
6C
7C
8C
D
1D
2D
7D
8D
E
1E
2E
7E
8E
F
1F
2F
3F
4F
5F
6F
7F
8F
G
1G
2G
3G
4G
5G
6G
7G
8G
H
1H
2H
3H
4H
5H
6H
7H
8H
Document Number: 38-08032 Rev. AD
Page 24 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
CY7C68013A/15A Pin Descriptions
Table 11. FX2LP Pin Descriptions[14]
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[15]
Description
10
9
10
3
2D
AVCC
Power
N/A
N/A
Analog VCC. Connect this pin to the 3.3 V power
source. This signal provides power to the analog
section of the chip.
17
16
14
7
1D
AVCC
Power
N/A
N/A
Analog VCC. Connect this pin to the 3.3 V power
source. This signal provides power to the analog
section of the chip.
13
12
13
6
2F
AGND
Ground
N/A
N/A
Analog Ground. Connect to ground with as short
a path as possible.
20
19
17
10
1F
AGND
Ground
N/A
N/A
Analog Ground. Connect to ground with as short
a path as possible.
19
18
16
9
1E
DMINUS
I/O/Z
Z
N/A
USB D– Signal. Connect to the USB D– signal.
2E
DPLUS
USB D+ Signal. Connect to the USB D+ signal.
18
I/O/Z
Z
N/A
94
–
17
–
15
–
8
–
A0
Output
L
L
95
–
–
–
–
A1
Output
L
L
96
–
–
–
–
A2
Output
L
L
97
–
–
–
–
A3
Output
L
L
117 –
–
–
–
A4
Output
L
L
118 –
–
–
–
A5
Output
L
L
119 –
–
–
–
A6
Output
L
L
120 –
–
–
–
A7
Output
L
L
126 –
–
–
–
A8
Output
L
L
127 –
–
–
–
A9
Output
L
L
128 –
–
–
–
A10
Output
L
L
21
–
–
–
–
A11
Output
L
L
22
–
–
–
–
A12
Output
L
L
23
–
–
–
–
A13
Output
L
L
24
–
–
–
–
A14
Output
L
L
25
–
–
–
–
A15
Output
L
L
59
–
–
–
–
D0
I/O/Z
Z
Z
60
–
–
–
–
D1
I/O/Z
Z
Z
61
–
–
–
–
D2
I/O/Z
Z
Z
62
–
–
–
–
D3
I/O/Z
Z
Z
63
–
–
–
–
D4
I/O/Z
Z
Z
86
–
–
–
–
D5
I/O/Z
Z
Z
87
–
–
–
–
D6
I/O/Z
Z
Z
88
–
–
–
–
D7
I/O/Z
Z
Z
39
–
–
–
–
PSEN#
Output
H
H
8051 Address Bus. This bus is driven at all times.
When the 8051 is addressing internal RAM it
reflects the internal address.
8051 Data Bus. This bidirectional bus is
high impedance when inactive, input for bus reads,
and output for bus writes. The data bus is used for
external 8051 program and data memory. The data
bus is active only for external bus accesses, and is
driven LOW in suspend.
Program Store Enable. This active LOW signal
indicates an 8051 code fetch from external
memory. It is active for program memory fetches
from 0x4000–0xFFFF when the EA pin is LOW, or
from 0x0000–0xFFFF when the EA pin is HIGH.
Notes
14. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in
standby. Note also that no pins should be driven while the device is powered down.
15. The Reset column indicates the state of signals during reset (RESET# asserted) or during Power on Reset (POR).
Document Number: 38-08032 Rev. AD
Page 25 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
34
28
–
–
99
77
49
42
35
12
11
1
–
11
10
100
–
12
11
5
–
5
4
54
Name
BKPT
8B
–
1C
RESET#
EA
XTALIN
Type
Default Reset[15]
Description
Output
L
L
Breakpoint. This pin goes active (HIGH) when the
8051 address bus matches the BPADDRH/L
registers and breakpoints are enabled in the
BREAKPT register (BPEN = 1). If the BPPULSE bit
in the BREAKPT register is HIGH, this signal
pulses HIGH for eight 12-/24-/48-MHz clocks. If the
BPPULSE bit is LOW, the signal remains HIGH
until the 8051 clears the BREAK bit (by writing 1 to
it) in the BREAKPT register.
Input
N/A
N/A
Active LOW Reset. Resets the entire chip. See
section ”Reset and Wakeup” on page 9 for more
details.
N/A
External Access. This pin determines where the
8051 fetches code between addresses 0x0000 and
0x3FFF. If EA = 0 the 8051 fetches this code from
its internal RAM. IF EA = 1 the 8051 fetches this
code from external memory.
N/A
Crystal Input. Connect this signal to a 24-MHz
parallel-resonant, fundamental mode crystal and
load capacitor to GND.
It is also correct to drive XTALIN with an external
24-MHz square wave derived from another clock
source. When driving from an external source, the
driving signal should be a 3.3-V square wave.
N/A
Crystal Output. Connect this signal to a 24-MHz
parallel-resonant, fundamental mode crystal and
load capacitor to GND.
If an external clock is used to drive XTALIN, leave
this pin open.
Input
Input
Output
N/A
N/A
2C
XTALOUT
N/A
2B
CLKOUT on
Clock
CLKOUT: 12-, 24- or 48-MHz clock, phase-locked
CY7C68013A
O/Z 12 MHz
Driven
to the 24-MHz input clock. The 8051 defaults to
and
12-MHz operation. The 8051 may three-state this
CY7C68014A
output by setting CPUCS.1 = 1.
-------------------------------------------------------------------------------------------PE1 on
---------- ---------Z
------PE1 is a bidirectional I/O port pin.
I
CY7C68015A
and
I/O/Z
CY7C68016A
8G
Multiplexed pin whose function is selected by
PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input
signal, which is either edge-triggered (IT0 = 1) or
level-triggered (IT0 = 0).
Port A
82
83
67
68
40
41
33
34
6G
PA0 or
INT0#
PA1 or
INT1#
Document Number: 38-08032 Rev. AD
I/O/Z
I/O/Z
I
(PA0)
I
(PA1)
Z
(PA0)
Z
(PA1)
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input
signal, which is either edge-triggered (IT1 = 1) or
level-triggered (IT1 = 0).
Page 26 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
84
85
89
90
91
92
69
70
71
72
73
74
42
43
44
45
46
47
35
36
37
38
39
40
8F
7F
6F
8C
7C
Name
PA2 or
SLOE
PA3 or
WU2
PA4 or
FIFOADR0
PA5 or
FIFOADR1
PA6 or
PKTEND
6C
PA7 or
FLAGD or
SLCS#
3H
PB0 or
FD[0]
4F
PB1 or
FD[1]
4H
PB2 or
FD[2]
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default Reset[15]
I
(PA2)
I
(PA3)
I
(PA4)
I
(PA5)
I
(PA6)
Z
(PA2)
Description
Multiplexed pin whose function is selected by two
bits:
IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with programmable polarity (FIFOPINPOLAR.4) for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Z
(PA3)
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup,
enabled by WU2EN bit (WAKEUP.1) and polarity
set by WU2POL (WAKEUP.4). If the 8051 is in
suspend and WU2EN = 1, a transition on this pin
starts up the oscillator and interrupts the 8051 to
enable it to exit the suspend mode. Asserting this
pin inhibits the chip from suspending if WU2EN = 1.
Z
(PA4)
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the
slave FIFOs connected to FD[7..0] or FD[15..0].
Z
(PA5)
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the
slave FIFOs connected to FD[7..0] or FD[15..0].
Z
(PA6)
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO
packet data to the endpoint and whose polarity is
programmable via FIFOPINPOLAR.5.
Z
(PA7)
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output
status flag signal.
SLCS# gates all other slave FIFO enable/strobes
I/O/Z
I
(PA7)
I/O/Z
I
(PB0)
I/O/Z
I
(PB1)
Z
(PB1)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PB2)
Z
(PB2)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
Port B
44
45
46
34
35
36
25
26
27
18
19
20
Document Number: 38-08032 Rev. AD
Z
(PB0)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
Page 27 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
47
54
55
56
57
37
44
45
46
47
28
29
30
31
32
21
22
23
24
25
Name
4G
PB3 or
FD[3]
5H
PB4 or
FD[4]
5G
PB5 or
FD[5]
5F
PB6 or
FD[6]
6H
PB7 or
FD[7]
Type
Default Reset[15]
Description
I/O/Z
I
(PB3)
Z
(PB3)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PB4)
Z
(PB4)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PB5)
Z
(PB5)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PB6)
Z
(PB6)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PB7)
Z
(PB7)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PC0)
I/O/Z
I
(PC1)
I/O/Z
I
(PC2)
Z
(PC2)
Multiplexed pin whose function is selected by
PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
I/O/Z
I
(PC3)
Z
(PC3)
Multiplexed pin whose function is selected by
PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
I/O/Z
I
(PC4)
Z
(PC4)
Multiplexed pin whose function is selected by
PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
I/O/Z
I
(PC5)
Z
(PC5)
Multiplexed pin whose function is selected by
PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
I/O/Z
I
(PC6)
Z
(PC6)
Multiplexed pin whose function is selected by
PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
I/O/Z
I
(PC7)
Z
(PC7)
Multiplexed pin whose function is selected by
PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT C
72
73
74
75
76
77
78
79
57
58
59
60
61
62
63
64
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PC0 or
GPIFADR0
PC1 or
GPIFADR1
PC2 or
GPIFADR2
–
PC3 or
GPIFADR3
–
PC4 or
GPIFADR4
–
PC5 or
GPIFADR5
–
PC6 or
GPIFADR6
–
PC7 or
GPIFADR7
Document Number: 38-08032 Rev. AD
Z
(PC0)
Z
(PC1)
Multiplexed pin whose function is selected by
PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
Page 28 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[15]
Description
PORT D
102
103
104
105
121
122
123
124
80
81
82
83
95
96
97
98
52
53
54
55
56
1
2
3
45
46
47
48
49
50
51
52
8A
PD0 or
FD[8]
7A
PD1 or
FD[9]
6B
PD2 or
FD[10]
6A
PD3 or
FD[11]
3B
PD4 or
FD[12]
3A
PD5 or
FD[13]
3C
PD6 or
FD[14]
2A
PD7 or
FD[15]
I/O/Z
I
(PD0)
Z
(PD0)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PD1)
Z
(PD1)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PD2)
Z
(PD2)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PD3)
Z
(PD3)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PD4)
Z
(PD4)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PD5)
Z
(PD5)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PD6)
Z
(PD6)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
I/O/Z
I
(PD7)
Z
(PD7)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)
bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Z
(PE0)
Multiplexed pin whose function is selected by the
PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051
Timer-counter0. T0OUT outputs a high level for
one CLKOUT clock cycle when Timer0 overflows.
If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte
timer/counter overflows.
Z
(PE1)
Multiplexed pin whose function is selected by the
PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active HIGH signal from 8051
Timer-counter1. T1OUT outputs a high level for
one CLKOUT clock cycle when Timer1 overflows.
If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte
timer/counter overflows.
Port E
108
109
86
87
–
–
–
–
–
–
PE0 or
T0OUT
PE1 or
T1OUT
Document Number: 38-08032 Rev. AD
I/O/Z
I/O/Z
I
(PE0)
I
(PE1)
Page 29 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
110
111
112
113
114
115
4
88
89
90
91
92
93
3
–
–
–
–
–
–
8
–
–
–
–
–
–
1
–
–
–
–
Name
PE2 or
T2OUT
PE3 or
RXD0OUT
PE4 or
RXD1OUT
PE5 or
INT6
–
PE6 or
T2EX
–
PE7 or
GPIFADR8
1A
5
4
9
2
1B
6
5
–
–
–
RDY0 or
SLRD
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default Reset[15]
I
(PE2)
I
(PE3)
I
(PE4)
I
(PE5)
Description
Z
(PE2)
Multiplexed pin whose function is selected by the
PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active HIGH output signal from 8051
Timer2. T2OUT is active (HIGH) for one clock cycle
when Timer/Counter 2 overflows.
Z
(PE3)
Multiplexed pin whose function is selected by the
PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active HIGH signal from 8051
UART0. If RXD0OUT is selected and UART0 is in
Mode 0, this pin provides the output data for
UART0 only when it is in sync mode. Otherwise it
is a 1.
Z
(PE4)
Multiplexed pin whose function is selected by the
PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051
UART1. When RXD1OUT is selected and UART1
is in Mode 0, this pin provides the output data for
UART1 only when it is in sync mode. In Modes 1,
2, and 3, this pin is HIGH.
Z
(PE5)
Multiplexed pin whose function is selected by the
PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input
signal. The INT6 pin is edge-sensitive, active
HIGH.
I/O/Z
I
(PE6)
Z
(PE6)
Multiplexed pin whose function is selected by the
PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active HIGH input signal to the 8051
Timer2. T2EX reloads timer 2 on its falling edge.
T2EX is active only if the EXEN2 bit is set in
T2CON.
I/O/Z
I
(PE7)
Z
(PE7)
Multiplexed pin whose function is selected by the
PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
N/A
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Input
N/A
RDY1 or
SLWR
Input
N/A
N/A
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave
FIFOs connected to FD[7..0] or FD[15..0].
RDY2
Input
N/A
N/A
RDY2 is a GPIF input signal.
Document Number: 38-08032 Rev. AD
Page 30 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[15]
Description
7
6
–
–
–
RDY3
Input
N/A
N/A
RDY3 is a GPIF input signal.
8
7
–
–
–
RDY4
Input
N/A
N/A
RDY4 is a GPIF input signal.
9
8
–
–
–
RDY5
Input
N/A
N/A
RDY5 is a GPIF input signal.
69
70
54
55
36
37
29
30
7H
7G
CTL0 or
FLAGA
CTL1 or
FLAGB
O/Z
O/Z
H
H
L
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output
status flag signal.
Defaults to programmable for the FIFO selected by
the FIFOADR[1:0] pins.
L
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output
status flag signal.
Defaults to FULL for the FIFO selected by the
FIFOADR[1:0] pins.
CTL2 or
FLAGC
O/Z
H
L
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output
status flag signal.
Defaults to EMPTY for the FIFO selected by the
FIFOADR[1:0] pins.
–
CTL3
O/Z
H
L
CTL3 is a GPIF control output.
–
–
CTL4
Output
H
L
CTL4 is a GPIF control output.
–
–
CTL5
Output
H
L
CTL5 is a GPIF control output.
71
56
38
31
8H
66
51
–
–
67
52
–
98
76
–
IFCLK on
CY7C68013A
and
CY7C68014A
Interface Clock, used for synchronously clocking
data into or out of the slave FIFOs. IFCLK also
serves as a timing reference for all slave FIFO
control signals and GPIF. When internal clocking is
used (IFCONFIG.7 = 1) the IFCLK pin can be
configured to output 30/48 MHz by bits
IFCONFIG.5 and IFCONFIG.6. IFCLK may be
inverted, whether internally or externally sourced,
by setting the bit IFCONFIG.4 =1.
-----------------PE0 on
---------- ---------- ---------- ---------------------------------------------------------------------CY7C68015A
–
I
Z
PE0 is a bidirectional I/O port pin.
and
I/O/Z
CY7C68016A
I/O/Z
Z
Z
32
26
20
13
2G
28
22
–
–
–
INT4
Input
N/A
N/A
INT4 is the 8051 INT4 interrupt request input
signal. The INT4 pin is edge-sensitive, active
HIGH.
106
84
–
–
–
INT5#
Input
N/A
N/A
INT5# is the 8051 INT5 interrupt request input
signal. The INT5 pin is edge-sensitive, active LOW.
N/A
T2 is the active HIGH T2 input signal to 8051
Timer2, which provides the input to Timer2 when
C/T2 = 1. When C/T2 = 0, Timer2 does not use this
pin.
31
25
–
–
–
T2
Document Number: 38-08032 Rev. AD
Input
N/A
Page 31 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[15]
Description
30
24
–
–
–
T1
Input
N/A
N/A
T1 is the active HIGH T1 signal for 8051 Timer1,
which provides the input to Timer1 when C/T1 is 1.
When C/T1 is 0, Timer1 does not use this bit.
29
23
–
–
–
T0
Input
N/A
N/A
T0 is the active HIGH T0 signal for 8051 Timer0,
which provides the input to Timer0 when C/T0 is 1.
When C/T0 is 0, Timer0 does not use this bit.
53
43
–
–
–
RXD1
Input
N/A
N/A
RXD1is an active HIGH input signal for 8051
UART1, which provides data to the UART in all
modes.
52
42
–
–
–
TXD1
Output
H
L
TXD1is an active HIGH output pin from 8051
UART1, which provides the output clock in sync
mode, and the output data in async mode.
51
41
–
–
–
RXD0
Input
N/A
N/A
RXD0 is the active HIGH RXD0 input to 8051
UART0, which provides data to the UART in all
modes.
50
40
–
–
–
TXD0
Output
H
L
TXD0 is the active HIGH TXD0 output from 8051
UART0, which provides the output clock in sync
mode, and the output data in async mode.
–
–
–
CS#
Output
H
H
CS# is the active LOW chip select for external
memory.
42
41
32
–
–
–
WR#
Output
H
H
WR# is the active LOW write strobe output for
external memory.
40
31
–
–
–
RD#
Output
H
H
RD# is the active LOW read strobe output for
external memory.
–
–
–
OE#
Output
H
H
OE# is the active LOW output enable for external
memory.
21
14
2H
Input
N/A
N/A
Reserved. Connect to ground.
N/A
USB Wakeup. If the 8051 is in suspend, asserting
this pin starts up the oscillator and interrupts the
8051 to enable it to exit the suspend mode. Holding
WAKEUP asserted inhibits the EZ-USB chip from
suspending. This pin has programmable polarity
(WAKEUP.4).
38
33
101
36
27
79
29
51
22
44
15
7B
3F
Reserved
WAKEUP
SCL
Input
OD
N/A
Z
Z
Clock for the I2C interface. Connect to VCC with a
(if
2.2-k resistor, even if no I2C peripheral is
booting
attached.
is done)
Z
Data for I2C compatible interface. Connect to
(if
VCC with a 2.2-k resistor, even if no I2C
booting
compatible peripheral is attached.
is done)
37
30
23
16
3G
SDA
OD
Z
2
1
6
55
5A
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
26
20
18
11
1G
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
43
33
24
17
7E
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
48
38
–
–
–
VCC
Power
N/A
N/A
VCC. Connect to 3.3-V power source.
64
49
34
27
8E
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
68
53
–
–
–
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
81
66
39
32
5C
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
Document Number: 38-08032 Rev. AD
Page 32 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 11. FX2LP Pin Descriptions[14] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[15]
Description
100
78
50
43
5B
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
107
85
–
–
–
VCC
Power
N/A
N/A
VCC. Connect to the 3.3-V power source.
3
2
7
56
4B
GND
Ground
N/A
N/A
Ground
27
21
19
12
1H
GND
Ground
N/A
N/A
Ground
49
39
–
–
–
GND
Ground
N/A
N/A
Ground
58
48
33
26
7D
GND
Ground
N/A
N/A
Ground
65
50
35
28
8D
GND
Ground
N/A
N/A
Ground
80
65
–
–
–
GND
Ground
N/A
N/A
Ground
93
75
48
41
4C
GND
Ground
N/A
N/A
Ground
116
94
–
–
–
GND
Ground
N/A
N/A
Ground
125
99
4
53
4A
GND
Ground
N/A
N/A
Ground
14
13
–
–
–
NC
N/A
N/A
N/A
No Connect. This pin must be left open.
15
14
–
–
–
NC
N/A
N/A
N/A
No Connect. This pin must be left open.
16
15
–
–
–
NC
N/A
N/A
N/A
No Connect. This pin must be left open.
Document Number: 38-08032 Rev. AD
Page 33 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 12. FX2LP Register Summary
Hex Size
Name
Description
b7
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform
D7
Descriptor 0, 1, 2, 3 data
E480 128 reserved
GENERAL CONFIGURATION
E50D
GPCR2
General Purpose Configu- reserved
ration Register 2
E600 1
E601 1
CPUCS
IFCONFIG
E602 1
PINFLAGSAB[16]
E603 1
[16]
PINFLAGSCD
E604 1
FIFORESET[16]
E605
E606
E607
E608
BREAKPT
BPADDRH
BPADDRL
UART230
1
1
1
1
E609 1
FIFOPINPOLAR[16]
E60A 1
REVID
E60B 1
REVCTL[16]
E60C 1
3
E610 1
E611 1
E612
E613
E614
E615
1
1
1
1
2
E618 1
E619 1
E61A 1
E61B 1
E61C 4
E620 1
E621 1
E622 1
E623 1
E624 1
E625 1
E626 1
E627 1
E628 1
E629 1
E62A 1
CPU Control & Status
Interface Configuration
(Ports, GPIF, slave FIFOs)
Slave FIFO FLAGA and
FLAGB Pin Configuration
Slave FIFO FLAGC and
FLAGD Pin Configuration
Restore FIFOS to default
state
Breakpoint Control
Breakpoint Address H
Breakpoint Address L
230 Kbaud internally
generated ref. clock
Slave FIFO Interface pins
polarity
Chip Revision
Chip Revision Control
UDMA
GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA)
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
Endpoint 1-OUT
Configuration
EP1INCFG
Endpoint 1-IN
Configuration
EP2CFG
Endpoint 2 Configuration
EP4CFG
Endpoint 4 Configuration
EP6CFG
Endpoint 6 Configuration
EP8CFG
Endpoint 8 Configuration
reserved
EP2FIFOCFG[16]
Endpoint 2 / slave FIFO
configuration
[16]
EP4FIFOCFG
Endpoint 4 / slave FIFO
configuration
[16]
EP6FIFOCFG
Endpoint 6 / slave FIFO
configuration
EP8FIFOCFG[16]
Endpoint 8 / slave FIFO
configuration
reserved
[16
EP2AUTOINLENH
Endpoint 2 AUTOIN
Packet Length H
[16]
EP2AUTOINLENL
Endpoint 2 AUTOIN
Packet Length L
EP4AUTOINLENH[16] Endpoint 4 AUTOIN
Packet Length H
EP4AUTOINLENL[16] Endpoint 4 AUTOIN
Packet Length L
EP6AUTOINLENH[16] Endpoint 6 AUTOIN
Packet Length H
EP6AUTOINLENL[16] Endpoint 6 AUTOIN
Packet Length L
EP8AUTOINLENH[16] Endpoint 8 AUTOIN
Packet Length H
EP8AUTOINLENL[16] Endpoint 8 AUTOIN
Packet Length L
ECCCFG
ECC Configuration
ECCRESET
ECC Reset
ECC1B0
ECC1 Byte 0 Address
b6
b5
D6
D5
reserved
reserved
b4
D4
b3
D3
b2
b1
b0
Default
Access
D2
D1
D0
xxxxxxxx RW
reserved
reserved
reserved
00000000 R
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES
IFCFG0
00000010 rrbbbbbr
10000000 RW
0
IFCLKSRC
0
3048MHZ
FULL_reserved
SPEED_ONLY
PORTCSTB CLKSPD1
CLKSPD0
IFCLKOE
IFCLKPOL ASYNC
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000 RW
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000 RW
NAKALL
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx W
0
A15
A7
0
0
A14
A6
0
0
A13
A5
0
0
A12
A4
0
BREAK
A11
A3
0
BPPULSE
A10
A2
0
BPEN
A9
A1
230UART1
0
A8
A0
230UART0
00000000
xxxxxxxx
xxxxxxxx
00000000
0
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000 rrbbbbbb
rv7
rv6
rv5
rv4
rv3
rv2
rv1
rv0
0
0
0
0
0
0
dyn_out
enh_pkt
RevA
R
00000001
00000000 rrrrrrbb
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
VALID
VALID
VALID
VALID
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
SIZE
0
SIZE
0
0
0
0
0
BUF1
0
BUF1
0
BUF0
0
BUF0
0
10100010
10100000
11100010
11100000
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
0
x
LINE15
0
x
LINE14
0
x
LINE13
0
x
LINE12
0
x
LINE11
0
x
LINE10
0
x
LINE9
ECCM
x
LINE8
00000000 rrrrrrrb
00000000 W
00000000 R
rrrrbbbr
RW
RW
rrrrrrbb
bbbbbrbb
bbbbrrrr
bbbbbrbb
bbbbrrrr
Note
16. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”
Document Number: 38-08032 Rev. AD
Page 34 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex
E62B
E62C
E62D
E62E
E62F
E630
H.S.
E630
F.S.
E631
H.S.
E631
F.S
E632
H.S.
E632
F.S
E633
H.S.
E633
F.S
E634
H.S.
E634
F.S
E635
H.S.
E635
F.S
E636
H.S.
E636
F.S
E637
H.S.
E637
F.S
Size
1
1
1
1
1
1
Name
ECC1B1
ECC1B2
ECC2B0
ECC2B1
ECC2B2
EP2FIFOPFH[17]
1
EP2FIFOPFH[17]
1
EP2FIFOPFL[17]
1
EP2FIFOPFL
[17]
1
EP4FIFOPFH[17]
1
EP4FIFOPFH
[17]
1
EP4FIFOPFL[17]
1
EP4FIFOPFL[17]
1
EP6FIFOPFH
[17]
1
EP6FIFOPFH[17]
1
EP6FIFOPFL[17]
1
EP6FIFOPFL[17]
1
EP8FIFOPFH
[17]
1
EP8FIFOPFH[17]
1
EP8FIFOPFL[17]
1
EP8FIFOPFL[17]
8
E640 1
reserved
EP2ISOINPKTS
E641 1
EP4ISOINPKTS
E642 1
EP6ISOINPKTS
E643 1
EP8ISOINPKTS
E644 4
E648 1
E649 7
E650 1
reserved
INPKTEND[17]
OUTPKTEND[17]
INTERRUPTS
EP2FIFOIE[17]
E651 1
EP2FIFOIRQ[17,18]
E652 1
EP4FIFOIE[17]
E653 1
[17,18]
EP4FIFOIRQ
[17]
E654 1
EP6FIFOIE
E655 1
EP6FIFOIRQ[17,18]
E656 1
EP8FIFOIE[17]
[17,18]
E657 1
EP8FIFOIRQ
E658 1
IBNIE
E659 1
IBNIRQ[18]
E65A 1
NAKIE
E65B 1
NAKIRQ[18]
E65C 1
USBIE
Description
ECC1 Byte 1 Address
ECC1 Byte 2 Address
ECC2 Byte 0 Address
ECC2 Byte 1 Address
ECC2 Byte 2 Address
Endpoint 2 / slave FIFO
Programmable Flag H
Endpoint 2 / slave FIFO
Programmable Flag H
Endpoint 2 / slave FIFO
Programmable Flag L
Endpoint 2 / slave FIFO
Programmable Flag L
Endpoint 4 / slave FIFO
Programmable Flag H
Endpoint 4 / slave FIFO
Programmable Flag H
Endpoint 4 / slave FIFO
Programmable Flag L
Endpoint 4 / slave FIFO
Programmable Flag L
Endpoint 6 / slave FIFO
Programmable Flag H
Endpoint 6 / slave FIFO
Programmable Flag H
Endpoint 6 / slave FIFO
Programmable Flag L
Endpoint 6 / slave FIFO
Programmable Flag L
Endpoint 8 / slave FIFO
Programmable Flag H
Endpoint 8 / slave FIFO
Programmable Flag H
Endpoint 8 / slave FIFO
Programmable Flag L
Endpoint 8 / slave FIFO
Programmable Flag L
b7
LINE7
COL5
LINE15
LINE7
COL5
DECIS
b6
LINE6
COL4
LINE14
LINE6
COL4
PKTSTAT
b4
LINE4
COL2
LINE12
LINE4
COL2
IN:PKTS[1]
OUT:PFC11
OUT:PFC11
b3
LINE3
COL1
LINE11
LINE3
COL1
IN:PKTS[0]
OUT:PFC10
OUT:PFC10
b2
LINE2
COL0
LINE10
LINE2
COL0
0
b1
LINE1
LINE17
LINE9
LINE1
0
PFC9
b0
LINE0
LINE16
LINE8
LINE0
0
PFC8
Default
00000000
00000000
00000000
00000000
00000000
10001000
PKTSTAT
b5
LINE5
COL3
LINE13
LINE5
COL3
IN:PKTS[2]
OUT:PFC12
OUT:PFC12
DECIS
Access
R
R
R
R
R
bbbbbrbb
0
PFC9
10001000 bbbbbrbb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
IN:PKTS[2]
OUT:PFC8
PFC0
IN:PKTS[1]
OUT:PFC7
DECIS
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
0
0
PFC8
10001000 bbrbbrrb
DECIS
PKTSTAT
0
IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC10 OUT:PFC9
OUT:PFC10 OUT:PFC9 0
0
PFC8
10001000 bbrbbrrb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
IN: PKTS[1]
OUT:PFC7
DECIS
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
IN:PKTS[1] IN:PKTS[0] 0
OUT:PFC11 OUT:PFC10
OUT:PFC11 OUT:PFC10 0
PFC9
PFC8
00001000 bbbbbrbb
DECIS
IN: PKTS[0] PFC5
OUT:PFC6
PKTSTAT
IN:PKTS[2]
OUT:PFC12
PKTSTAT
OUT:PFC12
PFC9
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
IN:PKTS[2]
OUT:PFC8
PFC0
00001000 bbbbbrbb
PFC7
IN:PKTS[1]
OUT:PFC7
DECIS
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
0
PFC8
00001000 bbrbbrrb
PKTSTAT
0
IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC10 OUT:PFC9
OUT:PFC10 OUT:PFC9 0
0
DECIS
0
PFC8
00001000 bbrbbrrb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
IN: PKTS[1]
OUT:PFC7
IN: PKTS[0] PFC5
OUT:PFC6
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
EP2 (if ISO) IN Packets per
frame (1-3)
EP4 (if ISO) IN Packets per
frame (1-3)
EP6 (if ISO) IN Packets per
frame (1-3)
EP8 (if ISO) IN Packets per
frame (1-3)
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001 brrrrrbb
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001 brrrrrrr
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001 brrrrrbb
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001 brrrrrrr
Force IN Packet End
Force OUT Packet End
Skip
Skip
0
0
0
0
0
0
EP3
EP3
EP2
EP2
EP1
EP1
EP0
EP0
xxxxxxxx W
xxxxxxxx W
Endpoint 2 slave FIFO Flag
Interrupt Enable
Endpoint 2 slave FIFO Flag
Interrupt Request
Endpoint 4 slave FIFO Flag
Interrupt Enable
Endpoint 4 slave FIFO Flag
Interrupt Request
Endpoint 6 slave FIFO Flag
Interrupt Enable
Endpoint 6 slave FIFO Flag
Interrupt Request
Endpoint 8 slave FIFO Flag
Interrupt Enable
Endpoint 8 slave FIFO Flag
Interrupt Request
IN-BULK-NAK Interrupt
Enable
IN-BULK-NAK interrupt
Request
Endpoint Ping-NAK / IBN
Interrupt Enable
Endpoint Ping-NAK / IBN
Interrupt Request
USB Int Enables
0
0
0
0
EDGEPF
PF
EF
FF
00000000 RW
0
0
0
0
0
PF
EF
FF
00000000 rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000 RW
0
0
0
0
0
PF
EF
FF
00000000 rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000 RW
0
0
0
0
0
PF
EF
FF
00000000 rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000 RW
0
0
0
0
0
PF
EF
FF
00000000 rrrrrbbb
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00000000 RW
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00xxxxxx rrbbbbbb
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
00000000 RW
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
xxxxxx0x bbbbbbrb
0
EP0ACK
HSGRANT
URES
SUSP
SUTOK
SOF
SUDAV
00000000 RW
00000000 RW
00000000 RW
Notes
17. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.
18. The register can only be reset; it cannot be set.
Document Number: 38-08032 Rev. AD
Page 35 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size
Name
E65D 1
USBIRQ[19]
E65E 1
EPIE
E65F 1
EPIRQ[19]
E660 1
E661 1
E662 1
GPIFIE[20]
GPIFIRQ[20]
USBERRIE
E663 1
USBERRIRQ[19]
E664 1
E665 1
E666 1
ERRCNTLIM
CLRERRCNT
INT2IVEC
E667 1
INT4IVEC
E668 1
E669 7
E670 1
INTSET-UP
reserved
INPUT / OUTPUT
PORTACFG
E671 1
PORTCCFG
E672 1
PORTECFG
E673 4
E677 1
E678 1
reserved
reserved
I2CS
E679 1
I2DAT
E67A 1
I2CTL
E67B 1
XAUTODAT1
E67C 1
XAUTODAT2
E680
E681
E682
E683
E684
E685
E686
E687
E688
1
1
1
1
1
1
1
1
2
UDMA CRC
UDMACRCH[20]
UDMACRCL[20]
UDMACRCQUALIFIER
USB CONTROL
USBCS
SUSPEND
WAKEUPCS
TOGCTL
USBFRAMEH
USBFRAMEL
MICROFRAME
FNADDR
reserved
E68A
E68B
E68C
E68D
1
1
1
1
ENDPOINTS
EP0BCH[20]
EP0BCL[20]
reserved
EP1OUTBC
E68E
E68F
E690
E691
E692
E694
E695
E696
E698
E699
1
1
1
1
2
1
1
2
1
1
reserved
EP1INBC
EP2BCH[20]
EP2BCL[20]
reserved
EP4BCH[20]
EP4BCL[20]
reserved
EP6BCH[20]
EP6BCL[20]
E67D 1
E67E 1
E67F 1
Description
b7
USB Interrupt Requests 0
Endpoint Interrupt
EP8
Enables
Endpoint Interrupt
EP8
Requests
GPIF Interrupt Enable
0
GPIF Interrupt Request
0
USB Error Interrupt
ISOEP8
Enables
USB Error Interrupt
ISOEP8
Requests
USB Error counter and limit EC3
Clear Error Counter EC3:0 x
Interrupt 2 (USB)
0
Autovector
Interrupt 4 (slave FIFO & 1
GPIF) Autovector
Interrupt 2&4 setup
0
b6
EP0ACK
EP6
b5
HSGRANT
EP4
b4
URES
EP2
b3
SUSP
EP1OUT
b2
SUTOK
EP1IN
b1
SOF
EP0OUT
b0
SUDAV
EP0IN
Default Access
0xxxxxxx rbbbbbbb
00000000 RW
EP6
EP4
EP2
EP1OUT
EP1IN
EP0OUT
EP0IN
0
0
0
ISOEP6
0
0
ISOEP4
0
0
ISOEP2
0
0
0
0
0
0
GPIFWF
GPIFWF
0
GPIFDONE
GPIFDONE
ERRLIMIT
00000000 RW
000000xx RW
00000000 RW
ISOEP6
ISOEP4
ISOEP2
0
0
0
ERRLIMIT
0000000x bbbbrrrb
EC2
x
I2V4
EC1
x
I2V3
EC0
x
I2V2
LIMIT3
x
I2V1
LIMIT2
x
I2V0
LIMIT1
x
0
LIMIT0
x
0
xxxx0100 rrrrbbbb
xxxxxxxx W
00000000 R
0
I4V3
I4V2
I4V1
I4V0
0
0
10000000 R
0
0
0
AV2EN
0
INT4SRC
AV4EN
00000000 RW
I/O PORTA Alternate
Configuration
I/O PORTC Alternate
Configuration
I/O PORTE Alternate
Configuration
FLAGD
SLCS
0
0
0
0
INT1
INT0
00000000 RW
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
GPIFA0
00000000 RW
GPIFA8
T2EX
INT6
RXD1OUT
RXD0OUT
T2OUT
T1OUT
T0OUT
00000000 RW
I²C Bus
Control & Status
I²C Bus
Data
I²C Bus
Control
Autoptr1 MOVX access,
when APTREN=1
Autoptr2 MOVX access,
when APTREN=1
START
STOP
LASTRD
ID1
ID0
BERR
ACK
DONE
000xx000 bbbrrrrr
d7
d6
d5
d4
d3
d2
d1
d0
xxxxxxxx RW
0
0
0
0
0
0
STOPIE
400KHZ
00000000 RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
UDMA CRC MSB
UDMA CRC LSB
UDMA CRC Qualifier
CRC15
CRC7
QENABLE
CRC14
CRC6
0
CRC13
CRC5
0
CRC12
CRC4
0
CRC11
CRC3
QSTATE
CRC10
CRC2
QSIGNAL2
CRC9
CRC1
QSIGNAL1
CRC8
CRC0
QSIGNAL0
01001010 RW
10111010 RW
00000000 brrrbbbb
USB Control & Status
Put chip into suspend
Wakeup Control & Status
Toggle Control
USB Frame count H
USB Frame count L
Microframe count, 0-7
USB Function address
HSM
x
WU2
Q
0
FC7
0
0
0
x
WU
S
0
FC6
0
FA6
0
x
WU2POL
R
0
FC5
0
FA5
0
x
WUPOL
I/O
0
FC4
0
FA4
DISCON
x
0
EP3
0
FC3
0
FA3
NOSYNSOF
x
DPEN
EP2
FC10
FC2
MF2
FA2
RENUM
x
WU2EN
EP1
FC9
FC1
MF1
FA1
SIGRSUME
x
WUEN
EP0
FC8
FC0
MF0
FA0
x0000000
xxxxxxxx
xx000101
x0000000
00000xxx
xxxxxxxx
00000xxx
0xxxxxxx
Endpoint 0 Byte Count H
Endpoint 0 Byte Count L
(BC15)
(BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx RW
xxxxxxxx RW
Endpoint 1 OUT Byte
Count
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0xxxxxxx RW
Endpoint 1 IN Byte Count 0
Endpoint 2 Byte Count H 0
Endpoint 2 Byte Count L BC7/SKIP
BC6
0
BC6
BC5
0
BC5
BC4
0
BC4
BC3
0
BC3
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
0xxxxxxx RW
00000xxx RW
xxxxxxxx RW
Endpoint 4 Byte Count H
Endpoint 4 Byte Count L
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx RW
xxxxxxxx RW
Endpoint 6 Byte Count H
Endpoint 6 Byte Count L
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
BC10
BC2
BC9
BC1
BC8
BC0
00000xxx RW
xxxxxxxx RW
RW
rrrrbbbb
W
bbbbrbbb
rrrbbbbb
R
R
R
R
Notes
19. The register can only be reset; it cannot be set.
20. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.
Document Number: 38-08032 Rev. AD
Page 36 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex
E69A
E69C
E69D
E69E
E6A0
Size
2
1
1
2
1
Name
reserved
EP8BCH[21]
EP8BCL[21]
reserved
EP0CS
E6A1 1
EP1OUTCS
E6A2 1
EP1INCS
E6A3 1
EP2CS
E6A4 1
EP4CS
E6A5 1
EP6CS
E6A6 1
EP8CS
E6A7 1
EP2FIFOFLGS
E6A8 1
EP4FIFOFLGS
E6A9 1
EP6FIFOFLGS
E6AA 1
EP8FIFOFLGS
E6AB 1
EP2FIFOBCH
E6AC 1
EP2FIFOBCL
E6AD 1
EP4FIFOBCH
E6AE 1
EP4FIFOBCL
E6AF 1
EP6FIFOBCH
E6B0 1
EP6FIFOBCL
E6B1 1
EP8FIFOBCH
E6B2 1
EP8FIFOBCL
E6B3 1
SUDPTRH
E6B4 1
SUDPTRL
E6B5 1
SUDPTRCTL
2
E6B8 8
reserved
SET-UPDAT
E6C0 1
E6C1 1
GPIF
GPIFWFSELECT
GPIFIDLECS
E6C2
E6C3
E6C4
E6C5
1
1
1
1
E6C6 1
GPIFIDLECTL
GPIFCTLCFG
GPIFADRH[21]
GPIFADRL[21]
FLOWSTATE
FLOWSTATE
E6C7 1
E6C8 1
FLOWLOGIC
FLOWEQ0CTL
Description
Endpoint 8 Byte Count H
Endpoint 8 Byte Count L
b7
0
BC7/SKIP
b6
b5
b4
b3
b2
b1
b0
Default
Access
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx RW
xxxxxxxx RW
Endpoint 0 Control and Sta- HSNAK
tus
Endpoint 1 OUT Control 0
and Status
Endpoint 1 IN Control and 0
Status
Endpoint 2 Control and Sta- 0
tus
Endpoint 4 Control and Sta- 0
tus
Endpoint 6 Control and Sta- 0
tus
Endpoint 8 Control and Sta- 0
tus
Endpoint 2 slave FIFO
0
Flags
Endpoint 4 slave FIFO
0
Flags
Endpoint 6 slave FIFO
0
Flags
Endpoint 8 slave FIFO
0
Flags
Endpoint 2 slave FIFO
0
total byte count H
Endpoint 2 slave FIFO
BC7
total byte count L
Endpoint 4 slave FIFO
0
total byte count H
Endpoint 4 slave FIFO
BC7
total byte count L
Endpoint 6 slave FIFO
0
total byte count H
Endpoint 6 slave FIFO
BC7
total byte count L
Endpoint 8 slave FIFO
0
total byte count H
Endpoint 8 slave FIFO
BC7
total byte count L
Setup Data Pointer high A15
address byte
Setup Data Pointer low ad- A7
dress byte
Setup Data Pointer Auto 0
Mode
0
0
0
0
0
BUSY
STALL
10000000 bbbbbbrb
0
0
0
0
0
BUSY
STALL
00000000 bbbbbbrb
0
0
0
0
0
BUSY
STALL
00000000 bbbbbbrb
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000 rrrrrrrb
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000 rrrrrrrb
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100 rrrrrrrb
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100 rrrrrrrb
0
0
0
0
PF
EF
FF
00000010 R
0
0
0
0
PF
EF
FF
00000010 R
0
0
0
0
PF
EF
FF
00000110 R
0
0
0
0
PF
EF
FF
00000110 R
0
0
BC12
BC11
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
0
0
0
0
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
0
0
0
BC11
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
0
0
0
0
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
A14
A13
A12
A11
A10
A9
A8
xxxxxxxx RW
A6
A5
A4
A3
A2
A1
0
xxxxxxx0 bbbbbbbr
0
0
0
0
0
0
SDPAUTO
00000001 RW
8 bytes of setup data
D7
SET-UPDAT[0] =
bmRequestType
SET-UPDAT[1] =
bmRequest
SET-UPDAT[2:3] = wValue
SET-UPDAT[4:5] = wIndex
SET-UPDAT[6:7] =
wLength
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx R
Waveform Selector
GPIF Done, GPIF IDLE
drive mode
Inactive Bus, CTL states
CTL Drive Type
GPIF Address H
GPIF Address L
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1
DONE
0
0
0
0
FIFOWR0
0
FIFORD1
0
FIFORD0
IDLEDRV
11100100 RW
10000000 RW
0
TRICTL
0
GPIFA7
0
0
0
GPIFA6
CTL5
CTL5
0
GPIFA5
CTL4
CTL4
0
GPIFA4
CTL3
CTL3
0
GPIFA3
CTL2
CTL2
0
GPIFA2
CTL1
CTL1
0
GPIFA1
CTL0
CTL0
GPIFA8
GPIFA0
11111111
00000000
00000000
00000000
Flowstate Enable and
Selector
Flowstate Logic
CTL-Pin States in
Flowstate
(when Logic = 0)
FSE
0
0
0
0
FS2
FS1
FS0
00000000 brrrrbbb
LFUNC1
CTL0E3
LFUNC0
CTL0E2
TERMA2
CTL0E1/
CTL5
TERMA1
CTL0E0/
CTL4
TERMA0
CTL3
TERMB2
CTL2
TERMB1
CTL1
TERMB0
CTL0
00000000 RW
00000000 RW
RW
RW
RW
RW
Note
21. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.
Document Number: 38-08032 Rev. AD
Page 37 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size
Name
E6C9 1
FLOWEQ1CTL
E6CA 1
E6CB 1
FLOWHOLDOFF
FLOWSTB
E6CC 1
FLOWSTBEDGE
E6CD 1
E6CE 1
FLOWSTBPERIOD
GPIFTCB3[22]
E6CF 1
GPIFTCB2[22]
E6D0 1
GPIFTCB1[22]
E6D1 1
GPIFTCB0[22]
2
E6D2 1
E6D3 1
E6D4 1
3
E6DA 1
E6DB 1
E6DC 1
3
E6E2 1
E6E3 1
E6E4 1
3
E6EA 1
E6EB 1
E6EC 1
3
E6F0 1
E6F1 1
E6F2 1
E6F3 1
E6F4 1
E6F5 1
E6F6 2
E740
E780
E7C0
E800
F000
64
64
64
2048
1024
F400 512
F600 512
Description
CTL-Pin States in Flowstate (when Logic = 1)
Holdoff Configuration
Flowstate Strobe
Configuration
Flowstate Rising/Falling
Edge Configuration
Master-Strobe Half-Period
GPIF Transaction Count
Byte 3
GPIF Transaction Count
Byte 2
GPIF Transaction Count
Byte 1
GPIF Transaction Count
Byte 0
reserved
reserved
reserved
EP2GPIFFLGSEL[22] Endpoint 2 GPIF Flag
select
EP2GPIFPFSTOP
Endpoint 2 GPIF stop
transaction on prog. flag
[22]
EP2GPIFTRIG
Endpoint 2 GPIF Trigger
reserved
reserved
reserved
EP4GPIFFLGSEL[22] Endpoint 4 GPIF Flag
select
EP4GPIFPFSTOP
Endpoint 4 GPIF stop
transaction on GPIF Flag
[22]
EP4GPIFTRIG
Endpoint 4 GPIF Trigger
reserved
reserved
reserved
EP6GPIFFLGSEL[22] Endpoint 6 GPIF Flag
select
EP6GPIFPFSTOP
Endpoint 6 GPIF stop
transaction on prog. flag
[22]
EP6GPIFTRIG
Endpoint 6 GPIF Trigger
reserved
reserved
reserved
EP8GPIFFLGSEL[22] Endpoint 8 GPIF Flag
select
EP8GPIFPFSTOP
Endpoint 8 GPIF stop
transaction on prog. flag
[22]
EP8GPIFTRIG
Endpoint 8 GPIF Trigger
reserved
XGPIFSGLDATH
GPIF Data H
(16-bit mode only)
XGPIFSGLDATLX
Read/Write GPIF Data L &
trigger transaction
XGPIFSGLDATLNOX Read GPIF Data L, no
transaction trigger
GPIFREADYCFG
Internal RDY, Sync/Async,
RDY pin states
GPIFREADYSTAT
GPIF Ready Status
GPIFABORT
Abort GPIF Waveforms
reserved
ENDPOINT BUFFERS
EP0BUF
EP0-IN/-OUT buffer
EP10UTBUF
EP1-OUT buffer
EP1INBUF
EP1-IN buffer
reserved
EP2FIFOBUF
512/1024 byte EP 2 / slave
FIFO buffer (IN or OUT)
EP4FIFOBUF
512 byte EP 4 / slave FIFO
buffer (IN or OUT)
reserved
b7
CTL0E3
b6
CTL0E2
b5
CTL0E1/
CTL5
HOPERIOD3 HOPERIOD2 HOPERIOD1
SLAVE
RDYASYNC CTLTOGL
b4
b3
CTL0E0/
CTL3
CTL4
HOPERIOD0 HOSTATE
SUSTAIN
0
b2
CTL2
b1
CTL1
CTL0
b0
Default Access
00000000 RW
HOCTL2
MSTB2
HOCTL1
MSTB1
HOCTL0
MSTB0
00010010 RW
00100000 RW
0
0
0
0
0
0
FALLING
RISING
00000001 rrrrrrbb
D7
TC31
D6
TC30
D5
TC29
D4
TC28
D3
TC27
D2
TC26
D1
TC25
D0
TC24
00000010 RW
00000000 RW
TC23
TC22
TC21
TC20
TC19
TC18
TC17
TC16
00000000 RW
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
00000000 RW
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
00000001 RW
00000000 RW
0
0
0
0
0
0
FS1
FS0
00000000 RW
0
0
0
0
0
0
0
FIFO2FLAG 00000000 RW
x
x
x
x
x
x
x
x
xxxxxxxx W
0
0
0
0
0
0
FS1
FS0
00000000 RW
0
0
0
0
0
0
0
FIFO4FLAG 00000000 RW
x
x
x
x
x
x
x
x
xxxxxxxx W
0
0
0
0
0
0
FS1
FS0
00000000 RW
0
0
0
0
0
0
0
FIFO6FLAG 00000000 RW
x
x
x
x
x
x
x
x
xxxxxxxx W
0
0
0
0
0
0
FS1
FS0
00000000 RW
0
0
0
0
0
0
0
FIFO8FLAG 00000000 RW
x
x
x
x
x
x
x
x
xxxxxxxx W
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx R
INTRDY
SAS
TCXRDY5
0
0
0
0
0
00000000 bbbrrrrr
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx R
xxxxxxxx W
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
xxxxxxxx RW
xxxxxxxx RW
RW
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
Note
22. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.
Document Number: 38-08032 Rev. AD
Page 38 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size
Name
F800 1024 EP6FIFOBUF
FC00 512 EP8FIFOBUF
Description
512/1024 byte EP 6 / slave D7
FIFO buffer (IN or OUT)
512 byte EP 8 / slave FIFO D7
buffer (IN or OUT)
FE00 512 reserved
xxxx
I²C Configuration Byte
80
81
82
83
84
85
86
87
88
1
1
1
1
1
1
1
1
1
89
1
8A
8B
8C
8D
8E
8F
90
91
92
1
1
1
1
1
1
1
1
1
93
98
5
1
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A8
1
1
1
1
1
1
1
1
1
1
5
1
A9
AA
1
1
AB
1
AC
1
AD
AF
B0
B1
2
1
1
1
B2
B3
B4
B5
B6
B7
B8
1
1
1
1
1
1
1
B9
1
Special Function Registers (SFRs)
IOA[24]
Port A (bit addressable)
SP
Stack Pointer
DPL0
Data Pointer 0 L
DPH0
Data Pointer 0 H
[24]
DPL1
Data Pointer 1 L
[24]
DPH1
Data Pointer 1 H
DPS[24]
Data Pointer 0/1 select
PCON
Power Control
TCON
Timer/Counter Control
(bit addressable)
TMOD
Timer/Counter Mode
Control
TL0
Timer 0 reload L
TL1
Timer 1 reload L
TH0
Timer 0 reload H
TH1
Timer 1 reload H
CKCON[24]
Clock Control
reserved
[24]
IOB
Port B (bit addressable)
EXIF[24]
External Interrupt Flag(s)
MPAGE[24]
Upper Addr Byte of MOVX
using @R0 / @R1
reserved
SCON0
Serial Port 0 Control
(bit addressable)
SBUF0
Serial Port 0 Data Buffer
[24]
AUTOPTRH1
Autopointer 1 Address H
AUTOPTRL1[24]
Autopointer 1 Address L
reserved
AUTOPTRH2[24]
Autopointer 2 Address H
AUTOPTRL2[24]
Autopointer 2 Address L
reserved
[24]
IOC
Port C (bit addressable)
INT2CLR[24]
Interrupt 2 clear
INT4CLR[24]
Interrupt 4 clear
reserved
IE
Interrupt Enable
(bit addressable)
reserved
EP2468STAT[24]
Endpoint 2,4,6,8 status
flags
EP24FIFOFLGS
Endpoint 2,4 slave FIFO
[24]
status flags
EP68FIFOFLGS
Endpoint 6,8 slave FIFO
[24]
status flags
reserved
AUTOPTRSETUP[24] Autopointer 1&2 setup
IOD[24]
Port D (bit addressable)
IOE[24]
Port E
(NOT bit addressable)
[24]
OEA
Port A Output Enable
[24]
OEB
Port B Output Enable
OEC[24]
Port C Output Enable
OED[24]
Port D Output Enable
OEE[24]
Port E Output Enable
reserved
IP
Interrupt Priority (bit addressable)
reserved
b7
D6
b6
D5
b5
D4
b4
D3
b3
D2
b2
D1
b1
D0
b0
Default Access
xxxxxxxx RW
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
0
DISCON
0
0
0
0
0
400KHZ
xxxxxxxx n/a
D7
D7
A7
A15
A7
A15
0
SMOD0
TF1
D6
D6
A6
A14
A6
A14
0
x
TR1
D5
D5
A5
A13
A5
A13
0
1
TF0
D4
D4
A4
A12
A4
A12
0
1
TR0
D3
D3
A3
A11
A3
A11
0
x
IE1
D2
D2
A2
A10
A2
A10
0
x
IT1
D1
D1
A1
A9
A1
A9
0
x
IE0
D0
D0
A0
A8
A0
A8
SEL
IDLE
IT0
xxxxxxxx
00000111
00000000
00000000
00000000
00000000
00000000
00110000
00000000
GATE
CT
M1
M0
GATE
CT
M1
M0
00000000 RW
D7
D7
D15
D15
x
D6
D6
D14
D14
x
D5
D5
D13
D13
T2M
D4
D4
D12
D12
T1M
D3
D3
D11
D11
T0M
D2
D2
D10
D10
MD2
D1
D1
D9
D9
MD1
D0
D0
D8
D8
MD0
00000000
00000000
00000000
00000000
00000001
D7
IE5
A15
D6
IE4
A14
D5
I²CINT
A13
D4
USBNT
A12
D3
1
A11
D2
0
A10
D1
0
A9
D0
0
A8
xxxxxxxx RW
00001000 RW
00000000 RW
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00000000 RW
D7
A15
A7
D6
A14
A6
D5
A13
A5
D4
A12
A4
D3
A11
A3
D2
A10
A2
D1
A9
A1
D0
A8
A0
00000000 RW
00000000 RW
00000000 RW
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
00000000 RW
00000000 RW
D7
x
x
D6
x
x
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
xxxxxxxx RW
xxxxxxxx W
xxxxxxxx W
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000 RW
EP8F
EP8E
EP6F
EP6E
EP4F
EP4E
EP2F
EP2E
01011010 R
0
EP4PF
EP4EF
EP4FF
0
EP2PF
EP2EF
EP2FF
00100010 R
0
EP8PF
EP8EF
EP8FF
0
EP6PF
EP6EF
EP6FF
01100110 R
0
D7
D7
0
D6
D6
0
D5
D5
0
D4
D4
0
D3
D3
APTR2INC
D2
D2
APTR1INC
D1
D1
APTREN
D0
D0
00000110 RW
xxxxxxxx RW
xxxxxxxx RW
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
00000000
00000000
00000000
00000000
00000000
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
10000000 RW
[23]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Notes
23. If no EEPROM is detected by the SIE then the default is 00000000.
24. SFRs not part of the standard 8051 architecture.
Document Number: 38-08032 Rev. AD
Page 39 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size
Name
BA
1
EP01STAT[25]
BB
1
GPIFTRIG[25, 26]
BC
BD
1
1
reserved
GPIFSGLDATH[25]
BE
BF
1
1
C0
1
GPIFSGLDATLX[25]
GPIFSGLDATLNOX[25]
SCON1[25]
C1
C2
C8
1
6
1
SBUF1[25]
C9
CA
1
1
reserved
RCAP2L
CB
1
RCAP2H
CC
CD
CE
D0
1
1
2
1
TL2
TH2
reserved
PSW
D1
D8
D9
E0
7
1
7
1
reserved
EICON[25]
reserved
ACC
E1
E8
7
1
reserved
EIE[25]
E9
F0
F1
F8
7
1
7
1
reserved
B
reserved
EIP[25]
F9
7
reserved
reserved
T2CON
Description
Endpoint 0&1 Status
Endpoint 2,4,6,8 GPIF
slave FIFO Trigger
b7
0
DONE
0
0
0
0
0
0
0
0
b2
EP1INBSY
RW
b1
b0
EP1OUTBSY EP0BSY
EP1
EP0
Default Access
00000000 R
10000xxx brrrrbbb
GPIF Data H (16-bit mode D15
only)
GPIF Data L w/ Trigger
D7
GPIF Data L w/ No Trigger D7
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx RW
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx RW
xxxxxxxx R
Serial Port 1 Control (bit
addressable)
Serial Port 1 Data Buffer
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00000000 RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
Timer/Counter 2 Control
(bit addressable)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000 RW
Capture for Timer 2, auto-reload, up-counter
Capture for Timer 2, auto-reload, up-counter
Timer 2 reload L
Timer 2 reload H
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
D7
D15
D6
D14
D5
D13
D4
D12
D3
D11
D2
D10
D1
D9
D0
D8
00000000 RW
00000000 RW
Program Status Word (bit CY
addressable)
AC
F0
RS1
RS0
OV
F1
P
00000000 RW
External Interrupt Control SMOD1
1
ERESI
RESI
INT6
0
0
0
01000000 RW
Accumulator (bit address- D7
able)
D6
D5
D4
D3
D2
D1
D0
00000000 RW
External Interrupt Enable(s)
1
1
1
EX6
EX5
EX4
EI²C
EUSB
11100000 RW
B (bit addressable)
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
1
1
PX6
PX5
PX4
PI²C
PUSB
11100000 RW
External Interrupt Priority 1
Control
b6
b5
b4
b3
R = all bits read-only
W = all bits write-only
r = read-only bit
w = write-only bit
b = both read/write bit
Notes
25. SFRs not part of the standard 8051 architecture.
26. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.
Document Number: 38-08032 Rev. AD
Page 40 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Absolute Maximum Ratings
Operating Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
TA (ambient temperature under bias)
Commercial ................................................... 0 °C to +70 °C
Storage temperature ................................ –65 °C to +150 °C
TA (ambient temperature under bias)
Industrial .................................................. –40 °C to +105 °C
Ambient temperature with
power supplied (Commercial)......................... 0 °C to +70 °C
Ambient temperature with
power supplied (Industrial) ...................... –40 °C to +105 °C
Supply voltage to ground potential ..............–0.5 V to +4.0 V
Supply voltage .........................................+3.00 V to +3.60 V
Ground voltage ................................................................ 0 V
FOSC (oscillator or crystal frequency) .... 24 MHz ± 100 ppm,
parallel resonant
DC input voltage to any input pin[27] ........................... 5.25 V
DC voltage applied to outputs
in high Z state .................................... –0.5 V to VCC + 0.5 V
Power dissipation .................................................... 300 mW
Static discharge voltage .......................................... >2000 V
Max output current, per I/O port ................................. 10 mA
Max output current, all five I/O ports
(128-pin and 100-pin packages) ................................. 50 mA
Thermal Characteristics
Maximum junction temperature ................................. 125 °C
The following table displays the thermal characteristics of various packages:
Table 13. Thermal Characteristics
Package
Ambient Temperature (°C)
Jc
Junction to Case
Thermal Resistance (°C/W)
Ja
Junction to Ambient Thermal
Resistance (°C/W)
70
24.4
47.7
56 SSOP
100 TQFP
70
11.9
45.9
128 TQFP
70
15.5
43.2
56 QFN
70
10.6
25.2
56 VFBGA
70
30.9
58.6
The junction temperature j, can be calculated using the following equation: j = P*Ja + a
Where,
P = Power
Ja = Junction to ambient temperature (Jc + Ca)
a = Ambient temperature (70 °C)
The case temperature c, can be calculated using the following equation: c = P*Ca + a
where,
P = Power
Ca = Case to ambient temperature
a = Ambient temperature (70 °C)
Note
27. Do not power I/O with the chip power OFF.
Document Number: 38-08032 Rev. AD
Page 41 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
DC Electrical Characteristics
Table 14. DC Characteristics
Parameter
Min
Typ
Max
Unit
–
3.00
3.3
3.60
V
VCC Ramp Up 0 to 3.3 V
–
200
–
–
s
VIH
Input HIGH voltage
–
2
–
5.25
V
VIL
Input LOW voltage
–
–0.5
–
0.8
V
VIH_X
Crystal input HIGH voltage
–
2
–
5.25
V
VIL_X
Crystal input LOW voltage
–
–0.5
–
0.8
V
II
Input leakage current
0< VIN < VCC
–
–
±10
A
VOH
Output voltage HIGH
IOUT = 4 mA
2.4
–
–
V
VOL
Output LOW voltage
IOUT = –4 mA
–
–
0.4
V
VCC
Description
Supply voltage
Conditions
IOH
Output current HIGH
–
–
–
4
mA
IOL
Output current LOW
–
–
–
4
mA
CIN
Input pin capacitance
ISUSP
ICC
TRESET
Except D+/D–
–
–
10
pF
D+/D–
–
–
15
pF
Suspend current
Connected
–
300
380[28]
A
CY7C68014/CY7C68016
Disconnected
–
100
150[28]
A
mA
mA
Suspend current
Connected
–
0.5
1.2[28]
CY7C68013/CY7C68015
Disconnected
–
0.3
1.0[28]
Supply current
Reset time after valid power
Pin reset after powered on
8051 running, connected to USB HS
–
50
85
mA
8051 running, connected to USB FS
–
35
65
mA
VCC min = 3.0 V
5.0
–
–
ms
200
–
–
s
USB Transceiver
USB 2.0 compliant in Full Speed and Hi-Speed modes.
Note
28. Measured at Max VCC, 25 °C.
Document Number: 38-08032 Rev. AD
Page 42 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
AC Electrical Characteristics
USB Transceiver
USB 2.0 compliant in Full-Speed and Hi-Speed modes.
Program Memory Read
Figure 12. Program Memory Read Timing Diagram
tCL
CLKOUT[29]
tAV
tAV
A[15..0]
tSTBH
tSTBL
PSEN#
tDH
[30]
tACC1
D[7..0]
data in
tSOEL
OE#
tSCSL
CS#
Table 15. Program Memory Read Parameters
Parameter
Description
Min
Typ
Max
Unit
Notes
–
20.83
–
ns
48 MHz
–
41.66
–
ns
24 MHz
tCL
1/CLKOUT frequency
–
83.2
–
ns
12 MHz
tAV
Delay from clock to valid address
0
–
10.7
ns
–
tSTBL
Clock to PSEN LOW
0
–
8
ns
–
tSTBH
Clock to PSEN HIGH
0
–
8
ns
–
tSOEL
Clock to OE LOW
–
–
11.1
ns
–
tSCSL
Clock to CS LOW
–
–
13
ns
–
tDSU
Data setup to clock
9.6
–
–
ns
–
tDH
Data hold time
0
–
–
ns
–
Notes
29. CLKOUT is shown with positive polarity.
30. tACC1 is computed from these parameters as follows:
tACC1(24 MHz) = 3*tCL – tAV – tDSU = 106 ns.
tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns.
Document Number: 38-08032 Rev. AD
Page 43 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Data Memory Read[31]
Figure 13. Data Memory Read Timing Diagram
tCL
Stretch = 0
CLKOUT[29]
tAV
tAV
A[15..0]
tSTBH
tSTBL
RD#
tSCSL
CS#
tSOEL
OE#
[32]
tDSU
tDH
tACC2
D[7..0]
data in
Stretch = 1
tCL
CLKOUT[29]
tAV
A[15..0]
RD#
CS#
tDSU
tACC3 [32]
D[7..0]
tDH
data in
Table 16. Data Memory Read Parameters
Parameter
tCL
Description
1/CLKOUT frequency
Min
Typ
Max
Unit
Notes
–
20.83
–
ns
48 MHz
–
41.66
–
ns
24 MHz
–
83.2
–
ns
12 MHz
tAV
Delay from clock to valid address
–
–
10.7
ns
–
tSTBL
Clock to RD LOW
–
–
11
ns
–
tSTBH
Clock to RD HIGH
–
–
11
ns
–
tSCSL
Clock to CS LOW
–
–
13
ns
–
tSOEL
Clock to OE LOW
–
–
11.1
ns
–
tDSU
Data setup to clock
9.6
–
–
ns
–
tDH
Data hold time
0
–
–
ns
–
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# is active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on
the stretch value.
Notes
31. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including typical
strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.
32. tACC2 and tACC3 are computed from these parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
Document Number: 38-08032 Rev. AD
Page 44 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Data Memory Write[33]
Figure 14. Data Memory Write Timing Diagram
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
WR#
tSCSL
CS#
tON1
tOFF1
data out
D[7..0]
Stretch = 1
tCL
CLKOUT
tAV
A[15..0]
WR#
CS#
tON1
tOFF1
data out
D[7..0]
Table 17. Data Memory Write Parameters
Parameter
Description
Min
Max
Unit
Notes
tAV
Delay from clock to valid address
0
10.7
ns
–
tSTBL
Clock to WR pulse LOW
0
11.2
ns
–
tSTBH
Clock to WR pulse HIGH
0
11.2
ns
–
tSCSL
Clock to CS pulse LOW
–
13.0
ns
–
tON1
Clock to data turn-on
0
13.1
ns
–
tOFF1
Clock to data hold time
0
13.1
ns
–
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on
the stretch value.
Note
33. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including
typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.
Document Number: 38-08032 Rev. AD
Page 45 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
PORTC Strobe Feature Timings
The RD# and WR# are present in the 100-pin version and the
128-pin package. In these 100-pin and 128-pin versions, an
8051 control bit can be set to pulse the RD# and WR# pins when
the 8051 reads from or writes to PORTC. This feature is enabled
by setting PORTCSTB bit in CPUCS register.
The RD# and WR# strobes are asserted for two CLKOUT cycles
when PORTC is accessed.
The WR# strobe is asserted two clock cycles after PORTC is
updated and is active for two clock cycles after that, as shown in
Figure 16.
As for read, the value of PORTC three clock cycles before the
assertion of RD# is the value that the 8051 reads in. The RD# is
pulsed for two clock cycles after three clock cycles from the point
when the 8051 has performed a read function on PORTC.
The RD# signal prompts the external logic to prepare the next
data byte. Nothing gets sampled internally on assertion of the
RD# signal itself; it is just a prefetch type signal to get the next
data byte prepared. So, using it with that in mind easily meets the
setup time to the next read.
The purpose of this pulsing of RD# is to allow the external
peripheral to know that the 8051 is done reading PORTC and the
data was latched into PORTC three CLKOUT cycles before
asserting the RD# signal. After the RD# is pulsed, the external
logic can update the data on PORTC.
Following is the timing diagram of the read and write strobing
function on accessing PORTC. Refer to Data Memory Read[31]
on page 44 and Data Memory Write[33] on page 45 for details on
propagation delay of RD# and WR# signals.
Figure 16. WR# Strobe Function when PORTC is Accessed by 8051
tCLKOUT
CLKOUT
PORTC IS UPDATED
tSTBL
tSTBH
WR#
Figure 17. RD# Strobe Function when PORTC is Accessed by 8051
tCLKOUT
CLKOUT
8051 READS PORTC
DATA CAN BE UPDATED BY EXTERNAL LOGIC
DATA MUST BE HELD FOR 3 CLK CYLCES
tSTBL
tSTBH
RD#
Document Number: 38-08032 Rev. AD
Page 46 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
GPIF Synchronous Signals
Figure 18. GPIF Synchronous Signals Timing Diagram[34]
tIFCLK
IFCLK
tSGA
GPIFADR[8:0]
RDYX
tSRY
tRYH
DATA(input)
valid
tSGD
tDAH
CTLX
tXCTL
DATA(output)
N
N+1
tXGD
Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[34, 35]
Parameter
Description
Min
Max
20.83
8.9
Typ
Unit
Min
Max
–
–
–
ns
–
–
–
ns
0
–
–
–
ns
9.2
–
–
–
ns
tIFCLK
IFCLK Period
tSRY
RDYX to clock setup time
tRYH
RDYX Hold Time
tSGD
GPIF data to clock setup time
tDAH
GPIF data hold time
0
–
–
–
ns
tSGA
Clock to GPIF address propagation delay
–
7.5
–
–
ns
tXGD
Clock to GPIF data output propagation delay
–
10
–
–
ns
tXCTL
Clock to CTLX output propagation delay
–
6.7
–
–
ns
tIFCLKR
IFCLK rise time
–
–
–
900
ps
tIFCLKF
IFCLK fall time
–
–
–
900
ps
tIFCLKOD
IFCLK output duty cycle
–
–
49
51
%
tIFCLKJ
IFCLK jitter peak to peak
–
–
–
300
ps
Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[35]
Parameter
Description
Min
Max
Unit
20.83
200
ns
RDYX to clock setup time
2.9
–
ns
RDYX Hold Time
3.7
–
ns
tSGD
GPIF data to clock setup time
3.2
–
ns
tDAH
GPIF data hold time
4.5
–
ns
tSGA
Clock to GPIF address propagation delay
–
11.5
ns
tXGD
Clock to GPIF data output propagation delay
–
15
ns
tXCTL
Clock to CTLX output propagation delay
–
10.7
ns
tIFCLK
IFCLK period[36]
tSRY
tRYH
Notes
34. Dashed lines denote signals with programmable polarity.
35. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
36. IFCLK must not exceed 48 MHz.
Document Number: 38-08032 Rev. AD
Page 47 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Slave FIFO Synchronous Read
Figure 19. Slave FIFO Synchronous Read Timing Diagram [37]
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tXFLG
FLAGS
DATA
N+1
N
tOEon
tXFD
tOEoff
SLOE
Table 20. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[38]
Parameter
Description
Min
Max
Typ
Min
Max
Unit
tIFCLK
IFCLK period
20.83
–
–
–
ns
tSRD
SLRD to clock setup time
18.7
–
–
–
ns
tRDH
Clock to SLRD hold time
0
–
–
–
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
–
–
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
–
–
ns
tXFLG
Clock to FLAGS output propagation delay
–
9.5
–
–
ns
tXFD
Clock to FIFO data output propagation delay
–
11
–
–
ns
tIFCLKR
IFCLK rise time
–
–
–
900
ps
tIFCLKF
IFCLK fall time
–
–
–
900
ps
tIFCLKOD
IFCLK output duty cycle
–
–
49
51
%
tIFCLKJ
IFCLK jitter peak to peak
–
–
–
300
ps
Table 21. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[38]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
200
ns
tSRD
SLRD to clock setup time
12.7
–
ns
tRDH
Clock to SLRD hold time
3.7
–
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
tXFLG
Clock to FLAGS output propagation delay
–
13.5
ns
tXFD
Clock to FIFO data output propagation delay
–
15
ns
Notes
37. Dashed lines denote signals with programmable polarity.
38. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
Document Number: 38-08032 Rev. AD
Page 48 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Slave FIFO Asynchronous Read
Figure 20. Slave FIFO Asynchronous Read Timing Diagram [39]
tRDpwh
SLRD
tRDpwl
FLAGS
tXFD
tXFLG
DATA
SLOE
N
N+1
tOEon
tOEoff
Table 22. Slave FIFO Asynchronous Read Parameters[40]
Min
Max
Unit
tRDpwl
Parameter
SLRD pulse width LOW
Description
50
–
ns
tRDpwh
SLRD pulse width HIGH
50
–
ns
tXFLG
SLRD to FLAGS output propagation delay
–
70
ns
tXFD
SLRD to FIFO data output propagation delay
–
15
ns
tOEon
SLOE turn-on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn-off to FIFO data hold
–
10.5
ns
Notes
39. Dashed lines denote signals with programmable polarity.
40. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document Number: 38-08032 Rev. AD
Page 49 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Slave FIFO Synchronous Write
Figure 21. Slave FIFO Synchronous Write Timing Diagram [41]
tIFCLK
IFCLK
SLWR
DATA
tSWR
tWRH
N
Z
tSFD
Z
tFDH
FLAGS
tXFLG
Table 23. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[42]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
–
ns
tSWR
SLWR to clock setup time
10.4
–
ns
tWRH
Clock to SLWR hold time
0
–
ns
tSFD
FIFO data to clock setup time
9.2
–
ns
tFDH
Clock to FIFO data hold time
0
–
ns
tXFLG
Clock to FLAGS output propagation time
–
9.5
ns
Table 24. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[42]
Min
Max
Unit
tIFCLK
Parameter
IFCLK Period
Description
20.83
200
ns
tSWR
SLWR to clock setup time
12.1
–
ns
tWRH
Clock to SLWR hold time
3.6
–
ns
tSFD
FIFO data to clock setup time
3.2
–
ns
tFDH
Clock to FIFO data hold time
4.5
–
ns
tXFLG
Clock to FLAGS output propagation time
–
13.5
ns
Notes
41. Dashed lines denote signals with programmable polarity.
42. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
Document Number: 38-08032 Rev. AD
Page 50 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Slave FIFO Asynchronous Write
Figure 22. Slave FIFO Asynchronous Write Timing Diagram [43]
tWRpwh
SLWR
SLWR/SLCS#
tWRpwl
tSFD
tFDH
DATA
tXFD
FLAGS
Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[44]
Parameter
Description
Min
Max
Unit
tWRpwl
SLWR pulse LOW
50
–
ns
tWRpwh
SLWR pulse HIGH
70
–
ns
tSFD
SLWR to FIFO DATA setup time
10
–
ns
tFDH
FIFO DATA to SLWR hold time
10
–
ns
tXFD
SLWR to FLAGS output propagation delay
–
70
ns
Notes
43. Dashed lines denote signals with programmable polarity.
44. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document Number: 38-08032 Rev. AD
Page 51 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Slave FIFO Synchronous Packet End Strobe
Figure 23. Slave FIFO Synchronous Packet End Strobe Timing Diagram [45]
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[46]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
–
ns
tSPE
PKTEND to clock setup time
14.6
–
ns
tPEH
Clock to PKTEND hold time
0
–
ns
tXFLG
Clock to FLAGS output propagation delay
–
9.5
ns
Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[46]
Parameter
Description
Min
Max
Unit
20.83
200
ns
tIFCLK
IFCLK period
tSPE
PKTEND to clock setup time
8.6
–
ns
tPEH
Clock to PKTEND hold time
2.5
–
ns
tXFLG
Clock to FLAGS output propagation delay
–
13.5
ns
Notes
45. Dashed lines denote signals with programmable polarity.
46. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
Document Number: 38-08032 Rev. AD
Page 52 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
There is no specific timing requirement that should be met for
asserting the PKTEND pin to asserting SLWR. PKTEND can be
asserted with the last data value clocked into the FIFOs or
thereafter. The setup time tSPE and the hold time tPEH must be
met.
Although there are no specific timing requirements for PKTEND
assertion, there is a specific corner-case condition that needs
attention while using the PKTEND pin to commit a one byte or
word packet. There is an additional timing requirement that
needs to be met when the FIFO is configured to operate in auto
mode and it is required to send two packets back to back: a full
packet (full defined as the number of bytes in the FIFO meeting
the level set in AUTOINLEN register) committed automatically
followed by a short one byte or word packet committed manually
using the PKTEND pin. In this scenario, the user must ensure to
assert PKTEND, at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet. Figure 24 shows this scenario. X is the value
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 24 shows a scenario where two packets are committed.
The first packet gets committed automatically when the number
of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte/word short packet being
committed manually using PKTEND.
Note that there is at least one IFCLK cycle timing between the
assertion of PKTEND and clocking of the last byte of the previous
packet (causing the packet to be committed automatically).
Failing to adhere to this timing results in the FX2 failing to send
the one byte or word short packet.
Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram[47]
tIFCLK
IFCLK
tSFA
tFAH
FIFOADR
>= tWRH
>= tSWR
SLWR
tSFD
DATA
tFDH
tSFD
X-4
X-3
tFDH
tSFD
X-2
tFDH
tSFD
X-1
tFDH
tSFD
X
tFDH
tSFD
tFDH
1
At least one IFCLK cycle
tSPE
tPEH
PKTEND
Note
47. Dashed lines denote signals with programmable polarity.
Document Number: 38-08032 Rev. AD
Page 53 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Slave FIFO Asynchronous Packet End Strobe
Figure 25. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[48]
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Table 28. Slave FIFO Asynchronous Packet End Strobe Parameters[49]
Parameter
Description
Min
Max
Unit
tPEpwl
PKTEND pulse width LOW
50
–
ns
tPWpwh
PKTEND pulse width HIGH
50
–
ns
tXFLG
PKTEND to FLAGS output propagation delay
–
115
ns
Slave FIFO Output Enable
Figure 26. Slave FIFO Output Enable Timing Diagram[48]
SLOE
tOEoff
tOEon
DATA
Table 29. Slave FIFO Output Enable Parameters
Min
Max
Unit
tOEon
Parameter
SLOE assert to FIFO DATA output
Description
–
10.5
ns
tOEoff
SLOE deassert to FIFO DATA hold
–
10.5
ns
Slave FIFO Address to Flags/Data
Figure 27. Slave FIFO Address to Flags/Data Timing Diagram[48]
FIFOADR [1.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Table 30. Slave FIFO Address to Flags/Data Parameters
Min
Max
Unit
tXFLG
Parameter
FIFOADR[1:0] to FLAGS output propagation delay
Description
–
10.7
ns
tXFD
FIFOADR[1:0] to FIFODATA output propagation delay
–
14.3
ns
Notes
48. Dashed lines denote signals with programmable polarity.
49. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document Number: 38-08032 Rev. AD
Page 54 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Slave FIFO Synchronous Address
Figure 28. Slave FIFO Synchronous Address Timing Diagram[50]
IFCLK
SLCS/FIFOADR [1:0]
tSFA
tFAH
Table 31. Slave FIFO Synchronous Address Parameters[51]
Parameter
Description
Min
Max
Unit
20.83
200
ns
FIFOADR[1:0] to clock setup time
25
–
ns
Clock to FIFOADR[1:0] hold time
10
–
ns
Min
Max
Unit
tIFCLK
Interface clock period
tSFA
tFAH
Slave FIFO Asynchronous Address
Figure 29. Slave FIFO Asynchronous Address Timing Diagram [50]
SLCS/FIFOADR [1:0]
tSFA
tFAH
SLRD/SLWR/PKTEND
Table 32. Slave FIFO Asynchronous Address Parameters[52]
Parameter
Description
tSFA
FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time
10
–
ns
tFAH
RD/WR/PKTEND to FIFOADR[1:0] hold time
10
–
ns
Notes
50. Dashed lines denote signals with programmable polarity.
51. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
52. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document Number: 38-08032 Rev. AD
Page 55 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Sequence Diagram
Single and Burst Synchronous Read Example
Figure 30. Slave FIFO Synchronous Read Sequence and Timing Diagram[53]
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSRD
T=0
tRDH
>= tSRD
>= tRDH
SLRD
t=3
t=2
T=3
T=2
SLCS
tXFLG
FLAGS
tXFD
tXFD
Data Driven: N
DATA
N+1
N+1
N+2
N+3
tOEon
tOEoff
tOEon
tXFD
tXFD
N+4
tOEoff
SLOE
t=4
T=4
T=1
t=1
Figure 31. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
FIFO POINTER
N
IFCLK
IFCLK
N
N+1
FIFO DATA BUS Not Driven
Driven: N
N+1
N+1
Not Driven
■
At t = 0, the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied LOW in some applications). Note
that tSFA has a minimum of 25 ns. This means that when IFCLK
is running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■
At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO. Note: the data is prefetched and is driven on the bus
when SLOE is asserted.
At t = 2, SLRD is asserted. SLRD must meet the setup time of
tSRD (time from asserting the SLRD signal to the rising edge of
the IFCLK) and maintain a minimum hold time of tRDH (time
from the IFCLK edge to the deassertion of the SLRD signal).
If the SLCS signal is used, it must be asserted before SLRD is
IFCLK
N+2
IFCLK
N+3
IFCLK
N+4
SLRD
SLOE
Figure 30 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
■
N+1
SLOE
SLRD
SLRD
SLOE
IFCLK
IFCLK
N+1
IFCLK
N+4
SLRD
N+2
N+3
N+4
IFCLK
N+4
SLOE
N+4
Not Driven
asserted (The SLCS and SLRD signals must both be asserted
to start a valid read condition).
■
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge of
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
MUST also be asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle, on the rising edge of the
clock, the FIFO pointer is updated and incremented to point to
address N+1. For each subsequent rising edge of IFCLK, while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
Note
53. Dashed lines denote signals with programmable polarity.
Document Number: 38-08032 Rev. AD
Page 56 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Single and Burst Synchronous Write
Figure 32. Slave FIFO Synchronous Write Sequence and Timing Diagram[54]
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSWR
tWRH
>= tWRH
>= tSWR
T=0
SLWR
t=2
T=2
t=3
T=5
SLCS
tXFLG
tXFLG
FLAGS
tFDH
tSFD
tSFD
N+1
N
DATA
t=1
tFDH
T=1
tSFD
tSFD
tFDH
N+3
N+2
T=3
tFDH
T=4
tSPE
tPEH
PKTEND
Figure 32 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
followed by burst write of three bytes and committing all four
bytes as a short packet using the PKTEND pin.
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 32, after the four bytes are written to the FIFO,
SLWR is deasserted. The short 4 byte packet can be committed
to the host by asserting the PKTEND signal.
■
At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied LOW in some applications) Note
that tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■
At t = 1, the external master/peripheral must outputs the data
value onto the data bus with a minimum set up time of tSFD
before the rising edge of IFCLK.
■
At t = 2, SLWR is asserted. The SLWR must meet the setup
time of tSWR (time from asserting the SLWR signal to the rising
edge of IFCLK) and maintain a minimum hold time of tWRH (time
from the IFCLK edge to the deassertion of the SLWR signal).
If the SLCS signal is used, it must be asserted with SLWR or
before SLWR is asserted (The SLCS and SLWR signals must
both be asserted to start a valid write condition).
There is no specific timing requirement that should be met for
asserting PKTEND signal with regards to asserting the SLWR
signal. PKTEND can be asserted with the last data value or
thereafter. The only requirement is that the setup time tSPE and
the hold time tPEH must be met. In the scenario of Figure 32, the
number of data values committed includes the last value written
to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND can also be asserted in subsequent clock cycles. The
FIFOADDR lines should be held constant during the PKTEND
assertion.
■
While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
The FIFO flag is also updated after a delay of tXFLG from the
rising edge of the clock.
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the
Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner-case condition that
needs attention while using the PKTEND to commit a one
byte/word packet. Additional timing requirements exist when the
FIFO is configured to operate in auto mode and it is desired to
send two packets: a full packet (‘full’ defined as the number of
bytes in the FIFO meeting the level set in the AUTOINLEN
register) committed automatically followed by a short one byte or
word packet committed manually using the PKTEND pin.
In this case, the external master must ensure to assert the
PKTEND pin at least one clock cycle after the rising edge that
caused the last byte or word that needs to be clocked into the
previous auto committed packet (the packet with the number of
bytes equal to what is set in the AUTOINLEN register). Refer to
Figure 24 on page 53 for further details on this timing.
Note
54. Dashed lines denote signals with programmable polarity.
Document Number: 38-08032 Rev. AD
Page 57 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram[55]
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tRDpwl
tRDpwh
tRDpwl
T=0
tRDpwh
tRDpwl
tRDpwl
tRDpwh
tRDpwh
SLRD
t=3
t=2
T=3
T=2
T=5
T=4
T=6
SLCS
tXFLG
tXFLG
FLAGS
tXFD
Data (X)
Driven
DATA
tXFD
tXFD
N
N
tXFD
N+3
N+2
tOEon
tOEoff
tOEon
N+1
tOEoff
SLOE
t=4
t=1
T=7
T=1
Figure 34. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
FIFO POINTER
N
FIFO DATA BUS Not Driven
SLRD
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
SLOE
N
N
N+1
N+1
N+1
N+1
N+2
N+2
N+3
N+3
Driven: X
N
N
Not Driven
N
N+1
N+1
N+2
N+2
Not Driven
Figure 33 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of tXFD from the activating edge of SLRD. In Figure 33, data N
is the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (SLRD is asserted), SLOE
must be in an asserted state. SLRD and SLOE can also be tied
together.
■
At t = 0, the FIFO address is stable and the SLCS signal is
asserted.
■
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is the previous
data, the data that was in the FIFO from an earlier read cycle.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of tRDpwl and minimum de-active pulse width of
tRDpwh. If SLCS is used, then SLCS must be asserted before
SLRD is asserted (The SLCS and SLRD signals must both be
asserted to start a valid read condition.)
Note In the burst read mode, during SLOE is asserted, the data
bus is in a driven state and outputs the previous data. After SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is
incremented.
■
Note
55. Dashed lines denote signals with programmable polarity.
Document Number: 38-08032 Rev. AD
Page 58 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Sequence Diagram of a Single and Burst Asynchronous Write
Figure 35. Slave FIFO Asynchronous Write Sequence and Timing Diagram[56]
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tWRpwl
tWRpwh
T=0
tWRpwl
tWRpwl
tWRpwh
tWRpwl
tWRpwh
tWRpwh
SLWR
t=3
t =1
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
tXFLG
tXFLG
FLAGS
tSFD tFDH
tSFD tFDH
tSFD tFDH
tSFD tFDH
N+1
N+2
N+3
N
DATA
t=2
T=2
T=5
T=8
tPEpwl
tPEpwh
PKTEND
Figure 35 shows the timing relationship of the SLAVE FIFO write
in an asynchronous mode. The diagram shows a single write
followed by a burst write of 3 bytes and committing the 4byte
short packet using PKTEND.
■
At t = 0 the FIFO address is applied, ensuring that it meets the
setup time of tSFA. If SLCS is used, it must also be asserted
(SLCS may be tied LOW in some applications).
■
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of tWRpwl and minimum de-active pulse width of
tWRpwh. If the SLCS is used, it must be asserted with SLWR or
before SLWR is asserted.
■
At t = 2, data must be present on the bus tSFD before the
deasserting edge of SLWR.
■
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after tXFLG from the deasserting
edge of SLWR.
The same sequence of events is shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
In Figure 35, after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be committed
to the host using PKTEND. The external device should be
designed to not assert SLWR and the PKTEND signal at the
same time. It should be designed to assert the PKTEND after
SLWR is deasserted and met the minimum deasserted pulse
width. The FIFOADDR lines have to held constant during the
PKTEND assertion.
Note
56. Dashed lines denote signals with programmable polarity.
Document Number: 38-08032 Rev. AD
Page 59 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Ordering Information
Table 33. Ordering Information
Ordering Code
Package Type
RAM Size
Address
# Prog I/Os 8051
/Data Bus
Serial Debug[57]
Ideal for Battery Powered Applications
CY7C68014A-128AXC
128 TQFP – Pb-free
16K
40
16-/8-bit
Y
CY7C68014A-100AXC
100 TQFP – Pb-free
16K
40
–
Y
CY7C68014A-56PVXC
56 SSOP – Pb-free
16K
24
–
N
CY7C68014A-56LTXC
56 QFN - Pb-free
16K
24
–
N
CY7C68016A-56LTXC
56 QFN - Pb-free
16K
26
–
N
CY7C68016A-56LTXCT
56 QFN - Pb-free
16K
26
–
N
Ideal for Non Battery Powered Applications
CY7C68013A-128AXC
128 TQFP – Pb-free
16K
40
16-/8-bit
Y
CY7C68013A-128AXI
128 TQFP – Pb-free (Industrial)
16K
40
16-/8-bit
Y
CY7C68013A-100AXC
100 TQFP – Pb-free
16K
40
–
Y
CY7C68013A-100AXI
100 TQFP – Pb-free (Industrial)
16K
40
–
Y
CY7C68013A-56PVXC
56 SSOP – Pb-free
16K
24
–
N
CY7C68013A-56PVXCT
56 SSOP – Pb-free
16K
24
–
N
CY7C68013A-56PVXI
56 SSOP – Pb-free (Industrial)
16K
24
–
N
CY7C68013A-56BAXC
56 VFBGA – Pb-free
16K
24
–
N
CY7C68013A-56BAXCT
56 VFBGA – Pb-free
16K
24
–
N
CY7C68013A-56LTXC
56 QFN – Pb-free
16K
24
–
N
CY7C68013A-56LTXCT
56 QFN – Pb-free
16K
24
–
N
CY7C68013A-56LTXI
56 QFN – Pb-free (Industrial)
16K
24
–
N
CY7C68015A-56LTXC
56 QFN – Pb-free
16K
26
–
N
Development Tool Kit
CY3684
EZ-USB FX2LP development kit
CY3689
EZ-USB FX2LP Discovery Kit
Reference Design Kit
CY4611B
USB 2.0 to ATA/ATAPI reference design using EZ-USB FX2LP
Ordering Code Definitions
CY
7
C
68
XXXX
-
XXXXX
(C, I)
(T)
Tape and Reel
Thermal Rating:
C = Commercial
I = Industrial
Package Type:
LTX = QFN (Saw Type) Pb-free
LFX = QFN (Punch Type) Pb-free
Part Number
Family Code: 68 = USB
Technology Code: C = CMOS
Marketing Code: 7 = Cypress Products
Company ID: CY = Cypress
Note
57. As UART is not available in the 56-pin package of CY7C68013A, serial port debugging using Keil Monitor is not possible.
Document Number: 38-08032 Rev. AD
Page 60 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Package Diagrams
The FX2LP is available in five packages:
■
56-pin SSOP
■
56-pin QFN
■
100-pin TQFP
■
128-pin TQFP
■
56-ball VFBGA
Figure 36. 56-pin SSOP (300 Mils) Package Outline, 51-85062
51-85062 *F
Document Number: 38-08032 Rev. AD
Page 61 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 37. 56-pin QFN ((8 × 8 × 1 mm) 4.5 × 5.2 E-Pad (Sawn)) Package Outline, 001-53450
001-53450 *E
Figure 38. 100-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
A1
0.05
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
0°
ș2
11°
0.20
b
0.22 0.30 0.38
0.45 0.60 0.75
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
13°
12°
L
L1
INCLUDE MOLD PROTRUSION/END FLASH.
7°
ș1
c
Document Number: 38-08032 Rev. AD
0.15
NOTE:
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Page 62 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 39. 128-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85101
51-85101 *F
Document Number: 38-08032 Rev. AD
Page 63 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Figure 40. 56-ball VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball Package Outline, 001-03901
001-03901 *F
Document Number: 38-08032 Rev. AD
Page 64 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
PCB Layout Recommendations
■
Bypass and flyback caps on VBUS, near connector, are
recommended.
Follow these recommendations to ensure reliable
high-performance operation:[58]
■
DPLUS and DMINUS trace lengths should be kept to within
2 mm of each other in length, with preferred length of 20 to
30 mm.
■
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to split under these traces.
■
Do not place vias on the DPLUS or DMINUS trace routing.
■
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
■
Four-layer, impedance-controlled boards are required to
maintain signal quality.
■
Specify impedance targets (ask your board vendor what they
can achieve).
■
To control impedance, maintain trace widths and trace spacing.
■
Minimize stubs to minimize reflected signals.
■
Connections between the USB connector shell and signal
ground must be near the USB connector.
Note
58. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com and High Speed USB Platform Design Guidelines,
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Document Number: 38-08032 Rev. AD
Page 65 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Quad Flat Package No Leads (QFN) Package Design Notes
Electrical contact of the part to the PCB is made by soldering the
leads on the bottom surface of the package to the PCB.
Therefore, special attention is required to the heat transfer area
below the package to provide a good thermal bond to the circuit
board. Design a copper (Cu) fill in the PCB as a thermal pad
under the package. Heat is transferred from the FX2LP through
the device’s metal paddle on the bottom side of the package.
Heat from here is conducted to the PCB at the thermal pad. It is
then conducted from the thermal pad to the PCB inner ground
plane by a 5 × 5 array of via. A via is a plated-through hole in the
PCB with a finished diameter of 13 mil. The QFN’s metal die
paddle must be soldered to the PCB’s thermal pad. Solder mask
is placed on the board top side over each via to resist solder flow
into the via. The mask on the top side also minimizes outgassing
during the solder reflow process.
For further information on this package design, refer to
application notes for Surface Mount Assembly of Amkor's
MicroLeadFrame (MLF) Packages. You can find this on Amkor's
website http://www.amkor.com.
This application note provides detailed information about board
mounting guidelines, soldering flow, rework process, etc.
Figure 41 shows a cross-sectional area underneath the
package. The cross section is of only one via. The solder paste
template should be designed to allow at least 50% solder
coverage. The thickness of the solder paste template should be
5 mil. Use the No Clean type 3 solder paste for mounting the part.
Nitrogen purge is recommended during reflow.
Figure 42 is a plot of the solder mask pattern and Figure 43
displays an X-Ray image of the assembly (darker areas indicate
solder).
Figure 41. Cross-section of the Area Underneath the QFN Package
0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
Via hole for thermally connecting the
QFN to the circuit board ground plane.
0.013” dia
PCB Material
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Figure 42. Plot of the Solder Mask (White Area)
Figure 43. X-ray Image of the Assembly
Document Number: 38-08032 Rev. AD
Page 66 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Acronyms
Document Conventions
Table 34. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 35. Units of Measure
ASIC
application-specific integrated circuit
ATA
advanced technology attachment
kHz
DID
device identifier
mA
milliamperes
DSL
digital service line
Mbps
megabits per second
DSP
digital signal processor
MBPs
megabytes per second
ECC
error correction code
MHz
megahertz
EEPROM
electrically erasable programmable read only
memory
uA
microamperes
V
volts
EPP
enhanced parallel port
FIFO
first in first out
GPIF
general programmable interface
GPIO
general purpose input output
I/O
input output
LAN
local area network
MPEG
moving picture experts group
PCMCIA
personal computer memory card international
association
PID
product identifier
PLL
phase locked loop
QFN
quad flat no leads
RAM
random access memory
SIE
serial interface engine
SOF
start of frame
SSOP
super small outline package
TQFP
thin quad flat pack
USART
universal serial asynchronous receiver/transmitter
USB
universal serial bus
UTOPIA
universal test and operations physical-layer
interface
VFBGA
very fine ball grid array
VID
vendor identifier
Document Number: 38-08032 Rev. AD
Symbol
Unit of Measure
kilohertz
Page 67 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Errata
This section describes the errata for the EZ-USB® FX2LP™ CY7C68013A/14A/15A/16A Rev. B silicon. Details include errata trigger
conditions, scope of impact, available workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Package Type
Operating Range
CY7C68013A
All
Commercial
CY7C68014A
All
Commercial
CY7C68015A
All
Commercial
CY7C68016A
All
Commercial
CY7C68013A/14A/15A/16A Qualification Status
In production
CY7C68013A/14A/15A/16A Errata Summary
This table defines the errata for available CY7C68013A/14A/15A/16A family devices. An “X” indicates that the errata pertain to the
selected device.
Items
CY7C68013A/14A/15A/16A Silicon Revision
[1.]. Empty Flag Assertion
X
B
Fix Status
No silicon fix planned currently. Use the workaround.
1. Empty Flag Assertion
■
Problem Definition
In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT
Endpoint (EP) in the first transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than
one word in the first transaction.
■
Parameters Affected
NA
■
Trigger Condition(S)
In Slave FIFO Asynchronous Word Wide Mode, after firmware boot and initialization, EP2 OUT endpoint empty flag indicates the
status as ‘Empty’. When data is received in EP2, the status changes to ‘Not-Empty’. However, if data transferred to EP2 is a single
word, then asserting SLRD with FIFOADR pointing to any other endpoint changes ‘Not-Empty’ status to ‘Empty’ for EP2 even
though there is a word data (or it is untouched). This is noticed only when the single word is sent as the first transaction and not if
it follows a multi-word packet as the first transaction.
■
Scope of Impact
External interface does not see data available in EP2 OUT endpoint and can end up waiting for data to be read.
■
Workaround
One of the following workarounds can be used:
• Send a pulse signal to the SLWR pin, with FIFOADR pins pointing to an endpoint other than EP2, after firmware initialization
and before or after transferring the data to EP2 from the host
• Set the length of the first data to EP2 to be more than a word
• Prioritize EP2 read from the Master for multiple OUT EPs and single word write to EP2
• Write to an IN EP, if any, from the Master before reading from other OUT EPs (other than EP2) from the Master.
■
Fix Status
There is no silicon fix planned for this currently; use the workarounds provided.
Document Number: 38-08032 Rev. AD
Page 68 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document History Page
Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed
USB Peripheral Controller
Document Number: 38-08032
Rev.
ECN No.
Submission
Date
**
124316
03/17/2003
New data sheet (Advance Information).
*A
128461
09/02/2003
Updated Document Title to read as “CY7C68013A/CY7C68015A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller”.
Changed status from Advance Information to Final.
Added CY7C68015A part related information in all instances across the document.
Replaced I2C-compatible with I2C in all instances across the document.
Updated Logic Block Diagram (Added ECC block and fixed errors).
Updated Functional Overview:
Updated 8051 Microprocessor:
Updated 8051 Clock Frequency:
Added Figure 1.
Updated Reset and Wakeup:
Updated Reset Pin:
Updated description; added Figure 2; and also added Table 5.
Updated Register Addresses:
Updated figure below the heading.
Updated Endpoint RAM:
Updated Endpoint Configurations (Hi-Speed Mode):
Updated Figure 5 (for clarity).
Added ECC Generation.
Updated I2C Controller:
Added “I2C Software Reset”.
Updated Compatible with Previous Generation EZ-USB FX2:
Updated description; and also updated Table 9.
Added CY7C68013A/14A and CY7C68015A/16A Differences.
Updated Register Summary:
Updated Table 12.
Updated Package Diagrams:
spec 51-85144 – Changed revision from *B to *D.
Minor grammatical edits across the document.
Description of Change
*B
130335
10/09/2003
Changed status from Final to Preliminary.
*C
131673
02/12/2004
Updated Functional Overview:
Updated Reset and Wakeup:
Updated Reset Pin:
Updated description; added Note 7 and referred the same note at the end of sentence “If the crystal
input pin is driven by a clock signal the internal PLL stabilizes in 200 μs after VCC has reached 3.0 Volts”.
Updated Endpoint RAM:
Updated Endpoint Configurations (Hi-Speed Mode):
Updated description (Replaced column 9 with column 8 in last paragraph).
Updated ECC Generation:
Updated description.
Removed “ECC Features”.
Updated ECC Implementation:
Updated description.
Updated Register Summary:
Updated Table 12.
*C (cont.)
131673
02/12/2004
Updated DC Electrical Characteristics:
Updated Table 14:
Added VIH_X, VIL_X parameters and their corresponding details.
Updated USB Transceiver:
Replaced “certified” with “compliant”.
Updated AC Electrical Characteristics:
Updated USB Transceiver:
Replaced “certified” with “compliant”.
Updated Data Memory Write[33]:
Updated Figure 14.
Added Sequence Diagram.
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
*D
230713
06/09/2004
Updated Ordering Information:
Updated Table 33:
Updated part numbers (Changed Lead free MPNs as per spec change in 28-00054).
Document Number: 38-08032 Rev. AD
Page 69 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document History Page (continued)
Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed
USB Peripheral Controller
Document Number: 38-08032
Rev.
ECN No.
Submission
Date
*E
242398
07/13/2004
Minor Change:
Post to external web,
*F
271169
10/07/2004
Updated Features:
Added “USB 2.0–USB-IF high speed certified (TID # 40440111)”.
Added Features (CY7C68013A/14A only).
Added Features (CY7C68015A/16A only).
Updated Logic Block Diagram (Added USB 2.0 logo).
Updated Absolute Maximum Ratings:
Replaced TBD with values for “Power Dissipation”.
Updated DC Electrical Characteristics:
Updated Table 14:
Updated minimum and maximum values of VCC parameter.
Replaced TBD with values for VIH_X, VIL_X, ISUSP, ICC parameters.
Updated AC Electrical Characteristics:
Updated Slave FIFO Asynchronous Packet End Strobe:
Updated Table 28:
Changed maximum value of tXFLG parameter from 70 ns to 115 ns.
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
*G
316313
02/04/2005
Updated Document Title to read as “CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A,
EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller”.
Changed status from Preliminary to Final.
Added CY7C68014A, CY7C68016A part related information in all instances across the document.
Updated DC Electrical Characteristics:
Updated Table 14:
Added VCC Ramp Up parameter and its corresponding details.
Updated AC Electrical Characteristics:
Updated Slave FIFO Synchronous Packet End Strobe:
Added description; and also added Figure 24.
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
*H
338901
04/18/2005
Updated Register Summary:
Updated Table 12.
Updated AC Electrical Characteristics:
Updated Data Memory Read[31]:
Added description.
Updated Data Memory Write[33]:
Added description.
Updated Slave FIFO Synchronous Read:
Updated Table 20:
Replaced TBD with “–” under “Min” column corresponding to tXFD parameter.
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
*I
371097
06/09/2005
Updated AC Electrical Characteristics:
Added PORTC Strobe Feature Timings.
*J
397239
09/19/2005
Added 56-pin VFBGA Package related information in all instances across the document.
Updated Register Summary:
Updated Table 12.
Updated DC Electrical Characteristics:
Updated Table 14:
Updated minimum and maximum values of VCC parameter.
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
Updated Package Diagrams:
Added spec 001-03901 *B.
Document Number: 38-08032 Rev. AD
Description of Change
Page 70 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document History Page (continued)
Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed
USB Peripheral Controller
Document Number: 38-08032
Rev.
ECN No.
Submission
Date
*K
420505
02/09/2006
Updated Pin Assignments:
Updated description (Replaced “four package types” with “five package types”).
Updated Absolute Maximum Ratings:
Added “Ambient Temperature with Power Supplied (Industrial)” and its corresponding details.
Added Thermal Characteristics.
Updated AC Electrical Characteristics:
Updated Slave FIFO Asynchronous Write:
Updated Figure 22 (Remove SLCS).
Updated Sequence Diagram:
Updated Single and Burst Synchronous Write:
Updated description.
Updated Sequence Diagram of a Single and Burst Asynchronous Read:
Updated description.
Updated to new template.
*L
2064406
02/04/2008
Updated Features:
Replaced “TID # 40440111” with “TID # 40460272”.
Updated Functional Overview:
Updated CY7C68013A/14A and CY7C68015A/16A Differences:
Updated Table 10 (Removed T0OUT and T1OUT in “CY7C68015A/CY7C68016A” column).
Updated AC Electrical Characteristics:
Updated Slave FIFO Synchronous Write:
Updated Table 23 (Updated minimum value of tSWR parameter).
Updated Package Diagrams:
spec 51-85144 – Changed revision from *D to *G.
*M
2710327
05/22/2009
Updated Operating Conditions:
Changed value of FOSC (oscillator or crystal frequency) from
“24 MHz ± 100 ppm, Parallel Resonant” to “24 MHz ± 10 ppm, Parallel Resonant”.
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
Updated Package Diagrams:
Added spec 51-85187 *C.
*N
2727334
07/01/2009
Updated Package Diagrams:
spec 51-85187 – Changed revision from *C to *D.
Fixed Typo in Document History Page (Removed sentence on E-Pad size change from *F revision).
*O
2756202
08/26/2009
Updated Ordering Information:
Updated Table 33:
No change in part numbers.
Added a column “Serial Debug” and added details under the column.
Added Note 57 and referred the same note in “Serial Debug”.
*P
2785207
10/12/2009
Updated Ordering Information:
Updated Table 33:
No change in part numbers.
Updated details in “Package Type” column (Added information on Pb-free parts).
*Q
2811890
11/20/2009
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
Updated details under “# Program I/Os” column for CY7C68016A-56LTXC and
CY7C68016A-56LTXCT MPNs.
*R
2896281
03/19/2010
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
Updated Package Diagrams:
spec 51-85062 – Changed revision from *C to *D.
spec 51-85144 – Changed revision from *G to *H.
spec 51-85187 – Changed revision from *D to *E.
spec 51-85050 – Changed revision from *B to *C.
spec 51-85101 – Changed revision from *C to *D.
Updated to new template.
Document Number: 38-08032 Rev. AD
Description of Change
Page 71 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document History Page (continued)
Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed
USB Peripheral Controller
Document Number: 38-08032
Rev.
ECN No.
Submission
Date
*S
3035980
09/22/2010
Updated Operating Conditions:
Changed value of FOSC (oscillator or crystal frequency) from
“24 MHz + 10 ppm, Parallel Resonant” to “24 MHz + 100 ppm, Parallel Resonant”.
Updated Ordering Information:
Updated Table 33:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
*T
3161410
02/03/2011
Updated Package Diagrams:
Removed spec 51-85144 *H.
Added spec 001-12921 *A.
Removed spec 51-85187 *E.
Added spec 001-53450 *B.
spec 51-85050 – Changed revision from *C to *D.
spec 51-85101 – Changed revision from *D to *E.
Completing Sunset Review.
*U
3195232
03/14/2011
Updated table numbering.
Updated Thermal Characteristics:
Updated Table 13 (Removed column “Ca Case to Ambient Temperature (°C/W)”).
Updated AC Electrical Characteristics:
Updated GPIF Synchronous Signals:
Updated Table 18 (Added a column “Typ” and added values in that column).
Updated Slave FIFO Synchronous Read:
Updated Table 20 (Added a column “Typ” and added values in that column).
Updated Package Diagrams:
spec 001-12921 – Changed revision from *A to *B.
spec 001-03901 – Changed revision from *C to *D.
*V
3512313
02/01/2012
Updated Ordering Information:
Updated Table 33:
Updated part numbers.
Updated Package Diagrams:
spec 51-85062 – Changed revision from *D to *E.
Removed spec 001-12921 *B.
spec 001-03901 – Changed revision from *D to *E.
Completing Sunset Review.
*W
3998554
07/19/2013
Added Errata footnote (Note 6).
Updated Functional Overview:
Updated Interrupt System:
Updated FIFO/GPIF Interrupt (INT4):
Added Note 6 and referred the same note in “Endpoint 2 empty flag” in Table 4.
Updated Package Diagrams:
spec 51-85062 – Changed revision from *E to *F.
spec 001-53450 – Changed revision from *B to *C.
Added Errata.
Updated to new template.
*X
4617527
01/15/2015
Added More Information.
Updated Pin Assignments:
Updated CY7C68013A/15A Pin Descriptions:
Updated Table 11 (Added a column “Reset” and added details in that column).
Updated AC Electrical Characteristics:
Updated Data Memory Read[31]:
Added Note 31 and referred the same note in heading.
Updated Figure 13.
Updated Data Memory Write[33]:
Added Note 31 and referred the same note in heading.
Updated Package Diagrams:
spec 001-53450 – Changed revision from *C to *D.
spec 51-85050 – Changed revision from *D to *E.
spec 51-85101 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*Y
5317277
06/28/2016
Updated to new template.
Document Number: 38-08032 Rev. AD
Description of Change
Page 72 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document History Page (continued)
Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed
USB Peripheral Controller
Document Number: 38-08032
Rev.
ECN No.
Submission
Date
*Z
5713641
04/26/2017
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
AA
5930426
11/09/2017
Updated AC Electrical Characteristics:
Updated GPIF Synchronous Signals:
Updated Table 18.
Updated Table 19.
AB
6403695
12/06/2018
Updated Features:
Added Note 1 and referred the note at the end in “Integrated I2C controller; runs at 100 or 400 kHz”.
Updated Functional Overview:
Updated I2C Bus:
Added Note 4 and referred the note at the end in “FX2LP supports the I2C bus as a master only at
100/400 kHz”.
Updated Thermal Characteristics:
Added “Maximum junction temperature” and its corresponding details.
Updated Package Diagrams:
spec 001-53450 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
AC
6637530
07/26/2019
Updated to new template.
AD
7113265
04/30/2021
Updated EZ-USB FX2LP Development Kit in More Information.
Added “CY3689” in Ordering Information.
Document Number: 38-08032 Rev. AD
Description of Change
Page 73 of 74
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
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Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary of
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Document Number: 38-08032 Rev. AD
Revised April 30, 2021
FX2LP is a trademark and EZ-USB is a registered trademark of Cypress Semiconductor Corporation.
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