Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY7C68023/CY7C68024
®
EZ-USB NX2LP™
USB 2.0 NAND Flash Controller
CY7C68023/CY7C68024, EZ-USB® NX2LP™ USB 2.0 NAND Flash Controller
Features
■
43 mA typical active current
■
Space-saving and Pb-free 56-pin QFN package (8 mm × 8 mm)
■
Support for board-level manufacturing test through USB
interface
■
3.3 V NAND flash operation
Eight chip enable pins
❐ Up to eight NAND flash single device chips
❐ Up to four NAND flash dual-device chips
■
NAND flash power management support
■
Industry-standard ECC NAND flash correction
❐ 1-bit error correction per 256 bytes
❐ 2-bit error detection per 256 bytes
■
Industry-standard (SmartMedia) Page Management for Wear
Leveling Algorithm, Bad Block Handling, and Physical to
Logical management
The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND
Flash controller. This controller adheres to the Mass Storage
Class Bulk-Only Transport Specification. The USB port of the
NX2LP is connected to a host computer directly or through the
downstream port of a USB hub. The Host software issues
commands and data to the NX2LP and receives the status and
data from the NX2LP using the standard USB protocol.
■
Supports 8-bit NAND flash interfaces
■
Supports 30 ns, 50 ns, and 100 ns NAND flash timing
■
Complies with the USB Mass Storage Class Specification
Revision 1.0
■
High-Speed (480 Mbps) or Full-Speed (12 Mbps) USB support
■
Both common NAND page sizes supported
❐ 512 bytes — Up to 1 Gbit capacity
❐ 2K bytes — Up to 8 Gbit capacity
■
■
Functional Description
CY7C68024 complies with the USB 2.0 Specification for
Bus-Powered Devices (TID# 40460274)
The NX2LP supports industry-leading 8-bit NAND flash
interfaces and both common NAND page sizes of 512 and 2k
bytes. Eight chip enable pins allow the NX2LP to be connected
to up to eight single or four dual-device NAND flash chips.
Certain NX2LP features are configurable, enabling the NX2LP to
meet the needs of different design requirements.
NX2LP Block Diagram
Write Protect
Chip Reset
LED2#
24 MHz
Xtal
LED1#
PLL
EZ-USB NX2LP
Internal Control Logic
Control
NAND Control Signals
NAND Flash
Interface
Logic
VBUS
D+
D-
Smart HS/
FS USB
Engine
USB 2.0
Xceiver
Cypress Semiconductor Corporation
Document Number: 38-08055 Rev. *J
•
198 Champion Court
Chip Enable Signals
8-bit Data Bus
Data
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2020
CY7C68023/CY7C68024
Pin Assignments
GND
VCC
N/C
GND
CE7#
CE6#
CE5#
CE4#
CE3#
CE2#
CE1#
CE0#
Reserved
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Figure 1. 56-pin QFN pinout
R_B1#
1
42
RESET#
R_B2#
2
41
GND
AVCC
3
40
N/C
XTALOUT
4
39
N/C
XTALIN
5
38
WP_SW#
AGND
6
37
Reserved
AVCC
7
36
LED2#
DPLUS
8
35
LED1#
DMINUS
9
34
ALE
AGND
10
33
CLE
20
21
22
23
24
25
26
27
28
DD3
DD4
DD5
DD6
DD7
GND
VCC
GND
WE#
DD2
29
19
14
18
GND
DD1
RE0#
DD0
30
17
13
VCC
RE1#
N/C
16
VCC
31
15
32
12
Reserved
11
Reserved
VCC
GND
Pin Descriptions
Pin
1
2
3
Name
R_B1#[1]
R_B2#
AVCC
Type
I
I
PWR
Default State at Startup
Z
Z
PWR
Description
Ready/Busy 1 (2.2k to 4k pull-up resistor is required)
Ready/Busy 2 (2.2k to 4k pull-up resistor is required)
Analog 3.3 V supply
4
5
6
7
8
9
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
Xtal
Xtal
GND
PWR
I/O
I/O
N/A
N/A
GND
PWR
Z
Z
Crystal output
Crystal input
Ground
Analog 3.3 V supply
USB D+
USB D-
10
AGND
GND
GND
Ground
11
12
VCC
GND
PWR
GND
PWR
GND
3.3 V supply
Ground
Note
1. A # sign after the pin name indicates that it is an active LOW signal.
Document Number: 38-08055 Rev. *J
Page 2 of 10
CY7C68023/CY7C68024
Pin Descriptions (continued)
Pin
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Name
N/C
GND
Reserved
Reserved
VCC
DDO
DD1
DD2
DD3
DD4
DD5
DD6
DD7
GND
VCC
GND
WE#
RE0#
RE1#
VCC
CLE
ALE
LED1#
LED2#
Reserved
WP_SW#
N/C
N/C
GND
RESET#
VCC
Reserved
CE0#
CE1#
CE2#
CE3#
CE4#
CE5#
CE6#
Type
N/A
GND
N/A
N/A
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
PWR
GND
O
O
O
PWR
O
O
O
O
O
I
N/A
N/A
GND
I
PWR
N/A
O
O
O
O
O
O
O
Default State at Startup
N/A
GND
N/A
N/A
PWR
Z
Z
Z
Z
Z
Z
Z
Z
GND
PWR
GND
H
H
H
PWR
Z
Z
Z
Z
Z
Z
N/A
N/A
GND
Z
PWR
N/A
Z
Z
Z
Z
Z
Z
Z
52
53
54
55
56
CE7#
GND
N/C
VCC
GND
O
GND
N/A
PWR
GND
Z
GND
N/A
PWR
GND
Document Number: 38-08055 Rev. *J
Description
No connect
Ground
Must be tied HIGH (no pull-up resistor required)
Must be tied HIGH (no pull-up resistor required)
3.3 V supply
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Ground
3.3 V supply
Ground
Write enable
Read Enable 0
Read Enable 1
3.3 V supply
Command latch enable
Address latch enable
Data activity LED sink
Chip active LED sink
No Connect
Write-protect switch input
No connect
No connect
Ground
NX2LP chip reset
3.3 V supply
Must be tied HIGH
Chip enable 0
Chip enable 1
Chip enable 2
Chip enable 3
Chip enable 4
Chip enable 5
Chip enable 6
Chip enable 7
Ground
No connect
3.3 V supply
Ground
Page 3 of 10
CY7C68023/CY7C68024
Additional Pin Descriptions
RE[1–0]#
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB. General guidelines are given at the end of this document.
The Read Enable output pins are used to control the data flow
from the NAND Flash devices. The device presents valid data
and increments its internal column address counter by one step
on each falling edge of the Read Enable pulse. A 10k pull-up is
an option For RE1–0#.
CLE
The Command Latch Enable output pin is used to indicate that
the data on the I/O bus is a command. The data is latched into
the NAND Flash control register on the rising edge of WE# when
CLE is HIGH.
Figure 2. XTALIN, XTALOUT Diagram
24-MHz Xtal
ALE
12 pF
12 pF
12-pF capacitor
values assume a
trace capacitance
of 3 pF per side on a
four-layer FR4 PCB
The Address Latch Enable output pin is used to indicate that the
data on the I/O bus is an address. The data is latched into the
NAND Flash address register on the rising edge of WE# when
ALE is HIGH.
LED1#
The Data Activity LED output pin is used to indicate data transfer
activity. LED1# is asserted LOW at the beginning of a data
transfer, and set to a HI-Z state when the transfer is complete. If
this functionality is not utilized, leave LED1# floating.
LED2#
XTALIN
XTALOUT
The NX2LP requires a 24-MHz (±100 ppm) signal to derive
internal timing. Typically, a 24-MHz (20 pF, 500 μW,
parallel-resonant fundamental mode) crystal is used, but a
24-MHz square wave from another source can also be used. If
a crystal is used, connect its pins to XTALIN and XTALOUT, and
also through 12 pF capacitors to GND. If an alternate clock
source is used, apply it to XTALIN and leave XTALOUT open.
Data[7–0]
The Data[7-0] I/O pins provide an 8-bit interface to a NAND Flash
device. These pins are used to transfer address, command, and
read/write data between the NX2LP and NAND Flash.
R_B[2–1]#
The Ready/Busy input pins are used to determine the state of the
currently selected NAND Flash device. These pins must be
pulled HIGH through a 2k-4k resistor. These pins are pulled LOW
by the NAND Flash when it is busy.
WE#
The Chip Active LED output pin is used to indicate proper device
operation. LED2# is asserted LOW when the NX2LP is powered
and initialized. It is placed in a HI-Z state under all other
conditions. If this functionality is not used, leave LED2# floating.
WP_SW#
The Write-protect Switch input pin is used to select whether or
not NAND Flash write-protection is enabled by the NX2LP. When
the pin is asserted LOW, the NAND Flash is write protected and
any attempts to write to the configuration data memory are
blocked.
CE[7–0]#
The Chip Enable output pins are used to select the NAND Flash
that the NX2LP interfaces. Unused Chip Enable pins should be
left floating.
RESET#
Asserting RESET# for 10 ms resets the NX2LP. A reset and/or
watchdog chip is recommended to ensure that startup and
brownout conditions are properly handled.
The Write Enable output pin is used by the NAND Flash to latch
commands, address, and data during the rising edge of the
pulse.
Document Number: 38-08055 Rev. *J
Page 4 of 10
CY7C68023/CY7C68024
Applications
Manufacturing Mode
The NX2LP is a High-Speed USB 2.0 peripheral device that
connects NAND Flash devices to a USB host using the USB
Mass Storage Class protocol.
In Manufacturing mode, the NX2LP enumerates using the
default descriptors and configuration data that are stored in
internal ROM. This mode enables first-time programming of the
configuration data memory area, and board-level manufacturing
tests.
Additional Resources
■
CY3685 EZ-USB NX2LP Development Kit
■
CY4618 EZ-USB NX2LP Reference Design Kit
■
USB Specification version 2.0
■
USB Mass Storage Class Bulk Only Transport Specification,
https://usb.org/sites/default/files/usbmassbulk_10.pdf
Functional Overview
USB Signaling Speed
The NX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0 dated April 27, 2000:
■
Full-Speed, with a signaling bit rate of 12 Mbits/sec
■
High-Speed, with a signaling bit rate of 480 Mbits/sec.
A unique USB serial number is required for each device in order
to comply with the USB Mass Storage specification. Cypress
also requires designers to use their own Vendor ID for final
products. The Vendor ID is obtained through registration with the
USB Implementor’s Forum (USB-IF), and the Product ID is
determined by the designer.
Cypress provides all the software tools and drivers necessary for
properly programming and testing the NX2LP. Refer to the
documentation in the development or reference design kit for
more information on these topics.
Figure 3. NX2LP Enumeration Process
Start-up
The NX2LP does not support the low speed signaling rate of
1.5 Mbits/sec.
Yes
NAND Flash Interface
NAND Flash
Present?
No
During normal operation the NX2LP supports an 8-bit I/O
interface, eight chip enable pins, and other control signals
compatible with industry standard NAND Flash devices.
Enumeration
During the startup sequence, internal logic checks for the
presence of NAND Flash with valid configuration data in the
configuration data memory area. If valid configuration data is
found, the NX2LP uses the values stored in NAND Flash to
configure the USB descriptors for normal operation as a USB
mass storage device. If no NAND Flash is detected, or if no valid
configuration data is found in the configuration data memory
area, the NX2LP uses the default values from internal ROM
space for manufacturing mode operation. The two modes of
operation are described in the following sections.
NAND Flash
Programmed?
No
Yes
Load Custom
Descriptors and
Configuration Data
Load Default
Descriptors and
Configuration Data
Enumerate As
USB Mass
Storage Device
Enumerate As
Generic NX2LP
Device
Normal Operation
Mode
Manufacturing
Mode
Normal Operation Mode
In Normal Operation Mode, the NX2LP behaves as a USB 2.0
Mass Storage Class NAND Flash controller. This includes all
typical USB device states (powered, configured, and so on). The
USB descriptors are returned according to the data stored in the
configuration data memory area. Normal read and write access
to the NAND Flash is available in this mode.
Document Number: 38-08055 Rev. *J
Page 5 of 10
CY7C68023/CY7C68024
Configuration Data
Certain features in the NX2LP can be configured by the designer to disable unneeded features, and to comply with the USB 2.0
specification’s descriptor requirements for mass storage devices. Table 1 lists the variable configuration data and the default values
that are stored in internal ROM space. The default ROM values are returned by an unprogrammed NX2LP device.
Table 1. Variable Configuration Data And Default ROM Values
Configuration Data
Description
Default ROM Value
Vendor ID
USB Vendor ID (Assigned by USB-IF)
Product ID
USB Product ID (Assigned by designer)
Serial Number
Manufacturer String
0x04B4 (Cypress)
0x6813
USB serial number
N/A
Manufacturer string in USB descriptors
N/A
Product String
Product string in USB descriptors
N/A
Enable Write Protection
Enables write protection capability
Enabled
SCSI Device Name
String shown in the device manager properties
Design Notes For The Quad Flat No-Lead
(QFN) Package
The NX2LP comes in a 56-pin QFN package, which utilizes a
metal pad on the bottom to aid in heat dissipation. The low-power
operation of the NX2LP makes the thermal pad on the bottom of
the QFN package unnecessary. Because of this, PCB layout may
utilize the space under the NX2LP for routing signals as needed,
provided that any traces or vias under the thermal pad are
covered by solder mask or other material to prevent shorting.
Standard PCB layout recommendations for USB devices still
apply.
For further information on this package design, please refer to
the application note from AMKOR titled “Surface Mount
Assembly of AMKOR’s MicroLeadFrame (MLF) Technology.”
This application note provides detailed information on board
mounting guidelines, soldering flow, rework process, etc.
N/A
PCB Layout Recommendations
The following recommendations should be followed to ensure
reliable High-speed USB performance operation.
■
A four-layer impedance controlled board is recommended to
ensure best signal quality.
■
Specify impedance targets (ask your board vendor what they
can achieve).
■
Maintain trace widths and trace spacing to control impedance.
■
Minimize stubs on DPLUS and DMINUS to avoid reflected
signals.
■
Place any connections between the USB connector shell and
signal ground near the USB connector.
■
Use bypass/flyback caps on VBUS, placed near connector.
■
Keep DPLUS and DMINUS trace lengths to within 2 mm of
each other in length, with preferred length of 20 mm–30 mm.
■
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
■
Place no vias on the DPLUS or DMINUS trace routing.
■
Isolate the DPLUS and DMINUS traces from all other signal
traces (use >10 mm. spacing for best signal quality).
Source for recommendations:
■
Document Number: 38-08055 Rev. *J
EZ-USB
FX2
PCB
Design
www.cypress.com/comment/47141.
Recommendations,
Page 6 of 10
CY7C68023/CY7C68024
Absolute Maximum Ratings
Power Dissipation .................................................... 300 mW
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ........................................... 2000 V
Max Output Current per IO port .................................. 10 mA
Storage Temperature ............................... –65 °C to +150 °C
Operating Conditions[2]
Ambient Temperature
with Power Supplied ...................................... 0 °C to +70 °C
TA (Ambient Temperature Under Bias) .......... 0 °C to +70 °C
Supply Voltage to Ground Potential .............–0.5 V to +4.0 V
Supply Voltage .........................................+3.00 V to +3.60 V
DC Input Voltage to Any Input Pin .............................. 5.25 V
Ground Voltage ................................................................ 0 V
DC Voltage Applied to Outputs
in High-Z State .................................... –0.5 V to VCC + 0.5 V
FOSC (Oscillator or Crystal Frequency)
Parallel Resonant .................................. 24 MHz ± 100 ppm
DC Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
VCC
Supply voltage
3.0
3.3
3.6
V
VCC Ramp
Supply Ramp-up 0 V to 3.3 V
200
–
–
μs
VIH
Input High voltage
2
–
5.25
V
VIL
Input Low voltage
–0.5
–
0.8
V
–
–
±10
μA
2
–
5.25
V
–0.5
–
0.8
V
2.4
–
–
V
II
Input leakage current
VIH_X
Crystal Input HIGH voltage
VIL_X
Crystal Input LOW voltage
VOH
Output voltage High
IOUT = 4 mA
VOL
Output voltage Low
IOUT = –4 mA
IOH
Output current High
IOL
Output current Low
CIN
Input pin capacitance
All but D+/D–
Only D+/D–
ICC
Supply current
USB High-Speed
ISUSP
Suspend current
CY7C68023
CY7C68024
0 < VIN < VCC
–
–
0.4
V
–
–
4
mA
–
–
4
mA
–
–
10
pF
–
–
15
pF
–
50
–
mA
USB Full-Speed
–
35
–
mA
Connected
–
0.5
1.2[3]
mA
Disconnected
–
0.3
1.0[3]
mA
Connected
–
300
380[3]
μA
μA
Disconnected
–
100
150[3]
IUNCONFIG
Unconfigured current
Before current requested in USB
descriptors is granted by the host
–
43
–
mA
TRESET
Reset Time After Valid Power
VCC > 3.0 V
5.0
–
–
mS
200
–
–
μS
Pin reset after valid startup
AC Electrical Characteristics
USB Transceiver
The NX2LP’s USB interface complies with the USB 2.0 specification for bus-powered devices.
NAND Flash Timing
The NX2LP supports 30-ns, 50-ns, and 100-ns NAND Flash devices.
Notes
2. If an alternate clock source is input on XTALIN, it must be supplied with standard 3.3 V signaling characteristics and XTALOUT must be left floating.
3. Measured at Max VCC, 25 °C.
Document Number: 38-08055 Rev. *J
Page 7 of 10
CY7C68023/CY7C68024
Ordering Information
Part Number
CY7C68023-56LTXC
Package Type
56-pin QFN - Sawn type
Package Diagram
Figure 4. 56-pin QFN (8 × 8 × 0.9 mm) - Sawn
001-53450 *E
Document Number: 38-08055 Rev. *J
Page 8 of 10
CY7C68023/CY7C68024
Document History Page
Description Title: CY7C68023/CY7C68024, EZ-USB® NX2LP™ USB 2.0 NAND Flash Controller
Document Number: 38-08055
Rev.
ECN No.
Submission
Date
**
286009
11/11/2004
New data sheet (Preliminary Information).
*A
334796
03/16/2005
Changed status from Preliminary to Final.
Updated Enumeration:
Updated Configuration Data:
Updated Table 1 (Replaced “0x6823 (NX2LP)” with “0x6813” in “Default ROM Value” column
corresponding to Product ID).
*B
397024
09/16/2005
Updated Operating Conditions:
Updated details corresponding to “Supply Voltage”.
Updated DC Characteristics:
Changed minimum value of VCC parameter from 3.15 V to 3.0 V.
Changed maximum value of VCC parameter from 3.45 V to 3.6 V.
Updated to new template.
*C
2717536
06/11/2009
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85144 – Changed revision from *D to *G.
Added spec 001-53450 **.
*D
2896245
03/19/2010
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85144 – Changed revision from *G to *H.
spec 001-53450 – Changed revision from ** to *B.
*E
3208866
03/29/2011
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85144 – Changed revision from *H to *I.
Updated to new template.
*F
3330673
07/28/2011
Updated Package Diagram:
Removed spec 51-85144 *I.
*G
3645844
06/14/2012
Updated Pin Assignments:
Updated Figure 1 (Marked Pin 37 as Reserved).
Updated Pin Descriptions:
Replaced “WP_NF#” with “Reserved” in “Name” column corresponding to pin 37.
Updated Additional Pin Descriptions:
Updated WP_SW#:
Updated description.
*H
4479631
09/23/2014
Updated Features:
Updated details under “Industry-standard ECC NAND flash correction”.
Updated Package Diagram:
spec 001-53450 – Changed revision from *B to *D.
*I
5883839
09/14/2017
Updated to new template.
Completing Sunset Review.
*J
6896593
06/12/2020
Updated Package Diagram:
spec 001-53450 – Changed revision from *D to *E.
Document Number: 38-08055 Rev. *J
Description of Change
Page 9 of 10
CY7C68023/CY7C68024
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Training | Components
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© Cypress Semiconductor Corporation, 2004-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility
of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any
device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.
“Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect
its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product
as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims,
costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical
Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published
data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a
Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-08055 Rev. *J
Revised June 12, 2020
EZ-USB NX2LP is a trademark and EZ-USB is a registered trademark of Cypress Semiconductor Corporation.
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