CY7C68053-56BAXI

CY7C68053 MoBL-USB™ FX2LP18 USB Microcontroller 1. CY7C68053 Features ■ ■ ■ USB 2.0 – USB-IF High Speed and Full Speed Compliant (TID# 40000188) Single-Chip Integrated USB 2.0 Transceiver, Smart SIE, and Enhanced 8051 Microprocessor Ideal for Mobile Applications (Cell Phone, Smart Phones, PDAs, MP3 Players) ❐ Ultra low power ❐ Suspend current: 20 µA (typical) Software: 8051 Code runs from: ❐ Internal RAM, which is loaded from EEPROM 16 kBytes of On-Chip Code/Data RAM Four Programmable BULK/INTERRUPT/ISOCHRONOUS endpoints ❐ Buffering options: double, triple, and quad Additional Programmable (BULK/INTERRUPT) 64-Byte Endpoint 8 or 16-Bit External Data Interface Smart Media Standard ECC Generation GPIF (General Programmable Interface) ❐ Allows direct connection to most parallel interface ❐ Programmable waveform descriptors and configuration registers to define waveforms ❐ Supports multiple Ready and Control outputs ■ Integrated, Industry Standard Enhanced 8051 ❐ 48 MHz, 24 MHz, or 12 MHz CPU operation ❐ Four clocks per instruction cycle ❐ Three counter/timers ❐ Expanded interrupt system ❐ Two data pointers 1.8V Core Operation 1.8V to 3.3V I/O Operation Vectored USB Interrupts and GPIF/FIFO Interrupts Separate Data Buffers for Setup and Data Portions of a CONTROL Transfer Integrated I2C Controller, runs at 100 or 400 kHz Four Integrated FIFOs ❐ Integrated glue logic and FIFOs lower system cost ❐ Automatic conversion to and from 16-bit buses ❐ Master or slave operation ❐ Uses external clock or asynchronous strobes ❐ Easy interface to ASIC and DSP ICs Available in Industrial Temperature Grade Available in one Pb-free Package with up to 24 GPIOs ❐ 56-pin VFBGA (24 GPIOs) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Block Diagram 24 MHz Ext. XTAL High-performance microprocessor using standard tools with lower-power options MoBL-USB FX2LP18 VCC 12/24/48 MHz, Four Clocks/Cycle A dd re ss ( 16) / D ata Bu s (8) x20 PLL /0.5 /1.0 /2.0 8051 Core IC Master Additional IOs (24) 2 1.5K Connected for Full-Speed D+ USB 2.0 XCVR CY Smart USB 1.1/2.0 Engine 16 KB RAM Abundant IO GPIF ECC RDY (2) CTL (3) D– Integrated Full- and High-Speed XCVR General Programmable I/F To Baseband Processors/ Application Processors/ ASICS/DSPs Up to 96 MBytes/sec Burst Rate 4 KB FIFO 8/16 Enhanced USB Core Simplifies 8051 Code “Soft Configuration” Easy Firmware Changes FIFO and Endpoint Memory (Master or Slave Operation) Cypress Semiconductor Corporation Document # 001-06120 Rev *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 02, 2009 [+] Feedback CY7C68053 Cypress Semiconductor Corporation’s MoBL-USB™ FX2LP18 (CY7C68053) is a low voltage (1.8V) version of the EZ-USB® FX2LP (CY7C68013A), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. The ingenious architecture of MoBL-USB FX2LP18 results in data transfer rates of over 53 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low cost 8051 microcontroller in a package as small as a 56VFBGA (5 mm x 5 mm). Because it incorporates the USB 2.0 transceiver, the MoBL-USB FX2LP18 is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With MoBL-USB FX2LP18, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8 or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The MoBL-USB FX2LP18 is also referred to as FX2LP18 in this document. 3.2 8051 Microprocessor The 8051 microprocessor embedded in the FX2LP18 family has 256 bytes of register RAM, an expanded interrupt system, and three timer/counters. 3.2.1 8051 Clock Frequency FX2LP18 has an on-chip oscillator circuit that uses an external 24 MHz (±100-ppm) crystal with the following characteristics: ■ ■ ■ ■ Parallel resonant Fundamental mode 500 µW drive level 12 pF (5% tolerance) load capacitors An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz, as required by the transceiver/PHY; internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically. Figure 1. Crystal Configuration 24 MHz C1 12 pF C2 12 pF 2. Applications There are a wide variety of applications for the MoBL-USB FX2LP18. It is used in cell phones, smart phones, PDAs, and MP3 players, to name a few. The ‘Reference Designs’ section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. For more information, visit http://www.cypress.com. 20 × PLL 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four-layer FR4 PCA The CLKOUT pin, which can be tristated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency — 48, 24, or 12 MHz. 3.2.2 Special Function Registers Certain 8051 Special Function Register (SFR) addresses are populated to provide fast access to critical FX2LP18 functions. These SFR additions are shown in Table 1 on page 3. Bold type indicates non standard, enhanced 8051 registers. The two SFR rows that end with ‘0’ and ‘8’ contain bit-addressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in FX2LP18. Because of the faster and more efficient SFR addressing, the FX2LP18 I/O ports are not addressable in external RAM space (using the MOVX instruction). 3. Functional Overview The functionality of this chip is described in the sections below. 3.1 USB Signaling Speed FX2LP18 operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000. ■ ■ Full speed, with a signaling bit rate of 12 Mbps High speed, with a signaling bit rate of 480 Mbps FX2LP18 does not support the low speed signaling mode of 1.5 Mbps. Document # 001-06120 Rev *I Page 2 of 40 [+] Feedback CY7C68053 Table 1. Special Function Registers x 0 1 2 3 4 5 6 7 8 9 A B C D E F 8x IOA SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON SCON0 SBUF0 AUTOPTRH1 AUTOPTRL1 Reserved AUTOPTRH2 AUTOPTRL2 Reserved AUTOPTRSET-UP EP2468STAT EP24FIFOFLGS EP68FIFOFLGS GPIFSGLDATH GPIFSGLDATLX GPIFSGLDATLNOX simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0. Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device handles device requests over endpoint zero: if RENUM = 0, the Default USB Device handles device requests; if RENUM = 1, the firmware does. EP01STAT GPIFTRIG RCAP2L RCAP2H TL2 TH2 IE IP T2CON EICON EIE EIP 9x IOB EXIF MPAGE Ax IOC INT2CLR Bx IOD IOE OEA OEB OEC OED OEE Cx SCON1 SBUF1 Dx PSW Ex ACC Fx B 3.3 I2C™ Bus FX2LP18 supports the I2C bus as a master only at 100 or 400 KHz. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to either VCC or VCC_IO, even if no I2C device is connected. (Connecting to VCC_IO may be more convenient.) 3.4 Buses This 56-pin package has an 8- or 16-bit ‘FIFO’ bidirectional data bus, multiplexed on I/O ports B and D. 3.7 Bus-Powered Applications The FX2LP18 fully supports bus-powered designs by enumerating with less than 100 mA as required by the USB 2.0 specification. 3.5 USB Boot Methods During the power up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is 0xC2. If found, it boot-loads the EEPROM contents into internal RAM (0xC2 load). If no EEPROM is present, an external processor must emulate an I2C slave. The FX2LP18 does not enumerate using internally stored descriptors (for example, Cypress’s VID/PID/DID is not used for enumeration).[1] 3.8 Interrupt System The FX2LP18 interrupts are described in this section. 3.8.1 INT2 Interrupt Request and Enable Registers FX2LP18 implements an autovector feature for INT2. There are 27 INT2 (USB) vectors. See the MoBL-USB™ Technical Reference Manual (TRM) for more details. 3.8.2 USB Interrupt Autovectors The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that is normally required to identify the individual USB interrupt source, the FX2LP18 provides a second level of interrupt vectoring, called ‘Autovectoring.’ When a USB interrupt is asserted, the FX2LP18 pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a ‘jump’ instruction to the USB interrupt service routine. The FX2LP18 jump instruction is encoded as shown in Table 2 on page 4. 3.6 ReNumeration™ Because the FX2LP18’s configuration is soft, one chip can take on the identities of multiple distinct USB devices. When first plugged into USB, the FX2LP18 enumerates automatically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP18 enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration™, happens instantly when the device is plugged in, with no hint that the initial download step has occurred. Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To Note 1. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly. Document # 001-06120 Rev *I Page 3 of 40 [+] Feedback CY7C68053 If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP18 substitutes its INT2VEC byte. Therefore, if the high byte (‘page’) of a jump-table address is preloaded at Table 2. INT2 USB Interrupts Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INT2VEC Value 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C EP2ISOERR EP4ISOERR EP6ISOERR EP8ISOERR EP0PING EP1PING EP2PING EP4PING EP6PING EP8PING ERRLIMIT EP0-IN EP0-OUT EP1-IN EP1-OUT EP2 EP4 EP6 EP8 IBN SUDAV SOF SUTOK SUSPEND USB RESET HISPEED EP0ACK Source location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page. Notes Setup data available Start of frame (or microframe) Setup token received USB suspend request Bus reset Entered high speed operation FX2LP18 ACK’d the control handshake Reserved EP0-IN ready to be loaded with data EP0-OUT has USB data EP1-IN ready to be loaded with data EP1-OUT has USB data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN-Bulk-NAK (any IN endpoint) Reserved EP0 OUT was pinged and it NAK’d EP1 OUT was pinged and it NAK’d EP2 OUT was pinged and it NAK’d EP4 OUT was pinged and it NAK’d EP6 OUT was pinged and it NAK’d EP8 OUT was pinged and it NAK’d Bus errors exceeded the programmed limit Reserved Reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error Document # 001-06120 Rev *I Page 4 of 40 [+] Feedback CY7C68053 Figure 2. Reset Timing Plots RESET# RESET# VIL 1.8V 1.62V VCC 0V TRESET Power on Reset VIL 1.8V VCC 0V TRESET Powered Reset 3.9 Reset and Wakeup The reset and wakeup pins are described in detail in this section. 3.9.1 Reset Pin The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C68053, the reset period must allow for the stabilization of the crystal and the PLL. This reset period must be approximately 5 ms after VCC has reached 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 μs after VCC has reached 3.0V[2]. Figure 2 shows a power on reset condition and a reset applied during operation. A power on reset is defined as the time reset is asserted while power is being applied to the circuit. A powered reset is defined as a reset in which the FX2LP18 has previously been powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation, which can be found on the Cypress web site. For more information on reset implementation for the MoBL-USB family of products, visit the Cypress web site at http://www.cypress.com. Table 3. Reset Timing Values Condition Power on reset with crystal Power on reset with external clock Powered reset 3.9.2 Wakeup Pins The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscillator restarts, after the PLL stabilizes, and then the 8051 receives a wakeup interrupt. This applies whether or not FX2LP18 is connected to the USB. TRESET 5 ms 200 μs + clock stability time 200 μs The FX2LP18 exits the power down (USB suspend) state using one of the following methods: ■ USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP18 and initiate a wakeup) External logic asserts the WAKEUP pin External logic asserts the PA3/WU2 pin ■ ■ The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. Note that WAKEUP is active LOW by default. 3.9.3 Lowering Suspend Current Good design practices for CMOS circuits dictate that any unused input pins must not be floating between VIL and VIH. Floating input pins will not damage the chip, but can substantially increase suspend current. To achieve the lowest suspend current, confiigure unused port pins as outputs. Connect unused input pins to ground. Some examples of pins that need attention during suspend are: ■ Port pins. For Port A, B, D pins, take extra care in shared bus situations. ❐ Connect completely unused pins to VCC_IO or GND. ❐ In a single-master system, the firmware must output enable all the port pins and drive them high or low, before FX2LP18 enters the suspend state. ❐ In a multi-master system (FX2LP18 and another processor sharing a common data bus), when FX2LP18 is suspended, the external master must drive the pins high or low. The external master must not let the pins float. CLKOUT. If CLKOUT is not used, it must be tri-stated during normal operation, but driven during suspend. IFCLK, RDY0, RDY1. These pins must be pulled to VCC_IO or GND or driven by another chip. ■ ■ Note 2. If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 μs. Document # 001-06120 Rev *I Page 5 of 40 [+] Feedback CY7C68053 ■ ■ CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be pulled to VCC_IO or GND or driven by another chip. RESET#, WAKEUP#. These pins must be pulled to VCC_IO or GND or driven by another chip during suspend. 3.11 Register Addresses Figure 4. Register Address Memory FFFF 4 kBytes EP2-EP8 buffers (8 x 512) Figure 3. FX2LP18 Internal Code Memory FFFF 7.5 kBytes USB regs and 4K FIFO buffers E200 E1FF 0.5 kBytes RAM E000 Data F000 EFFF 2 kBytes RESERVED E800 E7FF E7C0 E7BF E780 E77F E740 64 Bytes EP1IN 64 Bytes EP1OUT 64 Bytes EP0 IN/OUT 64 Bytes RESERVED 8051 Addressable Registers (512) Reserved (128) 128 Bytes GPIF Waveforms Reserved (512) . . . 3FFF E73F E700 E6FF E500 E4FF E480 E47F 16 kBytes RAM Code and Data E400 E3FF E200 E1FF 512 Bytes 8051 xdata RAM E000 0000 3.12 Endpoint RAM This section describes the FX2LP18 Endpoint RAM. 3.10 Program/Data RAM This section describes the FX2LP18 RAM. 3.10.1 Size The FX2LP18 has 16 kBytes of internal program/data RAM. No USB control registers appear in this space. Memory maps are shown in Figure 3 and Figure 4. 3.10.2 Internal Code Memory This mode implements the internal 16-kByte block of RAM (starting at 0) as combined code and data memory. Only the internal 16 kBytes and scratch pad 0.5 kBytes RAM spaces have the following access: ■ ■ ■ ■ 3.12.1 Size ■ ■ 3 × 64 bytes (Endpoints 0, 1) 8 × 512 bytes (Endpoints 2, 4, 6, 8) 3.12.2 Organization ■ ■ ■ ■ ■ ■ EP0 Bidirectional endpoint zero, 64-byte buffer EP1IN, EP1OUT 64-byte buffers: bulk or interrupt EP2, 4, 6, 8 Eight 512-byte buffers: bulk, interrupt, or isochronous. EP4 and EP8 can be double buffered, while EP2 and 6 can be double, triple, or quad buffered. For high speed endpoint configuration options, see Figure 5 on page 7. USB download USB upload Setup data pointer I2C interface boot load 3.12.3 Setup Data Buffer A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer. Document # 001-06120 Rev *I Page 6 of 40 [+] Feedback CY7C68053 3.12.4 Endpoint Configurations (High Speed Mode) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any one of the 12 configurations shown in the vertical columns of Figure 5. When operating in full speed BULK mode only the first 64 bytes of each buffer are used. For example, in high speed the maximum packet size is 512 bytes, but in full speed it is 64 bytes. Even though a buffer is configured to be a 512 byte buffer, in full speed only the first 64 bytes are used. The unused endpoint buffer space is not available for other operations. An example endpoint configuration is: EP2–1024 double buffered; EP6–512 quad buffered (column 8). Figure 5. Endpoint Configuration EP0 IN&OUT EP1 IN EP1 OUT 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 EP2 512 512 EP2 512 512 EP2 512 512 EP2 512 512 EP2 512 512 EP2 512 512 EP2 1024 EP2 1024 EP2 1024 EP2 512 EP2 EP2 1024 1024 512 512 EP4 512 512 EP4 512 512 EP4 512 512 512 512 512 512 512 512 1024 1024 1024 EP6 512 1024 1024 EP6 512 512 EP6 512 512 EP6 1024 EP6 512 512 EP6 512 512 EP6 1024 EP6 512 512 EP6 512 512 EP6 1024 512 512 1024 1024 1024 EP8 512 512 512 512 1024 EP8 512 512 512 512 1024 EP8 512 512 512 512 1024 EP8 512 512 EP8 512 512 1024 1 2 3 4 5 6 7 8 9 10 11 12 3.12.5 Default Full Speed Alternate Settings Table 4. Default Full Speed Alternate Settings[3, 4] Alternate Setting ep0 ep1out ep1in ep2 ep4 ep6 ep8 0 64 0 0 0 0 0 0 64 64 bulk 64 bulk 64 bulk out (2×) 64 bulk out (2×) 64 bulk in (2×) 64 bulk in (2×) 1 64 64 int 64 int 64 int out (2×) 64 bulk out (2×) 64 int in (2×) 64 bulk in (2×) 2 64 64 int 64 int 64 iso out (2×) 64 bulk out (2×) 64 iso in (2×) 64 bulk in (2×) 3 Notes 3. ‘0’ means ‘not implemented.’ 4. ‘2×’ means ‘double buffered.’ Document # 001-06120 Rev *I Page 7 of 40 [+] Feedback CY7C68053 3.12.6 Default High Speed Alternate Settings Table 5. Default High Speed Alternate Settings[3, 4] Alternate Setting ep0 ep1out ep1in ep2 ep4 ep6 ep8 0 64 0 0 0 0 0 0 64 512 bulk[5] 512 bulk[5] 512 bulk out (2×) 512 bulk out (2×) 512 bulk in (2×) 512 bulk in (2×) 1 64 64 int 64 int 512 int out (2×) 512 bulk out (2×) 512 int in (2×) 512 bulk in (2×) 2 64 64 int 64 int 512 iso out (2×) 512 bulk out (2×) 512 iso in (2×) 512 bulk in (2×) 3 3.13 External FIFO Interface The architecture, control signals, and clock rates are presented in this section. 3.13.1 Architecture The FX2LP18 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags). In operation, some of the eight RAM blocks fill or empty from the SIE while the others are connected to the I/O transfer logic. The transfer logic takes two forms: the GPIF for internally generated control signals or the slave FIFO interface for externally controlled transfers. 3.13.2 Master/Slave Control Signals The FX2LP18 endpoint FIFOs are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is instantaneous, giving zero transfer time between ‘USB FIFOs’ and ‘Slave FIFOs’. Because they are physically the same memory, no bytes are actually transferred between buffers. At any given time, some RAM blocks are filling and emptying with USB data under SIE control, while other RAM blocks are available to the 8051, the I/O control unit, or both. The RAM blocks operate as single port in the USB domain, and dual port in the 8051-I/O domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown. The I/O control unit implements either an internal master (M for master) or external master (S for Slave) interface. In Master (M) mode, the GPIF internally controls FIFOADR[1:0] to select a FIFO. The two ready (RDY) pins can be used as flag inputs from an external FIFO or other logic. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 megabytes/s (48 MHz IFCLK with 16-bit interface). In Slave (S) mode, the FX2LP18 accepts either an internally derived clock or externally supplied clock (IFCLK, maximum frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal (SLOE) enables data of the selected width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE, and PKTEND are gated by the signal SLCS#. 3.13.3 GPIF and FIFO Clock Rates An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off. Another bit within the IFCONFIG register inverts the IFCLK signal whether internally or externally sourced. 3.14 GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user programmable finite state machine. It allows the CY7C68053 to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, parallel printer port, and Utopia. The GPIF has three programmable control outputs (CTL), and two general purpose ready inputs.The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, and so on. A sequence of the GPIF vectors makes up a single waveform that is executed to perform the desired data move between the FX2LP18 and the external device. Note 5. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. Nnever transfer packets larger than 64 bytes to EP1. Document # 001-06120 Rev *I Page 8 of 40 [+] Feedback CY7C68053 3.14.1 Three Control OUT Signals The 56-pin package brings out three of these signals, CTL0–CTL2. The 8051 programs the GPIF unit to define the CTL waveforms. CTLx waveform edges can be programmed to make transitions as fast as once per clock cycle (20.8 ns using a 48 MHz clock). 3.14.2 Two Ready IN Signals The FX2LP18 package brings out all two Ready inputs (RDY0–RDY1). The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. 3.14.3 Long Transfer Mode In master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 232 transactions. The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction. 3.16 USB Uploads and Downloads The core has the ability to directly edit the data contents of the internal 16-kByte RAM and of the internal 512-byte scratch pad RAM using a vendor-specific command. This capability is normally used when ‘soft’ downloading user code and is available only to and from internal RAM, only when the 8051 is held in reset. The available RAM spaces are 16 kBytes from 0x0000–0x3FFF (code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad data RAM).[7] 3.17 Autopointer Access FX2LP18 provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. The autopointers are available in external FX2LP18 registers, under control of a mode bit (AUTOPTRSET-UP.0). Using the external FX2LP18 autopointer access (at 0xE67B – 0xE67C) allows the autopointer to access all RAM. Also, the autopointers can point to any FX2LP18 register or endpoint buffer space. 3.15 ECC Generation[6] 3.18 I2C Controller FX2LP18 has one I2C port that is driven by two internal controllers. One controller automatically operates at boot time to load the VID/PID/DID, configuration byte, and firmware. The second controller is used by the 8051, once running, to control external I2C devices. The I2C port operates in master mode only. 3.18.1 I2C Port Pins The I2C pins SCL and SDA must have external 2.2K ohm pull up resistors even if no EEPROM is connected to the FX2LP18. The value of the pull up resistors required may vary, depending on the combination of VCC_IO and the supply used for the EEPROM. The pull up resistors used must be such that when the EEPROM pulls SDA low, the voltage level meets the VIL specification of the FX2LP18. For example, if the EEPROM runs off a 3.3V supply and VCC_IO is 1.8V, the pull up resistors recommended are 10K ohm. This requirement may also vary depending on the devices being run on the I2C pins. Refer to the I2C specifications for details. External EEPROM device address pins must be configured properly. See Table 6 on page 10 for configuring the device address pins. If no EEPROM is connected to the I2C port, EEPROM emulation is required by an external processor. This is because the FX2LP18 comes out of reset with the DISCON bit set, so the device will not enumerate without an EEPROM (C2 load) or EEPROM emulation. The MoBL-USB can calculate Error Correcting Codes (ECCs) on data that passes across its GPIF or Slave FIFO interfaces. There are two ECC configurations: two ECCs, each calculated over 256 bytes (SmartMedia Standard) and one ECC calculated over 512 bytes. The ECC can correct any 1-bit error or detect any 2-bit error. 3.15.1 ECC Implementation The two ECC configurations are selected by the ECCM bit. 3.15.1.1 ECCM = 0 Two 3-byte ECCs are each calculated over a 256-byte block of data. This configuration conforms to the SmartMedia Standard. This configuration writes any value to ECCRESET, then passes data across the GPIF or Slave FIFO interface. The ECC for the first 256 bytes of data is calculated and stored in ECC1. The ECC for the next 256 bytes is stored in ECC2. After the second ECC is calculated, the values in the ECCx registers do not change until ECCRESET is written again, even if more data is subsequently passed across the interface. 3.15.1.2 ECCM = 1 One 3-byte ECC is calculated over a 512-byte block of data. This configuration writes any value to ECCRESET then passes data across the GPIF or Slave FIFO interface. The ECC for the first 512 bytes of data is calculated and stored in ECC1; ECC2 is unused. After the ECC is calculated, the value in ECC1 does not change until ECCRESET is written again, even if more data is subsequently passed across the interface. Notes 6. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation. 7. After the data is downloaded from the host, a ‘loader’ can execute from internal RAM in order to transfer downloaded data to external memory. Document # 001-06120 Rev *I Page 9 of 40 [+] Feedback CY7C68053 Table 6. Strap Boot EEPROM Address Lines to These Values Bytes 16 128 256 4K 8K 16K Example EEPROM 24AA00 24AA01 24AA02 24AA32 24AA64 24AA128 [8] A2 N/A 0 0 0 0 0 A1 N/A 0 0 0 0 0 A0 N/A 0 0 1 1 1 program/data. The available RAM spaces are 16 kBytes from 0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051 is reset. I2C interface boot loads only occur after power on reset. 3.18.3 I2C Interface General Purpose Access The 8051 can control peripherals connected to the I2C bus using the I2CTL and I2DAT registers. FX2LP18 provides I2C master control only, it is never an I2C slave. 4. Pin Assignments Figure 6 identifies all signals for the package. It is followed by the pin diagram.Three modes are available: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power on default configuration. 3.18.2 I2C Interface Boot Load Access At power on reset the I2C interface boot loader loads the VID/PID/DID and configuration bytes and up to 16 kBytes of Figure 6. Signals Port PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GPIF Master FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] RDY0 RDY1 CTL0 CTL1 CTL2 Slave FIFO FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR FLAGA FLAGB FLAGC INT0#/PA0 INT1#/PA1 SLOE WU2/PA3 FIFOADR0 FIFOADR1 PKTEND PA7/FLAGD/SLCS# XTALIN XTALOUT RESET# WAKEUP# SCL SDA IFCLK CLKOUT DPLUS DMINUS INT0#/PA0 INT1#/PA1 PA2 WU2/PA3 PA4 PA5 PA6 PA7 INT0#/PA0 INT1#/PA1 PA2 WU2/PA3 PA4 PA5 PA6 PA7 Note 8. This EEPROM does not have address pins. Document # 001-06120 Rev *I Page 10 of 40 [+] Feedback CY7C68053 Figure 7. CY7C68053 56-pin VFBGA Pin Assignment - Top View 1 2 3 4 5 6 7 8 A 1A 2A 3A 4A 5A 6A 7A 8A B 1B 2B 3B 4B 5B 6B 7B 8B C 1C 2C 3C 4C 5C 6C 7C 8C D 1D 2D 7D 8D E 1E 2E 7E 8E F 1F 2F 3F 4F 5F 6F 7F 8F G 1G 2G 3G 4G 5G 6G 7G 8G H 1H 2H 3H 4H 5H 6H 7H 8H Document # 001-06120 Rev *I Page 11 of 40 [+] Feedback CY7C68053 4.1 CY7C68053 Pin Descriptions Table 7. FX2LP18 Pin Descriptions [9] 56 VFBGA 2D Name AVCC Type Power Default N/A Description Analog VCC. Connect this pin to 3.3V power source. This signal provides power to the analog section of the chip. Provide an appropriate bulk/bypass capacitance for this supply rail. Analog VCC. Connect this pin to 3.3V power source. This signal provides power to the analog section of the chip. Analog Ground. Connect this pin to ground with as short a path as possible. Analog Ground. Connect to this pin ground with as short a path as possible. USB D– Signal. Connect this pin to the USB D– signal. USB D+ Signal. Connect this pin to the USB D+ signal. Active LOW Reset. This pin resets the entire chip. See Reset and Wakeup on page 5 for details. Crystal Input. Connect this signal to a 24 MHz parallel resonant, fundamental mode crystal and load capacitor to GND. It is also correct to drive XTALIN with an external 24 MHz square wave derived from another clock source. Crystal Output. Connect this signal to a 24 MHz parallel resonant, fundamental mode crystal and load capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open. CLKOUT. 12, 24, or 48 MHz clock, phase locked to the 24 MHz input clock. The 8051 defaults to 12 MHz operation. The 8051 may tri-state this output by setting CPUCS.1 = 1. Multiplexed pin whose function is selected by PORTACFG.0 PA0 is a bidirectional I/O port pin. INT0# is the active LOW 8051 INT0 interrupt input signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0). Multiplexed pin whose function is selected by PORTACFG.1 PA1 is a bidirectional I/O port pin. INT1# is the active LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). Multiplexed pin whose function is selected by two bits: IFCONFIG[1:0]. PA2 is a bidirectional I/O port pin. SLOE is an input-only output enable with programmable polarity (FIFOPINPOLAR.4) for the slave FIFO’s connected to FD[7:0] or FD[15:0]. Multiplexed pin whose function is selected by: WAKEUP.7 and OEA.3 PA3 is a bidirectional I/O port pin. WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Asserting this pin inhibits the chip from suspending, if WU2EN = 1. 1D 2F 1F 1E 2E 8B 1C AVCC AGND AGND DMINUS DPLUS RESET# XTALIN Power Ground Ground I/O/Z I/O/Z Input Input N/A N/A N/A Z Z N/A N/A 2C XTALOUT Output N/A 2B CLKOUT O/Z 12 MHz Port A 8G PA0 or INT0# I/O/Z I (PA0) 6G PA1 or INT1# I/O/Z I (PA1) 8F PA2 or SLOE I/O/Z I (PA2) 7F PA3 or WU2 I/O/Z I (PA3) Note 9. Do not leave unused inputs floating. Tie either HIGH or LOW as appropriate. Only pull outputs up or down to ensure signals at power up and in standby. Do not drive any pins while the device is powered down. Document # 001-06120 Rev *I Page 12 of 40 [+] Feedback CY7C68053 Table 7. FX2LP18 Pin Descriptions (continued)[9] 56 VFBGA 6F Name PA4 or FIFOADR0 Type I/O/Z Default I (PA4) Description Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA4 is a bidirectional I/O port pin. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits. PA6 is a bidirectional I/O port pin. PKTEND is an input that commits the FIFO packet data to the endpoint and whose polarity is programmable using FIFOPINPOLAR.5. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and PORTACFG.7 bits. PA7 is a bidirectional I/O port pin. FLAGD is a programmable slave FIFO output status flag signal. SLCS# gates all other slave FIFO enable/strobes Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB0 is a bidirectional I/O port pin. FD[0] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB1 is a bidirectional I/O port pin. FD[1] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB2 is a bidirectional I/O port pin. FD[2] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB5 is a bidirectional I/O port pin. FD[5] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB6 is a bidirectional I/O port pin. FD[6] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected IFCONFIG[1:0]. PB7 is a bidirectional I/O port pin. FD[7] is the bidirectional FIFO/GPIF data bus. 8C PA5 or FIFOADR1 I/O/Z I (PA5) 7C PA6 or PKTEND I/O/Z I (PA6) 6C PA7 or FLAGD or SLCS# I/O/Z I (PA7) Port B 3H PB0 or FD[0] PB1 or FD[1] PB2 or FD[2] PB3 or FD[3] PB4 or FD[4] PB5 or FD[5] PB6 or FD[6] PB7 or FD[7] I/O/Z I (PB0) I (PB1) I (PB2) I (PB3) I (PB4) I (PB5) I (PB6) I (PB7) 4F I/O/Z 4H I/O/Z 4G I/O/Z 5H I/O/Z 5G I/O/Z 5F I/O/Z 6H I/O/Z Document # 001-06120 Rev *I Page 13 of 40 [+] Feedback CY7C68053 Table 7. FX2LP18 Pin Descriptions (continued)[9] 56 VFBGA PORT D 8A PD0 or FD[8] PD1 or FD[9] PD2 or FD[10] PD3 or FD[11] PD4 or FD[12] PD5 or FD[13] PD6 or FD[14] PD7 or FD[15] RDY0 or SLRD I/O/Z I (PD0) I (PD1) I (PD2) I (PD3) I (PD4) I (PD5) I (PD6) I (PD7) N/A Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[10] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[11] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[12] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[13] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[14] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[15] is the bidirectional FIFO/GPIF data bus. Multiplexed pin whose function is selected by IFCONFIG[1:0]. RDY0 is a GPIF input signal. SLRD is the input only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7:0] or FD[15:0]. Multiplexed pin whose function is selected by IFCONFIG[1:0]. RDY1 is a GPIF input signal. SLWR is the input only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7:0] or FD[15:0]. Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL0 is a GPIF control output. FLAGA is a programmable slave FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL1 is a GPIF control output. FLAGB is a programmable slave FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins. Multiplexed pin whose function is selected IFCONFIG[1:0]. CTL2 is a GPIF control output. FLAGC is a programmable slave FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. Interface clock, used to synchronous clock data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be configured to output 30 or 48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG.4 =1. Name Type Default Description 7A I/O/Z 6B I/O/Z 6A I/O/Z 3B I/O/Z 3A I/O/Z 3C I/O/Z 2A I/O/Z 1A Input 1B RDY1 or SLWR Input N/A 7H CTL0 or FLAGA O/Z H 7G CTL1 or FLAGB O/Z H 8H CTL2 or FLAGC O/Z H 2G IFCLK I/O/Z Z Document # 001-06120 Rev *I Page 14 of 40 [+] Feedback CY7C68053 Table 7. FX2LP18 Pin Descriptions (continued)[9] 56 VFBGA 7B Name WAKEUP Type Input Default N/A Description USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP asserted inhibits the MoBL-USB® chip from suspending. This pin has programmable polarity (WAKEUP.4). Clock for the I2C interface. Connect to VCC_IO or VCC with a 2.2K–10K pull up resistor. (An I2C peripheral is required.) Data for the I2C interface. Connect to VCC_IO or VCC with a 2.2K–10K pull up resistor. (An I2C peripheral is required.) VCC. Connect this pin to 1.8V to 3.3V power source. Provide the appropriate bulk and bypass capacitance for this supply rail. VCC. Connect this pin to 1.8V to 3.3V power source. VCC. Connect this pin to 1.8V to 3.3V power source. VCC. Connect this pin to 1.8V to 3.3V power source. VCC. Connect this pin to 1.8V power source. (Supplies power to internal digital 1.8V circuits.) Provide the appropriate bulk and bypass capacitance for this supply rail. VCC. Connect this pin to 1.8V power source. (Supplies power to internal analog 1.8V circuits.) Ground. Ground. Ground. Ground. Ground. Ground. Ground. 3F 3G SCL SDA OD OD Z Z 5A 5B 7E 8E 5C VCC_IO VCC_IO VCC_IO VCC_IO VCC_D Power Power Power Power Power N/A N/A N/A N/A N/A 1G 1H 2H 4A 4B 4C 7D 8D VCC_A GND GND GND GND GND GND GND Power Ground Ground Ground Ground Ground Ground Ground N/A N/A N/A N/A N/A N/A N/A N/A Document # 001-06120 Rev *I Page 15 of 40 [+] Feedback CY7C68053 5. Register Summary FX2LP18 register bit definitions are described in the MoBL-USB FX2LP18 TRM in greater detail. Table 8. FX2LP18 Register Summary Hex E400 E480 E50D E600 E601 E602 E603 E604 E605 E606 E607 E608 E609 E60A E60B E60C Size Name Description GPIF Waveform Memories 128 WAVEDATA GPIF Waveform descriptor 0, 1, 2, 3 data 128 Reserved GENERAL CONFIGURATION GPCR2 General Purpose Configuration Register 2 1 CPUCS CPU Control and Status 1 IFCONFIG Interface Configuration (Ports, GPIF, Slave FIFOs) [10] 1 PINFLAGSAB Slave FIFO FLAGA and FLAGB pin configuration 1 PINFLAGSCD[10] Slave FIFO FLAGC and FLAGD pin configuration 1 FIFORESET[10] Restore FIFOs to default state 1 BREAKPT Breakpoint control 1 BPADDRH Breakpoint address H 1 BPADDRL Breakpoint address L 1 Reserved Reserved 1 FIFOPINPOLAR[10] Slave FIFO interface pins polarity 1 REVID Chip revision 1 1 3 E610 E611 E612 E613 E614 E615 E618 E619 E61A E61B E61C E620 E621 E622 E623 E624 E625 E626 E627 E628 E629 E62A E62B 1 1 1 1 1 1 2 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 REVCTL[10] Chip revision control UDMA GPIFHOLDAMOUNT MSTB hold time (for UDMA) Reserved ENDPOINT CONFIGURATION EP1OUTCFG Endpoint 1-OUT configuration EP1INCFG Endpoint 1-IN configuration EP2CFG Endpoint 2 configuration EP4CFG Endpoint 4 configuration EP6CFG Endpoint 6 configuration EP8CFG Endpoint 8 configuration Reserved EP2FIFOCFG[10] Endpoint 2/Slave FIFO configuration [10] EP4FIFOCFG Endpoint 4/Slave FIFO configuration EP6FIFOCFG[10] Endpoint 6/Slave FIFO configuration [10] EP8FIFOCFG Endpoint 8/Slave FIFO configuration Reserved EP2AUTOINLENH[10 Endpoint 2 AUTOIN packet length H EP2AUTOINLENL[10] Endpoint 2 AUTOIN packet length L EP4AUTOINLENH[10 Endpoint 4 AUTOIN ] packet length H EP4AUTOINLENL[10] Endpoint 4 AUTOIN packet length L EP6AUTOINLENH[10 Endpoint 6 AUTOIN ] packet length H EP6AUTOINLENL[10] Endpoint 6 AUTOIN packet length L EP8AUTOINLENH[10 Endpoint 8 AUTOIN ] packet length H EP8AUTOINLENL[10] Endpoint 8 AUTOIN packet length L ECCCFG ECC Configuration ECCRESET ECC Reset ECC1B0 ECC1 Byte 0 address ECC1B1 ECC1 Byte 1 address b7 D7 b6 D6 b5 D5 b4 D4 b3 D3 b2 D2 b1 D1 b0 D0 Default Access xxxxxxxx RW Reserved 0 IFCLKSRC FLAGB3 FLAGD3 NAKALL 0 A15 A7 0 0 rv7 0 0 Reserved 0 3048MHZ FLAGB2 FLAGD2 0 0 A14 A6 0 0 rv6 0 0 FULL_SPEED Reserved _ONLY PORTCSTB CLKSPD1 CLKSPD0 IFCLKOE IFCLKPOL ASYNC FLAGB1 FLAGD1 0 0 A13 A5 0 PKTEND rv5 0 0 FLAGB0 FLAGD0 0 0 A12 A4 0 SLOE rv4 0 0 FLAGA3 FLAGC3 EP3 BREAK A11 A3 0 SLRD rv3 0 0 Reserved Reserved CLKINV GSTATE FLAGA2 FLAGC2 EP2 BPPULSE A10 A2 0 SLWR rv2 0 0 Reserved CLKOE IFCFG1 FLAGA1 FLAGC1 EP1 BPEN A9 A1 0 EF rv1 dyn_out Reserved 8051RES IFCFG0 FLAGA0 FLAGC0 EP0 0 A8 A0 0 FF rv0 enh_pkt 00000000 R 00000010 rrbbbbbr 10000000 RW 00000000 RW 00000000 RW xxxxxxxx W 00000000 rrrrbbbr xxxxxxxx RW xxxxxxxx RW 00000000 rrrrrrbb 00000000 rrbbbbbb RevA R 00000001 00000000 rrrrrrbb HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb VALID VALID VALID VALID VALID VALID 0 0 0 0 0 0 DIR DIR DIR DIR INFM1 INFM1 INFM1 INFM1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 OEP1 OEP1 OEP1 OEP1 TYPE0 TYPE0 TYPE0 TYPE0 TYPE0 TYPE0 AUTOOUT AUTOOUT AUTOOUT AUTOOUT 0 0 SIZE 0 SIZE 0 AUTOIN AUTOIN AUTOIN AUTOIN 0 0 0 0 0 0 ZEROLENIN ZEROLENIN ZEROLENIN ZEROLENIN 0 0 BUF1 0 BUF1 0 0 0 0 0 0 0 BUF0 0 BUF0 0 10100000 brbbrrrr 10100000 brbbrrrr 10100010 bbbbbrbb 10100000 bbbbrrrr 11100010 bbbbbrbb 11100000 bbbbrrrr WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb 0 PL7 0 PL7 0 PL7 0 PL7 0 x LINE15 LINE7 0 PL6 0 PL6 0 PL6 0 PL6 0 x LINE14 LINE6 0 PL5 0 PL5 0 PL5 0 PL5 0 x LINE13 LINE5 0 PL4 0 PL4 0 PL4 0 PL4 0 x LINE12 LINE4 0 PL3 0 PL3 0 PL3 0 PL3 0 x LINE11 LINE3 PL10 PL2 0 PL2 PL10 PL2 0 PL2 0 x LINE10 LINE2 PL9 PL1 PL9 PL1 PL9 PL1 PL9 PL1 0 x LINE9 LINE1 PL8 PL0 PL8 PL0 PL8 PL0 PL8 PL0 ECCM x LINE8 LINE0 00000010 rrrrrbbb 00000000 RW 00000010 rrrrrrbb 00000000 RW 00000010 rrrrrbbb 00000000 RW 00000010 rrrrrrbb 00000000 RW 00000000 rrrrrrrb 00000000 W 00000000 R 00000000 R Note 10. Read and writes to these registers may require synchronization delay, see MoBL-USB FX2LP18 Technical Reference Manual for ‘Synchronization Delay.’ Document # 001-06120 Rev *I Page 16 of 40 [+] Feedback CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name E62C 1 ECC1B2 E62D 1 ECC2B0 E62E 1 ECC2B1 E62F E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.S E640 E641 E642 E643 E644 E648 E649 E650 E651 E652 E653 E654 E655 E656 E657 E658 E659 E65A E65B E65C E65D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 4 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ECC2B2 EP2FIFOPFH[10] EP2FIFOPFH[10] EP2FIFOPFL[10] EP2FIFOPFL[10] EP4FIFOPFH[10] EP4FIFOPFH[10] EP4FIFOPFL[10] EP4FIFOPFL[10] EP6FIFOPFH[10] EP6FIFOPFH[10] EP6FIFOPFL[10] EP6FIFOPFL[10] EP8FIFOPFH[10] EP8FIFOPFH[10] EP8FIFOPFL[10] EP8FIFOPFL[10] Reserved EP2ISOINPKTS EP4ISOINPKTS EP6ISOINPKTS EP8ISOINPKTS Reserved INPKTEND[10] OUTPKTEND[10] INTERRUPTS EP2FIFOIE[10] EP2FIFOIRQ EP4FIFOIE [10,11] Description ECC1 Byte 2 address ECC2 Byte 0 address ECC2 Byte 1 address ECC2 Byte 2 address Endpoint 2/Slave FIFO programmable flag H Endpoint 2/Slave FIFO programmable flag H Endpoint 2/Slave FIFO programmable flag L Endpoint 2/Slave FIFO programmable flag L Endpoint 4/Slave FIFO programmable flag H Endpoint 4/Slave FIFO programmable flag H Endpoint 4/Slave FIFO programmable flag L Endpoint 4/Slave FIFO programmable flag L Endpoint 6/Slave FIFO programmable flag H Endpoint 6/Slave FIFO programmable flag H Endpoint 6/Slave FIFO programmable flag L Endpoint 6/Slave FIFO programmable flag L Endpoint 8/Slave FIFO programmable flag H Endpoint 8/Slave FIFO programmable flag H Endpoint 8/Slave FIFO programmable flag L Endpoint 8/Slave FIFO programmable flag L EP2 (if ISO) IN packets per frame (1-3) EP4 (if ISO) IN packets per frame (1-3) EP6 (if ISO) IN packets per frame (1-3) EP8 (if ISO) IN packets per frame (1-3) Force IN packet end Force OUT packet end Endpoint 2 Slave FIFO flag interrupt enable Endpoint 2 Slave FIFO flag interrupt request Endpoint 4 Slave FIFO flag interrupt enable Endpoint 4 Slave FIFO flag interrupt request Endpoint 6 Slave FIFO flag interrupt enable Endpoint 6 Slave FIFO flag interrupt request Endpoint 8 Slave FIFO flag interrupt enable Endpoint 8 Slave FIFO flag interrupt request IN-BULK-NAK interrupt enable IN-BULK-NAK interrupt request Endpoint Ping-NAK/IBN interrupt enable Endpoint Ping-NAK/IBN interrupt request USB interrupt enables USB interrupt requests b7 COL5 LINE15 LINE7 COL5 DECIS DECIS PFC7 IN:PKTS[1] OUT:PFC7 DECIS DECIS PFC7 IN: PKTS[1] OUT:PFC7 DECIS DECIS PFC7 IN:PKTS[1] OUT:PFC7 DECIS DECIS PFC7 IN: PKTS[1] OUT:PFC7 AADJ AADJ AADJ AADJ b6 COL4 LINE14 LINE6 COL4 PKTSTAT PKTSTAT PFC6 IN:PKTS[0] OUT:PFC6 PKTSTAT PKTSTAT PFC6 IN: PKTS[0] OUT:PFC6 PKTSTAT PKTSTAT PFC6 IN:PKTS[0] OUT:PFC6 PKTSTAT PKTSTAT PFC6 IN: PKTS[0] OUT:PFC6 0 0 0 0 b5 COL3 LINE13 LINE5 COL3 IN:PKTS[2] OUT:PFC12 OUT:PFC12 PFC5 PFC5 0 0 PFC5 PFC5 IN:PKTS[2] OUT:PFC12 OUT:PFC12 PFC5 PFC5 0 0 PFC5 PFC5 b4 COL2 LINE12 LINE4 b3 COL1 LINE11 LINE3 b2 COL0 LINE10 LINE2 COL0 0 0 PFC2 PFC2 0 0 PFC2 PFC2 0 0 PFC2 PFC2 0 0 PFC2 PFC2 b1 LINE17 LINE9 LINE1 0 PFC9 PFC9 PFC1 PFC1 0 0 PFC1 PFC1 PFC9 PFC9 PFC1 PFC1 0 0 PFC1 PFC1 b0 LINE16 LINE8 LINE0 0 PFC8 Default Access 00000000 R 00000000 R 00000000 R 00000000 R 10001000 bbbbbrbb COL2 COL1 IN:PKTS[1] IN:PKTS[0] OUT:PFC11 OUT:PFC10 OUT:PFC11 OUT:PFC10 PFC4 PFC4 IN: PKTS[1] OUT:PFC10 OUT:PFC10 PFC4 PFC4 PFC3 PFC3 IN: PKTS[0] OUT:PFC9 OUT:PFC9 PFC3 PFC3 IN:PKTS[2] 10001000 bbbbbrbb OUT:PFC8 PFC0 00000000 RW PFC0 PFC8 PFC8 PFC0 PFC0 PFC8 00000000 RW 10001000 bbrbbrrb 10001000 bbrbbrrb 00000000 RW 00000000 RW 00001000 bbbbbrbb IN:PKTS[1] IN:PKTS[0] OUT:PFC11 OUT:PFC10 OUT:PFC11 OUT:PFC10 PFC4 PFC4 IN: PKTS[1] OUT:PFC10 OUT:PFC10 PFC4 PFC4 PFC3 PFC3 IN: PKTS[0] OUT:PFC9 OUT:PFC9 PFC3 PFC3 IN:PKTS[2] 00001000 bbbbbrbb OUT:PFC8 PFC0 00000000 RW PFC0 PFC8 PFC8 PFC0 PFC0 00000000 RW 00001000 bbrbbrrb 00001000 bbrbbrrb 00000000 RW 00000000 RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPPF1 INPPF1 INPPF1 INPPF1 INPPF0 INPPF0 INPPF0 INPPF0 00000001 brrrrrbb 00000001 brrrrrrr 00000001 brrrrrbb 00000001 brrrrrrr Skip Skip 0 0 0 0 0 0 0 0 0 0 EP8 EP8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP6 EP6 EP0ACK EP0ACK 0 0 0 0 0 0 0 0 0 0 EP8 EP8 EP4 EP4 HSGRANT HSGRANT 0 0 0 0 0 0 0 0 0 0 EP6 EP6 EP2 EP2 URES URES EP3 EP3 EDGEPF 0 EDGEPF 0 EDGEPF 0 EDGEPF 0 EP4 EP4 EP1 EP1 SUSP SUSP EP2 EP2 PF PF PF PF PF PF PF PF EP2 EP2 EP0 EP0 SUTOK SUTOK EP1 EP1 EF EF EF EF EF EF EF EF EP1 EP1 0 0 SOF SOF EP0 EP0 FF FF FF FF FF FF FF FF EP0 EP0 IBN IBN SUDAV SUDAV xxxxxxxx W xxxxxxxx W 00000000 RW 00000000 rrrrrbbb 00000000 RW 00000000 rrrrrbbb 00000000 RW 00000000 rrrrrbbb 00000000 RW 00000000 rrrrrbbb 00000000 RW 00xxxxxx rrbbbbbb 00000000 RW xxxxxx0x bbbbbbrb 00000000 RW 0xxxxxxx rbbbbbbb [10] EP4FIFOIRQ[10,11] EP6FIFOIE[10] EP6FIFOIRQ EP8FIFOIE [10,11] [10] EP8FIFOIRQ[10,11] IBNIE IBNIRQ[11] NAKIE NAKIRQ[11] USBIE USBIRQ[11] Note 11. The register can only be reset, it cannot be set. Document # 001-06120 Rev *I Page 17 of 40 [+] Feedback CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name E65E 1 EPIE E65F E660 E661 E662 E663 E664 E665 E666 E667 E668 E669 E670 E671 E672 E673 E677 E678 E679 E67A E67B E67C 1 1 1 1 1 1 1 1 1 1 7 1 1 1 4 1 1 1 1 1 1 EPIRQ[11] GPIFIE[10] GPIFIRQ[10] USBERRIE USBERRIRQ[11] ERRCNTLIM CLRERRCNT INT2IVEC Reserved INTSET-UP Reserved INPUT/OUTPUT PORTACFG PORTCCFG PORTECFG Reserved Reserved I2CS I2DAT I2CTL XAUTODAT1 XAUTODAT2 UDMA CRC UDMACRCH[10] UDMACRCL[10] UDMACRCQUALIFIER USB CONTROL USBCS SUSPEND WAKEUPCS TOGCTL USBFRAMEH USBFRAMEL MICROFRAME FNADDR Reserved ENDPOINTS EP0BCH[10] EP0BCL[10] Reserved EP1OUTBC Reserved EP1INBC EP2BCH[10] EP2BCL[10] Reserved EP4BCH[10] EP4BCL[10] Reserved EP6BCH[10] EP6BCL[10] Reserved EP8BCH[10] EP8BCL[10] Reserved EP0CS EP1OUTCS Description Endpoint interrupt enables Endpoint interrupt requests GPIF interrupt enable GPIF interrupt request USB error interrupt enables USB error interrupt requests USB error counter and limit Clear error counter EC3:0 Interrupt 2 (USB) autovector Interrupt 2 and 4 setup b7 EP8 EP8 0 0 ISOEP8 ISOEP8 EC3 x 0 1 0 b6 EP6 EP6 0 0 ISOEP6 ISOEP6 EC2 x I2V4 0 0 b5 EP4 EP4 0 0 ISOEP4 ISOEP4 EC1 x I2V3 0 0 b4 EP2 EP2 0 0 ISOEP2 ISOEP2 EC0 x I2V2 0 0 b3 EP1OUT EP1OUT 0 0 0 0 LIMIT3 x I2V1 0 AV2EN b2 EP1IN EP1IN 0 0 0 0 LIMIT2 x I2V0 0 0 b1 EP0OUT EP0OUT GPIFWF GPIFWF 0 0 LIMIT1 x 0 0 Reserved b0 EP0IN EP0IN Default Access 00000000 RW 0 RW GPIFDONE 00000000 RW GPIFDONE 000000xx RW ERRLIMIT 00000000 RW ERRLIMIT 0000000x bbbbrrrb LIMIT0 x 0 0 AV4EN xxxx0100 rrrrbbbb xxxxxxxx W 00000000 R 10000000 R 00000000 RW I/O PORTA alternate configuration I/O PORTC alternate configuration I/O PORTE alternate configuration FLAGD GPIFA7 GPIFA8 SLCS GPIFA6 T2EX 0 GPIFA5 INT6 0 GPIFA4 RXD1OUT 0 GPIFA3 RXD0OUT 0 GPIFA2 T2OUT INT1 GPIFA1 T1OUT INT0 GPIFA0 T0OUT 00000000 RW 00000000 RW 00000000 RW I²C bus control and status I²C bus data I²C bus control Autoptr1 MOVX access, when APTREN = 1 Autoptr2 MOVX access, when APTREN = 1 UDMA CRC MSB UDMA CRC LSB UDMA CRC qualifier START d7 0 D7 D7 STOP d6 0 D6 D6 LASTRD d5 0 D5 D5 ID1 d4 0 D4 D4 ID0 d3 0 D3 D3 BERR d2 0 D2 D2 ACK d1 STOPIE D1 D1 DONE d0 400KHZ D0 D0 000xx000 bbbrrrrr xxxxxxxx RW 00000000 RW xxxxxxxx RW xxxxxxxx RW E67D E67E E67F 1 1 1 CRC15 CRC7 QENABLE CRC14 CRC6 0 CRC13 CRC5 0 CRC12 CRC4 0 CRC11 CRC3 QSTATE CRC10 CRC2 QSIGNAL2 CRC9 CRC1 QSIGNAL1 CRC8 01001010 RW CRC0 10111010 RW QSIGNAL0 00000000 brrrbbbb E680 E681 E682 E683 E684 E685 E686 E687 E688 E68A E68B E68C E68D E68E E68F E690 E691 E692 E694 E695 E696 E698 E699 E69A E69C E69D E69E E6A0 E6A1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 2 1 1 2 1 1 2 1 1 2 1 1 USB control and status Put chip into suspend Wakeup control and status Toggle control USB frame count H USB frame count L Microframe count, 0-7 USB function address HSM x WU2 Q 0 FC7 0 0 0 x WU S 0 FC6 0 FA6 0 x WU2POL R 0 FC5 0 FA5 0 x WUPOL I/O 0 FC4 0 FA4 DISCON x 0 EP3 0 FC3 0 FA3 NOSYNSOF x DPEN EP2 FC10 FC2 MF2 FA2 RENUM x WU2EN EP1 FC9 FC1 MF1 FA1 SIGRSUME x WUEN EP0 FC8 FC0 MF0 FA0 x0000000 rrrrbbbb xxxxxxxx W xx000101 bbbbrbbb x0000000 rrrbbbbb 00000xxx R xxxxxxxx R 00000xxx R 0xxxxxxx R Endpoint 0 byte count H Endpoint 0 byte count L Endpoint 1 OUT byte count Endpoint 1 IN byte count Endpoint 2 byte count H Endpoint 2 byte count L Endpoint 4 byte count H Endpoint 4 byte count L Endpoint 6 byte count H Endpoint 6 byte count L Endpoint 8 byte count H Endpoint 8 byte count L Endpoint 0 control and status Endpoint 1 OUT control and status (BC15) (BC7) 0 0 0 BC7/SKIP 0 BC7/SKIP 0 BC7/SKIP 0 BC7/SKIP HSNAK 0 (BC14) BC6 BC6 BC6 0 BC6 0 BC6 0 BC6 0 BC6 0 0 (BC13) BC5 BC5 BC5 0 BC5 0 BC5 0 BC5 0 BC5 0 0 (BC12) BC4 BC4 BC4 0 BC4 0 BC4 0 BC4 0 BC4 0 0 (BC11) BC3 BC3 BC3 0 BC3 0 BC3 0 BC3 0 BC3 0 0 (BC10) BC2 BC2 BC2 BC10 BC2 0 BC2 BC10 BC2 0 BC2 0 0 (BC9) BC1 BC1 BC1 BC9 BC1 BC9 BC1 BC9 BC1 BC9 BC1 BUSY BUSY (BC8) BC0 BC0 BC0 BC8 BC0 BC8 BC0 BC8 BC0 BC8 BC0 STALL STALL xxxxxxxx RW xxxxxxxx RW 0xxxxxxx RW 0xxxxxxx RW 00000xxx RW xxxxxxxx RW 000000xx RW xxxxxxxx RW 00000xxx RW xxxxxxxx RW 000000xx RW xxxxxxxx RW 10000000 bbbbbbrb 00000000 bbbbbbrb Document # 001-06120 Rev *I Page 18 of 40 [+] Feedback CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name E6A2 1 EP1INCS E6A3 E6A4 E6A5 E6A6 E6A7 E6A8 E6A9 E6AA E6AB E6AC E6AD E6AE E6AF E6B0 E6B1 E6B2 E6B3 E6B4 E6B5 E6B8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 8 EP2CS EP4CS EP6CS EP8CS EP2FIFOFLGS EP4FIFOFLGS EP6FIFOFLGS EP8FIFOFLGS EP2FIFOBCH EP2FIFOBCL EP4FIFOBCH EP4FIFOBCL EP6FIFOBCH EP6FIFOBCL EP8FIFOBCH EP8FIFOBCL SUDPTRH SUDPTRL SUDPTRCTL Reserved SET-UPDAT Description Endpoint 1 IN control and status Endpoint 2 control and status Endpoint 4 control and status Endpoint 6 control and status Endpoint 8 control and status Endpoint 2 Slave FIFO flags Endpoint 4 Slave FIFO flags Endpoint 6 Slave FIFO flags Endpoint 8 Slave FIFO flags Endpoint 2 Slave FIFO total byte count H Endpoint 2 Slave FIFO total byte count L Endpoint 4 Slave FIFO total byte count H Endpoint 4 Slave FIFO total byte count L Endpoint 6 Slave FIFO total byte count H Endpoint 6 Slave FIFO total byte count L Endpoint 8 Slave FIFO total byte count H Endpoint 8 Slave FIFO total byte count L Setup data pointer high address byte Setup data pointer low address byte Setup data pointer auto mode 8 bytes of setup data SET-UPDAT[0] = bmRequestType SET-UPDAT[1] = bmRequest SET-UPDAT[2:3] = wValue SET-UPDAT[4:5] = wIndex SET-UPDAT[6:7] = wLength Waveform selector GPIF Done, GPIF Idle drive mode Inactive bus, CTL states CTL drive type b7 0 0 0 0 0 0 0 0 0 0 BC7 0 BC7 0 BC7 0 BC7 A15 A7 0 D7 b6 0 NPAK2 0 NPAK2 0 0 0 0 0 0 BC6 0 BC6 0 BC6 0 BC6 A14 A6 0 D6 b5 0 NPAK1 NPAK1 NPAK1 NPAK1 0 0 0 0 0 BC5 0 BC5 0 BC5 0 BC5 A13 A5 0 D5 b4 0 NPAK0 NPAK0 NPAK0 NPAK0 0 0 0 0 BC12 BC4 0 BC4 0 BC4 0 BC4 A12 A4 0 D4 b3 0 FULL FULL FULL FULL 0 0 0 0 BC11 BC3 0 BC3 BC11 BC3 0 BC3 A11 A3 0 D3 b2 0 EMPTY EMPTY EMPTY EMPTY PF PF PF PF BC10 BC2 BC10 BC2 BC10 BC2 BC10 BC2 A10 A2 0 D2 b1 BUSY 0 0 0 0 EF EF EF EF BC9 BC1 BC9 BC1 BC9 BC1 BC9 BC1 A9 A1 0 D1 b0 STALL STALL STALL STALL STALL FF FF FF FF BC8 BC0 BC8 BC0 BC8 BC0 BC8 BC0 A8 0 Default Access 00000000 bbbbbbrb 00101000 rrrrrrrb 00101000 rrrrrrrb 00000100 rrrrrrrb 00000100 rrrrrrrb 00000010 R 00000010 R 00000110 R 00000110 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R xxxxxxxx RW xxxxxxx0 bbbbbbbr SDPAUTO 00000001 RW D0 xxxxxxxx R E6C0 E6C1 E6C2 E6C3 E6C4 E6C5 E6C6 E6C7 E6C8 E6C9 E6CA E6CB E6CC E6CD E6CE E6CF E6D0 E6D1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 GPIF GPIFWFSELECT GPIFIDLECS GPIFIDLECTL GPIFCTLCFG Reserved Reserved FLOWSTATE FLOWSTATE FLOWLOGIC FLOWEQ0CTL FLOWEQ1CTL FLOWHOLDOFF FLOWSTB FLOWSTBEDGE FLOWSTBPERIOD GPIFTCB3[10] GPIFTCB2[10] GPIFTCB1[10] GPIFTCB0[10] Reserved Reserved SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 DONE 0 0 0 0 TRICTL 0 0 0 0 0 0 FIFOWR1 0 0 0 FIFOWR0 0 CTL2 CTL2 FIFORD1 0 CTL1 CTL1 FIFORD0 IDLEDRV CTL0 CTL0 11100100 RW 10000000 RW 11111111 RW 00000000 RW 00000000 00000000 00000000 brrrrbbb 00000000 RW 00000000 RW 00000000 RW 00010010 RW 00100000 RW 00000001 rrrrrrbb 00000010 RW 00000000 RW 00000000 RW 00000000 RW 00000001 RW 00000000 RW Flowstate enable and FSE 0 0 0 selector Flowstate logic LFUNC1 LFUNC0 TERMA2 TERMA1 CTL-pin states in flow state CTL0E3 CTL0E2 CTL0E1 CTL0E0 (when Logic = 0) CTL-pin states in flow state CTL0E3 CTL0E2 CTL0E1 CTL0E0 (when Logic = 1) Holdoff configuration HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 Flowstate strobe SLAVE RDYASYNC CTLTOGL SUSTAIN configuration Flowstate rising/falling edge 0 0 0 0 configuration Master strobe half period D7 D6 D5 D4 GPIF transaction count TC31 TC30 TC29 TC28 Byte 3 GPIF transaction count TC23 TC22 TC21 TC20 Byte 2 GPIF transaction count TC15 TC14 TC13 TC12 Byte 1 GPIF transaction count TC7 TC6 TC5 TC4 Byte 0 0 TERMA0 0 0 HOSTATE 0 0 D3 TC27 TC19 TC11 TC3 FS2 TERMB2 CTL2 CTL2 HOCTL2 MSTB2 0 D2 TC26 TC18 TC10 TC2 FS1 TERMB1 CTL1 CTL1 HOCTL1 MSTB1 FALLING D1 TC25 TC17 TC9 TC1 FS0 TERMB0 CTL0 CTL0 HOCTL0 MSTB0 RISING D0 TC24 TC16 TC8 TC0 Document # 001-06120 Rev *I Page 19 of 40 [+] Feedback CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name Description Reserved [10] Endpoint 2 GPIF flag E6D2 1 EP2GPIFFLGSEL select E6D3 1 EP2GPIFPFSTOP Endpoint 2 GPIF stop transaction on program flag E6D4 1 EP2GPIFTRIG[10] Endpoint 2 GPIF trigger 3 Reserved Reserved Reserved E6DA 1 EP4GPIFFLGSEL[10] Endpoint 4 GPIF flag select E6DB 1 EP4GPIFPFSTOP Endpoint 4 GPIF stop transaction on GPIF flag E6DC 1 EP4GPIFTRIG[10] Endpoint 4 GPIF trigger 3 Reserved Reserved Reserved E6E2 1 EP6GPIFFLGSEL[10] Endpoint 6 GPIF flag select E6E3 E6E4 1 1 3 EP6GPIFPFSTOP EP6GPIFTRIG[10] Endpoint 6 GPIF stop transaction on program flag Endpoint 6 GPIF trigger b7 0 0 x b6 0 0 x b5 0 0 x b4 0 0 x b3 0 0 x b2 0 0 x b1 FS1 0 x b0 FS0 Default Access 00000000 RW FIFO2FLAG 00000000 RW x xxxxxxxx W 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x FS1 0 x FS0 00000000 RW FIFO4FLAG 00000000 RW x xxxxxxxx W 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x 0 0 x FS1 0 x FS0 00000000 RW FIFO6FLAG 00000000 RW x xxxxxxxx W E6EA E6EB E6EC E6F0 E6F1 E6F2 E6F3 1 1 1 3 1 1 1 1 Reserved Reserved Reserved EP8GPIFFLGSEL[10] Endpoint 8 GPIF flag select EP8GPIFPFSTOP Endpoint 8 GPIF stop transaction on program flag EP8GPIFTRIG[10] Endpoint 8 GPIF trigger Reserved XGPIFSGLDATH GPIF Data H (16-bit mode only) XGPIFSGLDATLX Read/Write GPIF Data L and trigger transaction XGPIFSGLDATLRead GPIF Data L, no transNOX action trigger GPIFREADYCFG Internal RDY, sync/async, RDY pin states 0 0 x D15 D7 D7 INTRDY 0 0 x D14 D6 D6 SAS 0 0 x D13 D5 D5 TCXRDY5 0 0 x D12 D4 D4 0 0 0 x D11 D3 D3 0 0 0 x D10 D2 D2 0 FS1 0 x D9 D1 D1 0 FS0 00000000 RW FIFO8FLAG 00000000 RW x D8 D0 D0 0 xxxxxxxx W xxxxxxxx RW xxxxxxxx RW xxxxxxxx R 00000000 bbbrrrrr E6F4 E6F5 E6F6 E740 E780 E7C0 E800 F000 F400 F600 F800 FC00 FE00 xxxx GPIFREADYSTAT GPIF ready status GPIFABORT Abort GPIF waveforms Reserved ENDPOINT BUFFERS 64 EP0BUF EP0-IN/-OUT buffer 64 EP10UTBUF EP1-OUT buffer 64 EP1INBUF EP1-IN buffer 2048 Reserved 1024 EP2FIFOBUF 512/1024-byte EP 2/Slave FIFO buffer (IN or OUT) 512 EP4FIFOBUF 512 byte EP 4/Slave FIFO buffer (IN or OUT) 512 Reserved 1024 EP6FIFOBUF 512/1024-byte EP 6/Slave FIFO buffer (IN or OUT) 512 EP8FIFOBUF 512 byte EP 8/Slave FIFO buffer (IN or OUT) 512 Reserved I²C Configuration Byte 1 1 2 0 x 0 x 0 x 0 x 0 x 0 x RDY1 x RDY0 x 00xxxxxx R xxxxxxxx W D7 D7 D7 D7 D7 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D4 D4 D4 D4 D4 D3 D3 D3 D3 D3 D2 D2 D2 D2 D2 D1 D1 D1 D1 D1 D0 D0 D0 D0 D0 xxxxxxxx RW xxxxxxxx RW xxxxxxxx RW RW xxxxxxxx RW xxxxxxxx RW D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 xxxxxxxx RW xxxxxxxx RW 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx n/a [12] Note 12. If no EEPROM is detected by the SIE then the default is 00000000. Document # 001-06120 Rev *I Page 20 of 40 [+] Feedback CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A8 A9 AA AB AC AD AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Size Name Description Special Function Registers (SFRs) [13] 1 IOA Port A (bit addressable) 1 SP Stack Pointer 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DPL0 DPH0 DPL1[13] DPH1[13] DPS[13] PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON[13] Reserved IOB[13] EXIF[13] MPAGE[13] Reserved SCON0 SBUF0 AUTOPTRH1[13] AUTOPTRL1[13] Reserved AUTOPTRH2[13] AUTOPTRL2[13] Reserved IOC[13] INT2CLR[13] Reserved Reserved IE Reserved EP2468STAT[13] EP24FIFOFLGS [13] [13] b7 D7 D7 A7 A15 A7 A15 0 SMOD0 TF1 GATE D7 D7 D15 D15 x D7 IE5 A15 b6 D6 D6 A6 A14 A6 A14 0 x TR1 CT D6 D6 D14 D14 x D6 IE4 A14 b5 D5 D5 A5 A13 A5 A13 0 1 TF0 M1 D5 D5 D13 D13 T2M D5 I²CINT A13 b4 D4 D4 A4 A12 A4 A12 0 1 TR0 M0 D4 D4 D12 D12 T1M D4 USBNT A12 b3 D3 D3 A3 A11 A3 A11 0 x IE1 GATE D3 D3 D11 D11 T0M D3 1 A11 b2 D2 D2 A2 A10 A2 A10 0 x IT1 CT D2 D2 D10 D10 MD2 D2 0 A10 b1 D1 D1 A1 A9 A1 A9 0 x IE0 M1 D1 D1 D9 D9 MD1 D1 0 A9 b0 D0 D0 A0 A8 A0 A8 SEL IDLE IT0 M0 D0 D0 D8 D8 MD0 D0 0 A8 Default Access xxxxxxxx RW 00000111 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00110000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000001 RW xxxxxxxx RW 00001000 RW 00000000 RW Data Pointer 0 L Data Pointer 0 H Data Pointer 1 L Data Pointer 1 H Data Pointer 0/1 select Power control Timer/Counter control (bit addressable) Timer/Counter mode control Timer 0 reload L Timer 1 reload L Timer 0 reload H Timer 1 reload H Clock control Port B (bit addressable) External interrupt flags Upper address byte of MOVX using @R0/@R1 Serial Port 0 Control (bit addressable) Serial Port 0 data buffer Autopointer 1 address H Autopointer 1 address L Autopointer 2 address H Autopointer 2 address L Port C (bit addressable) Interrupt 2 Clear SM0_0 D7 A15 A7 A15 A7 D7 x x EA SM1_0 D6 A14 A6 A14 A6 D6 x x ES1 SM2_0 D5 A13 A5 A13 A5 D5 x x ET2 REN_0 D4 A12 A4 A12 A4 D4 x x ES0 TB8_0 D3 A11 A3 A11 A3 D3 x x ET1 RB8_0 D2 A10 A2 A10 A2 D2 x x EX1 TI_0 D1 A9 A1 A9 A1 D1 x x ET0 RI_0 D0 A8 A0 A8 A0 D0 x x EX0 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW xxxxxxxx RW xxxxxxxx W xxxxxxxx W 00000000 RW Interrupt Enable (bit addressable) Endpoint 2,4,6,8 status flags Endpoint 2,4 Slave FIFO status flags Endpoint 6,8 Slave FIFO status flags EP8F 0 0 EP8E EP4PF EP8PF EP6F EP4EF EP8EF EP6E EP4FF EP8FF EP4F 0 0 EP4E EP2PF EP6PF EP2F EP2EF EP6EF EP2E EP2FF EP6FF 01011010 R 00100010 R 01100110 R EP68FIFOFLGS Reserved AUTOPTRSETUP[13] Autopointer 1 and 2 Setup IOD[13] Port D (bit addressable) IOE[13] Port E (NOT bit addressable) OEA[13] Port A Output Enable OEB[13] Port B Output Enable OEC[13] Port C Output Enable OED[13] Port D Output Enable OEE[13] Port E Output Enable Reserved IP Interrupt Priority (bit addressable) Reserved EP01STAT[13] Endpoint 0 and 1 Status GPIFTRIG[13, 10] Endpoint 2,4,6,8 GPIF Slave FIFO trigger Reserved GPIFSGLDATH[13] GPIF Data H (16-bit mode only) GPIFSGLDATLX[13] GPIF Data L w/trigger GPIFSGLDATLGPIF Data L w/no trigger NOX[13] 0 D7 D7 D7 D7 D7 D7 D7 1 0 D6 D6 D6 D6 D6 D6 D6 PS1 0 D5 D5 D5 D5 D5 D5 D5 PT2 0 D4 D4 D4 D4 D4 D4 D4 PS0 0 D3 D3 D3 D3 D3 D3 D3 PT1 APTR2INC D2 D2 D2 D2 D2 D2 D2 PX1 APTR1INC D1 D1 D1 D1 D1 D1 D1 PT0 APTREN D0 D0 D0 D0 D0 D0 D0 PX0 00000110 RW xxxxxxxx RW xxxxxxxx RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 10000000 RW 0 DONE 0 0 0 0 0 0 0 0 EP1INBSY EP1OUTBSY RW EP1 EP0BSY EP0 00000000 R 10000xxx brrrrbbb D15 D7 D7 D14 D6 D6 D13 D5 D5 D12 D4 D4 D11 D3 D3 D10 D2 D2 D9 D1 D1 D8 D0 D0 xxxxxxxx RW xxxxxxxx RW xxxxxxxx R Note 13. SFRs not part of the standard 8051 architecture. Document # 001-06120 Rev *I Page 21 of 40 [+] Feedback CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex C0 C1 C2 C8 C9 CA CB CC CD CE D0 D1 D8 D9 E0 E1 E8 E9 F0 F1 F8 F9 Size Name 1 SCON1[13] 1 6 1 1 1 1 1 1 2 1 7 1 7 1 7 1 7 1 7 1 7 SBUF1[13] Reserved T2CON Reserved RCAP2L RCAP2H TL2 TH2 Reserved PSW Reserved EICON[13] Reserved ACC Reserved EIE[13] Reserved B Reserved EIP[13] Reserved Description Serial Port 1 Control (bit addressable) Serial Port 1 Data Buffer Timer/Counter 2 Control (bit addressable) Capture for Timer 2, auto-reload, up counter Capture for Timer 2, auto-reload, up counter Timer 2 Reload L Timer 2 Reload H Program Status Word (bit addressable) External Interrupt Control Accumulator (bit addressable) External Interrupt Enables B (bit addressable) External Interrupt Priority control b7 SM0_1 D7 TF2 b6 SM1_1 D6 EXF2 b5 SM2_1 D5 RCLK b4 REN_1 D4 TCLK b3 TB8_1 D3 EXEN2 b2 RB8_1 D2 TR2 b1 TI_1 D1 CT2 b0 RI_1 D0 CPRL2 Default Access 00000000 RW 00000000 RW 00000000 RW D7 D7 D7 D15 CY D6 D6 D6 D14 AC D5 D5 D5 D13 F0 D4 D4 D4 D12 RS1 D3 D3 D3 D11 RS0 D2 D2 D2 D10 OV D1 D1 D1 D9 F1 D0 D0 D0 D8 P 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW SMOD1 D7 1 D6 ERESI D5 RESI D4 INT6 D3 0 D2 0 D1 0 D0 01000000 RW 00000000 RW 1 D7 1 1 D6 1 1 D5 1 EX6 D4 PX6 EX5 D3 PX5 EX4 D2 PX4 EI²C D1 PI²C EUSB D0 PUSB 11100000 RW 00000000 RW 11100000 RW Ledgend R = All bits read only W = All bits write only r = Read-only bit w = Write-only bit b = Both read/write bit Document # 001-06120 Rev *I Page 22 of 40 [+] Feedback CY7C68053 6. Absolute Maximum Ratings Storage Temperature ............................................................. ..................................................................................... –65°C to +150°C Ambient Temperature with Power Supplied Industrial ................................................................................ ....................................................................................... –40°C to +85°C Supply Voltage to Ground Potential For 3.3V Power domain......................................................... ........................................................................................ –0.5V to +4.0V For 1.8V Power domain......................................................... ........................................................................................ –0.5V to +2.0V DC Input Voltage to Any Input Pin For pins under 3.3V Power Domain ...................................... ....................................................................................................3.6V[14] For pins under 1.8V - 3.3V Power Domain (GPIOs).............. ..................................................................................... 1.89V to 3.6V[14] (The GPIOs are not over voltage tolerant, except the SCL and SDA pins, which are 3.3V tolerant) DC Voltage Applied to Outputs in High Z State ..................... ............................................................................... –0.5V to VCC +0.5V Maximum Power Dissipation From AVcc Supply ................................................................. .....................................................................................................90 mW From I/O Supply .................................................................... .....................................................................................................36 mW From Core Supply ................................................................. .....................................................................................................95 mW Static Discharge Voltage........................................................ ....................................................................................................>2000V (I2C SCL and SDA pins only ................................................. .............................................................................................. ... >1500V) Maximum Output Current, per I/O port .................................. ......................................................................................................10 mA 7. Operating Conditions TA (Ambient Temperature Under Bias) Industrial ................................................................................ ....................................................................................... –40°C to +85°C Supply Voltage 3.3V Power Supply ................................................................ ............................................................................................ 3.0V to 3.6V 1.8V Power Supply ................................................................ ......................................................................................... 1.71V to1.89V Ground Voltage...................................................................... ............................................................................................................ 0V FOSC (Oscillator or Crystal Frequency).................................. .................................................................................. 24 MHz ± 100 ppm ............................................................................................... .................................................................................... Parallel Resonant ............................................................................................... ...................................................................................500 μW drive level ............................................................................................... .............................................................................Load capacitors 12 pF Note 14. Do not power I/O when chip power is OFF. Document # 001-06120 Rev *I Page 23 of 40 [+] Feedback CY7C68053 8. DC Characteristics Table 9. DC Characteristics Parameter AVCC VCC_IO VCC_A VCC_D VIH VIL VIH_X VIL_X II VOH VOL IOH IOL CIN ISUSP ICC_AVcc ICC_IO ICC_CORE TRESET Description 3.3V supply (to oscillator and PHY) 1.8V to 3.3V supply (to I/O) 1.8V supply to analog core 1.8V supply to digital core Input HIGH voltage Input LOW voltage Crystal input HIGH voltage Crystal input LOW voltage Hysteresis Input leakage current Output voltage HIGH Output LOW voltage Output current HIGH Output current LOW Input pin capacitance Suspend current Supply current (AVCC) Supply current (VCC_IO) Supply current (VCC_CORE) Reset time after valid power Pin reset after powered on Except D+/D– D+/D– Connected Disconnected 8051 running, connected to USB HS 8051 running, connected to USB FS 8051 running, connected to USB HS 8051 running, connected to USB FS 8051 running, connected to USB HS 8051 running, connected to USB FS VCC min = 3.0V 5.0 200 220 20 15 10 3 1 32 24 0< VIN < VCC_IO IOUT = 4 mA IOUT = –4 mA VCC_IO – 0.4 0.4 4 4 10 15 380[15] 150[15] 25 20 10 5 50 40 Conditions Min 3.00 1.71 1.71 1.71 0.6*VCC_IO 0 2.0 –0.5 50 ±10 Typ 3.3 1.8 1.8 1.8 Max 3.60 3.60 1.89 1.89 VCC_IO+10% Unit V V V V V V V V mV μA V V mA mA pF pF μA μA mA mA mA mA mA mA ms μs 0.3*VCC_IO 3.60 0.8 Note 15. Measured at maximum VCC, 25°C. Document # 001-06120 Rev *I Page 24 of 40 [+] Feedback CY7C68053 9. AC Electrical Characteristics 9.1 USB Transceiver USB 2.0-compliant in full and high speed modes. 9.2 GPIF Synchronous Signals Figure 8. GPIF Synchronous Signals Timing Diagram[16] tIFCLK IFCLK tSGA GPIFADR[8:0] RDYX tSRY tRYH DATA(input) tSGD valid tDAH CTLX tXCTL DATA(output) N tXGD N+1 Table 10.GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[16,17] Parameter tIFCLK tSRY tRYH tSGD tDAH tXGD tXCTL 8 Description IFCLK period RDYX to clock setup time Clock to RDYX GPIF data to clock setup time GPIF data hold time Clock to GPIF data output propagation delay Clock to CTLX output propagation delay Min 20.83 8.9 0 9.2 0 Max Unit ns ns ns ns ns 11 6.7 ns ns Table 11.GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[17] Parameter tIFCLK tSRY tRYH tSGD tDAH tXGD tXCTL IFCLK period[18] Description RDYX to clock setup time Clock to RDYX GPIF data to clock setup time GPIF data hold time Clock to GPIF data output propagation delay Clock to CTLX output propagation delay Min 20.83 2.9 3.7 3.2 4.5 15 13.06 Max 200 Unit ns ns ns ns ns ns ns Notes 16. Dashed lines denote signals with programmable polarity. 17. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK. 18. IFCLK must not exceed 48 MHz. Document # 001-06120 Rev *I Page 25 of 40 [+] Feedback CY7C68053 9.3 Slave FIFO Synchronous Read Figure 9. Slave FIFO Synchronous Read Timing Diagram[16] tIFCLK IFCLK tSRD SLRD tXFLG FLAGS tRDH DATA tOEon SLOE N N+1 tXFD tOEoff Table 12.Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[17] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK period SLRD to clock setup time Clock to SLRD hold time SLOE turn-on to FIFO data valid SLOE turn-off to FIFO data hold Clock to FLAGS output propagation delay Clock to FIFO data output propagation delay 2.15 Description Min 20.83 18.7 0 10.5 10.5 9.5 11 Max Unit ns ns ns ns ns ns ns Table 13.Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[17] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK period SLRD to clock setup time Clock to SLRD hold time SLOE turn-on to FIFO data valid SLOE turn-off to FIFO data hold Clock to FLAGS output propagation delay Clock to FIFO data output propagation delay 2.15 Description Min 20.83 12.7 3.7 10.5 10.5 13.5 17.31 Max 200 Unit ns ns ns ns ns ns ns Document # 001-06120 Rev *I Page 26 of 40 [+] Feedback CY7C68053 9.4 Slave FIFO Asynchronous Read Figure 10. Slave FIFO Asynchronous Read Timing Diagram[16] tRDpwh SLRD tRDpwl tXFLG FLAGS tXFD DATA N tOEon N+1 tOEoff SLOE Table 14.Slave FIFO Asynchronous Read Parameters[19] Parameter tRDpwl tRDpwh tXFLG tXFD tOEon tOEoff Description SLRD pulse width LOW SLRD pulse width HIGH SLRD to FLAGS output propagation delay SLRD to FIFO data output propagation delay SLOE turn-on to FIFO data valid SLOE turn-off to FIFO data hold 2.15 Min 50 50 70 15 10.5 10.5 Max Unit ns ns ns ns ns ns Note 19. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document # 001-06120 Rev *I Page 27 of 40 [+] Feedback CY7C68053 9.5 Slave FIFO Synchronous Write Figure 11. Slave FIFO Synchronous Write Timing Diagram[16] tIFCLK IFCLK SLWR tSWR tWRH DATA Z tSFD N tFDH Z FLAGS tXFLG Table 15.Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[17] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG IFCLK period SLWR to clock setup time Clock to SLWR hold time FIFO data to clock setup time Clock to FIFO data hold time Clock to FLAGS output propagation time Description Min 20.83 18.1 0 10.64 0 9.5 Max Unit ns ns ns ns ns ns Table 16.Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[10] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG IFCLK period SLWR to clock setup time Clock to SLWR hold time FIFO data to clock setup time Clock to FIFO data hold time Clock to FLAGS output propagation time Description Min 20.83 12.1 3.6 3.2 4.5 13.5 Max 200 Unit ns ns ns ns ns ns Document # 001-06120 Rev *I Page 28 of 40 [+] Feedback CY7C68053 9.6 Slave FIFO Asynchronous Write Figure 12. Slave FIFO Asynchronous Write Timing Diagram[16] tWRpwh SLWR tWRpwl tSFD DATA tFDH FLAGS tXFD Table 17.Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[19] Parameter tWRpwl tWRpwh tSFD tFDH tXFD SLWR pulse LOW SLWR pulse HIGH SLWR to FIFO data setup time FIFO data to SLWR hold time SLWR to FLAGS output propagation delay Description Min 50 50 10 10 70 Max Unit ns ns ns ns ns 9.7 Slave FIFO Synchronous Packet End Strobe Figure 13. Slave FIFO Synchronous Packet End Strobe Timing Diagram[16] IFCLK tPEH PKTEND tSPE FLAGS tXFLG Table 18.Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[10] Parameter tIFCLK tSPE tPEH tXFLG IFCLK period PKTEND to clock setup time Clock to PKTEND hold time Clock to FLAGS output propagation delay Description Min 20.83 14.6 0 9.5 Max Unit ns ns ns ns Table 19.Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[10] Parameter tIFCLK tSPE tPEH tXFLG IFCLK period PKTEND to clock setup time Clock to PKTEND hold time Clock to FLAGS output propagation delay Description Min 20.83 8.6 3.04 13.5 Max 200 Unit ns ns ns ns Document # 001-06120 Rev *I Page 29 of 40 [+] Feedback CY7C68053 There is no specific timing requirement to be met for asserting the PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The only consideration is that the setup time tSPE and the hold time tPEH must be met. Although there are no specific timing requirements for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. There is an additional timing requirement to be met when the FIFO is configured to operate in auto mode and you want to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this scenario, make sure to assert PKTEND at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet. Figure 14 shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode. Figure 14 shows a scenario where two packets are committed. The first packet is committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet is committed manually using PKTEND. Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing, results in the FX2LP18 failing to send the one byte/word short packet. Figure 14. Slave FIFO Synchronous Write Sequence and Timing Diagram[16] tIFCLK IFCLK tSFA tFAH FIFOADR >= tSWR >= tWRH SLWR tSFD tFDH tSFD X-3 tFDH tSFD X-2 tFDH tSFD X-1 tFDH tSFD X tFDH tSFD 1 tFDH DATA X-4 At least one IFCLK cycle tSPE tPEH PKTEND 9.8 Slave FIFO Asynchronous Packet End Strobe Figure 15. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[16] tPEpwh PKTEND tPEpwl FLAGS tXFLG Table 20.Slave FIFO Asynchronous Packet End Strobe Parameters[19] Parameter tPEpwl tPWpwh tXFLG Description PKTEND pulse width LOW PKTEND pulse width HIGH PKTEND to FLAGS output propagation delay Min 50 50 115 Max Unit ns ns ns Document # 001-06120 Rev *I Page 30 of 40 [+] Feedback CY7C68053 9.9 Slave FIFO Output Enable Figure 16. Slave FIFO Output Enable Timing Diagram[16] SLOE tOEoff DATA tOEon Table 21.Slave FIFO Output Enable Parameters Parameter tOEon tOEoff Description SLOE assert to FIFO data output SLOE deassert to FIFO data hold 2.15 Min Max 10.5 10.5 Unit ns ns 9.10 Slave FIFO Address to Flags/Data Figure 17. Slave FIFO Address to Flags/Data Timing Diagram[16] FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1 Table 22.Slave FIFO Address to Flags/Data Parameters Parameter tXFLG tXFD Description FIFOADR[1:0] to flags output propagation delay FIFOADR[1:0] to FIFO data output propagation delay Min Max 10.7 14.3 Unit ns ns Document # 001-06120 Rev *I Page 31 of 40 [+] Feedback CY7C68053 9.11 Slave FIFO Synchronous Address Figure 18. Slave FIFO Synchronous Address Timing Diagram[16] IFCLK SLCS/FIFOADR [1:0] tSFA tFAH Table 23.Slave FIFO Synchronous Address Parameters[10] Parameter tIFCLK tSFA tFAH Interface clock period FIFOADR[1:0] to clock setup time Clock to FIFOADR[1:0] hold time Description Min 20.83 25 10 Max 200 Unit ns ns ns 9.12 Slave FIFO Asynchronous Address Figure 19. Slave FIFO Asynchronous Address Timing Diagram[16] SLCS/FIFOADR [1:0] tSFA SLRD/SLWR/PKTEND tFAH Slave FIFO Asynchronous Address Parameters[19] Parameter tSFA tFAH Description FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time RD/WR/PKTEND to FIFOADR[1:0] hold time Min 10 10 Max Unit ns ns Document # 001-06120 Rev *I Page 32 of 40 [+] Feedback CY7C68053 9.13 Sequence Diagram Various sequence diagrams and examples are presented in this section. 9.13.1 Single and Burst Synchronous Read Example Figure 20. Slave FIFO Synchronous Read Sequence and Timing Diagram[16] tIFCLK IFCLK tSFA tFAH tSFA tFAH FIFOADR t=0 tSRD tRDH T=0 >= tSRD >= tRDH SLRD t=2 t=3 T=2 T=3 SLCS tXFLG FLAGS tXFD tXFD N+1 tOEoff tOEon N+1 N+2 tXFD N+3 tXFD N+4 DATA Data Driven: N tOEon tOEoff SLOE t=1 t=4 T=1 T=4 Figure 21. Slave FIFO Synchronous Sequence of Events Diagram IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK IFCLK FIFO POINTER N SLOE N SLRD N+1 SLOE SLRD N+1 SLOE N+1 SLRD N+2 N+2 N+3 N+3 N+4 SLRD N+4 SLOE N+4 Not Driven FIFO DATA BUS Not Driven Driven: N N+1 Not Driven N+1 N+4 N+4 Figure 20 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read. ■ If the SLCS signal is used, it must be asserted before SLRD (that is, the SLCS and SLRD signals must both be asserted to start a valid read condition). ■ At t = 0 the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied low in some applications). Note tSFA has a minimum of 25 ns. This means that when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle. At t = 1, SLOE is asserted. SLOE is an output enable only whose sole function is to drive the data bus. The data that is driven on the bus is the data that the internal FIFO pointer is currently pointing to. In this example, it is the first data value in the FIFO. Note The data is prefetched and driven on the bus when SLOE is asserted. At t = 2, SLRD is asserted. SLRD must meet the setup time of tSRD (time from asserting the SLRD signal to the rising edge of the IFCLK) and maintain a minimum hold time of tRDH (time from the IFCLK edge to the deassertion of the SLRD signal). ■ The FIFO pointer is updated on the rising edge of the IFCLK while SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of tXFD (measured from the rising edge of IFCLK) the new data value is present. N is the first data value read from the FIFO. To have data on the FIFO data bus, SLOE must also be asserted. ■ The same sequence of events is shown for a burst read and is marked with the time indicators of T = 0 through 5. Note For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle on the rising edge of the clock, the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. Page 33 of 40 Document # 001-06120 Rev *I [+] Feedback CY7C68053 9.13.2 Single and Burst Synchronous Write Figure 22. Slave FIFO Synchronous Write Sequence and Timing Diagram[16] tIFCLK IFCLK tSFA tFAH tSFA tFAH FIFOADR t=0 tSWR tWRH T=0 >= tSWR >= tWRH SLWR t=2 t=3 T=2 T=5 SLCS tXFLG tXFLG FLAGS tSFD tFDH N t=1 T=1 tSFD N+1 tFDH tSFD N+2 tFDH tSFD N+3 T=4 tFDH DATA T=3 tSPE tPEH PKTEND Figure 22 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the PKTEND pin. ■ FIFO data bus is written to the FIFO on every rising edge of IFCLK. The FIFO pointer is updated on each rising edge of IFCLK. In Figure 22, when the four bytes are written to the FIFO, SLWR is deasserted. The short 4-byte packet can be committed to the host by asserting the PKTEND signal. There is no specific timing requirement that needs to be met for asserting the PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only requirement is that the setup time tSPE and the hold time tPEH must be met. In the scenario of Figure 22, the number of data values committed includes the last value written to the FIFO. In this example, both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK. PKTEND can also be asserted in subsequent clock cycles. The FIFOADDR lines must be held constant during the PKTEND assertion. Although there are no specific timing requirements for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exist when the FIFO is configured to operate in auto mode and you want to send two packets: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this case, the external master must make sure to assert the PKTEND pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 14 on page 30 for further details about this timing. At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied low in some applications) Note tSFA has a minimum of 25 ns. This means that when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle. At t = 1, the external master/peripheral must output the data value onto the data bus with a minimum setup time of tSFD before the rising edge of IFCLK. At t = 2, SLWR is asserted. The SLWR must meet the setup time of tSWR (time from asserting the SLWR signal to the rising edge of IFCLK) and maintain a minimum hold time of tWRH (time from the IFCLK edge to the deassertion of the SLWR signal). If the SLCS signal is used, it must be asserted before SLWR is asserted. (That is, the SLCS and SLWR signals must both be asserted to start a valid write condition). While the SLWR is asserted, data is written to the FIFO and on the rising edge of the IFCLK, the FIFO pointer is incremented. The FIFO flag is also updated after a delay of tXFLG from the rising edge of the clock. ■ ■ ■ The same sequence of events is also shown for a burst write and is marked with the time indicators of T = 0 through 5. Note For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, when the SLWR is asserted, the data on the Document # 001-06120 Rev *I Page 34 of 40 [+] Feedback CY7C68053 9.13.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 23. Slave FIFO Asynchronous Read Sequence and Timing Diagram[16] tSFA tFAH tSFA tFAH FIFOADR t=0 tRDpwl tRDpwh T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwl tRDpwh SLRD t=2 t=3 T=2 T=3 T=4 T=5 T=6 SLCS tXFLG tXFLG FLAGS tXFD tXFD N tOEoff tOEon N+1 tXFD N+2 tXFD N+3 tOEoff DATA Data (X) Driven tOEon N SLOE t=1 t=4 T=1 T=7 Figure 24. Slave FIFO Asynchronous Read Sequence of Events Diagram SLOE SLRD SLRD SLOE SLOE SLRD SLRD SLRD SLRD SLOE FIFO POINTER N N Driven: X N N N+1 N N+1 Not Driven N+1 N N+1 N+1 N+2 N+1 N+2 N+2 N+3 N+2 N+3 Not Driven FIFO DATA BUS Not Driven Figure 23 illustrates the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. ■ ■ ■ At t = 0, the FIFO address is stable and the SLCS signal is asserted. At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data; it is data that was in the FIFO from a prior read cycle. At t = 2, SLRD is asserted. The SLRD must meet the minimum active pulse of tRDpwl and minimum inactive pulse width of tRDpwh. If SLCS is used then, SLCS must be asserted before SLRD is asserted (that is, the SLCS and SLRD signals must both be asserted to start a valid read condition). The data that is driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In Figure 23, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (for example, SLRD is asserted), SLOE MUST be in an asserted state. SLRD and SLOE can also be tied together. ■ The same sequence of events is also shown for a burst read marked with T = 0 through 5. Note In burst read mode, during SLOE assertion, the data bus is in a driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. Document # 001-06120 Rev *I Page 35 of 40 [+] Feedback CY7C68053 9.13.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 25. Slave FIFO Asynchronous Write Sequence and Timing Diagram[16] tSFA tFAH tSFA tFAH FIFOADR t=0 tWRpwl tWRpwh T=0 tWRpwl tWRpwh tWRpwl tWRpwh tWRpwl tWRpwh SLWR t =1 t=3 T=1 T=3 T=4 T=6 T=7 T=9 SLCS tXFLG tXFLG FLAGS tSFD tFDH tSFD tFDH N+1 T=2 T=5 tSFD tFDH N+2 tSFD tFDH N+3 T=8 DATA t=2 N tPEpwl tPEpwh PKTEND Figure 25 illustrates the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND. ■ At t = 0 the FIFO address is applied, ensuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications). At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum inactive pulse width of tWRpwh. If the SLCS is used, it must be asserted before SLWR is asserted. At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR. At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then the FIFO pointer is incremented. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR. The same sequence of events is shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note In the burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented. In Figure 25 when the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed to the host using the PKTEND. The external device must be designed to not assert SLWR and the PKTEND signal at the same time. It must be designed to assert the PKTEND after SLWR is deasserted and meet the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. ■ ■ ■ Document # 001-06120 Rev *I Page 36 of 40 [+] Feedback CY7C68053 10. Ordering Information Table 24. Ordering Information Ordering Code CY7C68053-56BAXI Development Tool Kit CY3687 MoBL-USB FX2LP18 Development Kit Package Type 56 VFBGA– Pb-free RAM Size 16K # Prog I/Os 24 8051 Address/Data Buses – 11. Package Diagram The FX2LP18 is available in a 56-pin VFBGA package. Figure 26. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 TOP VIEW BOTTOM VIEW Ø0.05 M C PIN A1 CORNER Ø0.15 M C A B Ø0.30±0.05(56X) A1 CORNER 12 3 4 5 6 6 8 A B C D E F G H 87654321 A B C D E F G H 0.50 -B3.50 5.00±0.10 5.00±0.10 3.50 5.00±0.10 -A0.10(4X) 0.10 C 0.50 5.00±0.10 SIDE VIEW 0.45 0.080 C REFERENCE JEDEC: MO-195C -C0.21 SEATING PLANE 0.160 ~0.260 1.0 max PACKAGE WEIGHT: 0.02 grams 001-03901-*B Document # 001-06120 Rev *I Page 37 of 40 [+] Feedback CY7C68053 12. PCB Layout Recommendations The following recommendations must be followed to ensure reliable high performance operation. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Bypass or flyback caps on VBus, near connector, are recommended. DPLUS and DMINUS trace lengths must be kept within 2 mm of each other in length, with preferred length of 20 to 30 mm. Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. It is preferable to have no vias placed on the DPLUS or DMINUS trace routing. Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. At least a four-layer impedance controlled board is required to maintain signal quality. Specify impedance targets (ask your board vendor what they can achieve). To control impedance, maintain trace widths and trace spacing to within specifications. Minimize stubs to minimize reflected signals. Connections between the USB connector shell and signal ground must be done near the USB connector. Document # 001-06120 Rev *I Page 38 of 40 [+] Feedback CY7C68053 Document History Page Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller Document Number: 001-06120 Rev. ** *A ECN No. 430449 434754 Submission Date 03/03/06 03/24/06 Orig. of Change OSG OSG New data sheet In Section 3.3, stated that SCL and SDA pins can be connected to VCC or VCC_IO Chnged sections 3.5, 3.18.1 and pin descriptions of SCL, SDA to indicate that since DISCON=1 after reset, an EEPROM or EEPROM emulation is required on the I2C interface In pin description table, renamed pin 2H (Reserved) to Ground In Section 6, added statement “The GPIO’s are not over voltage tolerant, except the SCL and SDA pins, which are 3.3V tolerant“ In Section 8,added a footnote to the DC char table stating that AVcc can be floated in low power mode In Section 8, changed VIHmax in DC char table from 3.6V to VCC_IO + 10% Changed the recommendation for the pull up resistors on I2C Split Icc into 4 different values, corresponding to the different voltage supplies Changed Isus typical to 20uA and 220uA Added section 3.9.3 on suspend current considerations Removed all references the part number CY7C68055. Corrected the bullet in Features to state that 24 GPIO’s are available. Added the Test ID (TID#) to the Features on the front page. Made changes to the block diagram on the first page (this is now a Visio drawing instead of a Framemaker drawing). Corrected the Ambient Temperature with Power Supplied. Moved figure titles to meet the new template. Checked grammar. Took out 9-bit address bus from the block diagram on the first page. Corrected Figure 4.1 Added Icc data in DC Characteristics and Maximum Power dissipation Changed ESD spec to 1500V Changed ESD spec to 2000V and 1500V only for SCL and SDA pins. Added min spec for tOEoff Changed Icc and power dissipation numbers Description of Change *B 465471 See ECN OSG *C 484726 See ECN ARI *D *E *F 492009 500408 502115 See ECN See ECN See ECN OSG OSG OSG *G 1128404 See ECN OSG/ARI Removed SLCS from figure in Section 9.6 Slave FIFO Asynchronous Write Changed SLWR Pulse HIGH parameter to 50ns Section 9.13.1 - Removed the indication that SLCS and SLRD can be asserted together Section 9.13.3 - Removed the indication that SLCS and SLRD can be asserted together Implemented the latest template. AESA ODC Section 7 - Changed -0°C to -40°C Deleted Note on AVcc parameter in DC Characteristics table *H *I 1349903 2728476 See ECN 07/02/09 Document # 001-06120 Rev *I Page 39 of 40 [+] Feedback CY7C68053 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com © Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document # 001-06120 Rev *I Revised July 02, 2009 Page 40 of 40 Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. MoBL-USB FX2LP18, EZ-USB FX2LP and ReNumeration are trademarks, and MoBL-USB is a registered trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback