CY7C68300A-56PVXC

This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A EZ-USB AT2™ USB 2.0 To ATA/ATAPI Bridge 1.0 Features • Complies with USB-IF specifications for USB 2.0, the USB Mass Storage Class, and the USB Mass Storage Class Bulk-Only Transport Specification • Operates at high (480-Mbps) or full (12-Mbps) speed • Complies with T13’s ATA/ATAPI-6 Draft Specification • Supports 48-bit addressing for large hard drives • Supports PIO modes 0, 3, 4, and UDMA modes 2, 4 • Uses one external serial EEPROM containing the USB device serial number, vendor and product identification data, and device configuration data • ATA interface IRQ signal support • Support for a single ATA/ATAPI device configured either as master or slave • “ATA-Enable” input signal, which three-states all signals on the ATA interface in order to allow sharing of the bus with another controller (e.g., an IEEE-1394 to ATA bridge chip) • Support for board-level manufacturing test via USB interface • 3.3V operation for self-powered devices • 56-pin SSOP and 56-pin QFN packages 2.0 Introduction The CY7C68300A implements a fixed-function bridge between one USB port and one ATA- or ATAPI-based mass storage device port. This bridge adheres to the Mass Storage Class Bulk-Only Transport Specification and is intended for self-powered devices. The USB port of the CY7C68300A is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the CY7C68300A SCL RESET I2C-Compatible Bus Controller SDA 24 MHz XTAL PLL ATA_EN (ATA Interf ace 3-state) AT2 Internal Logic ATA Interf ace ControlSignals Control ATA 16 Bit ATA Data Interf ace Logic VBUS D+ D- USB 2.0 XCVR CY Smart USB FS/HS Engine 4kBy teFIFO Data Figure 1-1. Block Diagram Cypress Semiconductor Corporation Document #: 38-08031 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 15, 2005 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A and receives status and data from the CY7C68300A using standard USB protocol. The ATA/ATAPI port of the CY7C68300A is connected to a mass storage device. A 4-Kbyte buffer maximizes ATA/ATAPI data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0, 3, and 4, and Ultra DMA modes 2 and 4. The device initialization process is configurable, enabling the CY7C68300A to initialize ATA/ATAPI devices without software intervention. 3.0 3.1 Pin Assignments Pin Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DD13 DD14 DD15 GND NC Vcc GND IORDY DMARQ AVcc XTALOUT XTALIN AGND Vcc DPLUS DMINUS GND Vcc GND PU10K RESERVED SCL SDA Vcc DD0 DD1 DD2 DD3 DD12 DD11 DD10 DD9 DD8 ATA_EN Vcc RESET# GND ARESET# VBUS_PWR_VALID CS1# 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 EZ-USB AT2 CY7C68300A 56-pin SSOP CS0# DA2 DA1 DA0 INTRQ Vcc DMACK# DIOR# DIOW# GND Vcc GND DD7 DD6 DD5 DD4 Figure 3-1. 56-pin SSOP Document #: 38-08031 Rev. *E Page 2 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A ATA_EN 44 DD15 DD14 DD13 DD12 DD11 DD10 GND GND VCC 56 55 54 53 52 51 50 49 48 47 46 45 IORDY DMARQ AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VCC GND PU10K RESERVED 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 43 42 41 40 39 38 VCC DD9 DD8 NC RESET# GND ARESET# VBUS_PWR_VALID CS1# CS0# DA2 DA1 DA0 INTRQ VCC DMACK# DIOR# DIOW# EZ-USB AT2 CY7C68300A 56-pin QFN 37 36 35 34 33 32 31 30 29 GND Figure 3-2. 56-pin QFN Pin Descriptions SSOP QFN Pin Pin Pin Name 1 2 3 4 5 6 7 8 9 10 50 51 52 53 54 55 56 1 2 3 DD13 DD14 DD15 GND NC VCC GND IORDY DMARQ AVCC PWR GND I[1] I[1] PWR I I Pin Type I/O[1] I/O[1] I/O[1] GND Hi-Z Default State at Start-up Hi-Z Hi-Z Hi-Z ATA Data bit 13. ATA Data bit 14. ATA Data bit 15. Ground. Reserved. This pin should remain a no-connect. VCC. Connect to 3.3V power source. Ground. ATA Control. ATA Control. Analog VCC. Connect the VCC through the shortest path possible. Pin Description Note: 1. ATA interface pins are not active when ATA_EN is not asserted. Document #: 38-08031 Rev. *E GND VCC VCC SDA DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 SCL Page 3 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Pin Descriptions (continued) SSOP QFN Pin Pin Pin Name 11 12 13 14 15 4 5 6 7 8 XTALOUT XTALIN AGND VCC DPLUS Pin Type Xtal Xtal GND PWR I/O Default State at Start-up Xtal Xtal Pin Description 24-MHz Crystal Output (see section 3.2.3). 24-MHz Crystal Input (see section 3.2.3). Analog Ground. Connect to ground with as short a path as possible. VCC. Connect to 3.3V power source. Pulled high when Reset is USB D+ Signal (see section 3.2.1). active. When Reset is released, the pull-up is controlled by pin 46(SSOP)/ 39(QFN). When VBUS_ PWR_VALID is high, the line is pulled up. VBUS_PWR _VALID is polled at start-up and then every 20 ms. Hi-Z USB D- Signal (see section 3.2.1). Ground. VCC. Connect to 3.3V power source. Ground. Hi-Z Tied to 10k ± 5% pull-up resistor. Reserved. Tie to GND. O I/O PWR I/O I/O I/O I/O I/O I/O I/O I/O GND PWR GND O/Z[1] O/Z [1] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 DMINUS GND VCC GND PU10K RESERVE D SCL SDA VCC DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 GND VCC GND DIOW#[2] DIOR# DMACK# VCC INTRQ DA0 DA1 DA2 CS0# CS1# I/O GND PWR GND SCL/SDA will be active for Clock signal for I2C-compatible interface (see section several ms at start-up. Then 3.2.2). driven high. Data signal for I2C-compatible interface (see section 3.2.2). VCC. Connect to 3.3V power source. Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z ATA Data bit 0. ATA Data bit 1. ATA Data bit 2. ATA Data bit 3. ATA Data bit 4. ATA Data bit 5. ATA Data bit 6. ATA Data bit 7. Ground. VCC. Connect to 3.3V power source. Ground. Driven high (CMOS) Driven high (CMOS) Input ATA Control. ATA Control. ATA Control. VCC. Connect to 3.3V power source. IDE ATA Interrupt request. O/Z[1] Driven high (CMOS) PWR I[1] O/Z[1] Driven high after 2 ms delay ATA Address. O/Z[1] Driven high after 2 ms delay ATA Address. O/Z[1] Driven high after 2 ms delay ATA Address. O/Z[1] Driven high after 2 ms delay ATA Chip Select. O/Z[1] Driven high after 2 ms delay ATA Chip Select. Document #: 38-08031 Rev. *E Page 4 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Pin Descriptions (continued) SSOP QFN Pin Pin Pin Name 46 47 48 49 39 40 41 42 VBUS_PW R_VALID ARESET# GND RESET# Pin Type I O/Z[1] GND I Default State at Start-up Input Pin Description VBUS detection. Indicates to the CY7C68300A that VBUS power is present. ATA Reset. Ground. Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC through a 100K resistor, and to GND through a 0.1-µF capacitor, supplying a 10-ms reset. VCC. Connect to 3.3V power source. Input – If CY7C68300A is not in mfg mode, polled every 20 ms after start-up. If LOW, SSOP pins 36–38, 41–45 and 47 or QFN pins 29–31, 34–38 and 40 are threestated. Hi-Z Hi-Z Active HIGH. ATA interface enable. Allows ATA bus sharing with other host devices. Setting ATA_EN = 1 enables the ATA interface for normal operation. Disabling ATA_EN three-states (High-Z) the ATA interface and halts the ATA interface state machine logic. 50 51 43 44 VCC ATA_EN PWR I 52 53 54 55 56 45 46 47 48 49 DD8 DD9 DD10 DD11 DD12 I/O[1] Hi-Z I/O[1] I/O[1] I/O[1] Hi-Z I/O[1] Hi-Z ATA Data bit 8. ATA Data bit 9. ATA Data bit 10. ATA Data bit 11. ATA Data bit 12. 3.2 3.2.1 Additional Pin Descriptions DPLUS, DMINUS 20pF 24MHz crystal DPLUS and DMINUS are the USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB. 3.2.2 SCL, SDA 20pF The clock and data pins for the I2C-compatible port should be connected to your configuration EEPROM and to VCC through 2.2k resistors. 3.2.3 XTALIN, XTALOUT Figure 3-3. XTALIN, XTALOUT Diagram ATA_EN signal could be detected properly under all circumstances. The CY7C68300A will behave in the following manner: • If ATA_EN transitions to '0' during normal operation, the CY7C68300A will disconnect from the USB and drop to a low-power mode. • If ATA_EN transitions to '1' when in low-power mode and no other condition is causing the low-power state, the CY7C68300A will return to a post-reset state and reconnect to the USB. • If the CY7C68300A is already in suspend and ATA_EN transitions to '0', the CY7C68300A will resume only long enough to stop driving the ATA interface (High-Z) and drop back to low-power again. • If the CY7C68300A is already in suspend and ATA_EN transitions to '1', the CY7C68300A will resume only long enough to start driving the ATA interface and drop to lowpower again. The CY7C68300A requires a 24-MHz signal to derive internal timing. Typically a 24-MHz parallel-resonant fundamental mode crystal is used, but a 24-MHz square wave from another source can also be used. If a crystal is used, connect the pins to XTALIN and XTALOUT, and also through 20-pF capacitors to GND. If an alternate clock source is used, apply it to XTALIN and leave XTALOUT open. 3.2.4 ATA_EN ATA_EN allows bus sharing with other host devices. Setting ATA_EN = 1 enables the ATA interface for normal operation. Setting ATA_EN = 0 disables (High-Z) the ATA interface pins and removes the CY7C68300A from the USB. Because the CY7C68300A supports a true low-power USB suspend state, new functionality was added to ensure that transitions of the Note: 2. A # sign after the signal name indicates that it is an active LOW signal. Document #: 38-08031 Rev. *E Page 5 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A The ATA_EN pin is sampled at a rate of 50 times per second by the CY7C68300A internal logic. This pin should be set to a HIGH at start-up. Note that disabling the ATA bus with the ATA_EN pin during the middle of a data transfer will result in data loss and can cause the operating system on the Host computer to crash. 3.2.5 ATA Interface Pins • High speed, with a signaling bit rate of 480 Mbits/sec. CY7C68300A does not support the low-speed signaling rate of 1.5 Mbits/sec. 5.2 ATA Interface If a cable is used to connect the CY7C68300A to a UDMA device, the cable must be an 80-pin cable as shown in the ATA-6 spec, Annex A. 3.2.6 VBUS_PWR_VALID VBUS_PWR_VALID indicates to the CY7C68300A that power is present on VBUS. This pin is polled by the CY7C68300A at start-up and then every 20ms thereafter. If this pin is ‘1’, the 1.5K pull-up is attached to D+. If this pin is ‘0’, the CY7C68300A will release the pullup on D+ as required by the USB specification. 3.2.7 RESET# The ATA/ATAPI port on the CY7C68300A is compliant with the Information Technology AT Attachment with Packet Interface 6 (ATA/ATAPI-6) Specification, T13/1410D Rev 3B. The CY7C68300A supports ATAPI packet commands over USB. Additionally, the CY7C68300A translates ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices with generic Mass Storage Class Bulk Only Transport drivers. 6.0 Enumeration Asserting RESET# for 10 ms will reset the entire chip. This pin is normally tied to VCC through a 100k resistor, and to GND through a 0.1-µF capacitor. During the power-up sequence, internal logic checks the I2Ccompatible port for an EEPROM whose first two bytes are both 0x4D. If a valid signature is found, the CY7C68300A uses the values stored in the EEPROM to configure the USB descriptors for normal operation. If an invalid EEPROM signature is read, or if no EEPROM is detected, the CY7C68300A defaults into Board Manufacturing Test Mode. The two modes of operation are described in subsections 6.1 and 6.2, below. 6.1 R8 100K NRESET C1 0.1 uFd Board Manufacturing Test Mode Figure 3-4. Typical Reset Circuit In Board Manufacturing Test Mode, the chip behaves as a USB 2.0 device but the ATA/ATAPI interface is not active. The CY7C68300A allows for reading and writing an EEPROM and for board level testing through vendor specific ATAPI commands utilizing the CBW Command Block as described in the USB Mass Storage Class Bulk-Only Transport Specification. There is a vendor-specific ATAPI command for the EEPROM access (CfgCB) and one for the board level testing (MfgCB). 6.1.1 CfgCB 4.0 Applications The CY7C68300A is a high-speed USB 2.0 peripheral device that connects a single ATA or ATAPI storage device to a USB host using the USB Mass Storage Class protocol. 4.1 Additional Resources • CY4615 EZ-USB AT2 Reference Design Kit • USB Specification version 2.0 • ATA Specification T13/1410D Rev 3B • USB Mass Storage Class Bulk Only Transport Specification, http://www.usb.org/developers/data/devclass/ usbmassbulk_10.pdf. The cfg_load and cfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this CfgCB is shown below. Byte 0 will be a vendor-specific command designator whose value is configurable and set in the configuration data (EEPROM address 0x04). Byte 1 must be set to 0x26 to identify CfgCB. Byte 2 is reserved and must be set to zero. Byte 3 is used to determine the memory source to write/read. For the CY7C68300A, this byte must be set to 0x02, meaning the EEPROM. Bytes 4 and 5 will be used to determine the start address. For the CY7C68300A, this must always be 0x0000. Bytes 6 through 15 are reserved and should be set to zero. The data transferred to the EEPROM must be in the format specified in Table 6-6 of this data sheet. Maximum data transfer size is 255 bytes. The data transfer length is determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransferLength) of the CBW. The type/direction of the command will be determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW. 5.0 5.1 Functional Overview USB Signaling Speed CY7C68300A operates at two of the three rates defined in the USB Specification Revision 2.0 dated April 27, 2000: • Full speed, with a signaling bit rate of 12 Mbits/sec Document #: 38-08031 Rev. *E Page 6 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-1. Command Block Wrapper 7 0–3 4–7 8–11 (08h-0Bh) 12 (0Ch) Dir 13 (0Dh) 14 (0Eh) 15–30 (0Fh1Eh) Table 6-2. Example CfgCB CfgCB Byte Descriptions 7 0 bVSCBSignature (set in configuration bytes) 1 bVSCBSubCommand (must be 0x26) 2 Reserved (must be set to zero) 3 Data Source (must be set to 0x02) 4 Start Address (LSB) (must be set to zero) 5 Start Address (MSB) (must be set to zero) 6–15 Reserved (must be set to zero) 6.1.2 MfgCB 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 5 1 1 0 0 0 0 0 4 0 0 0 0 0 0 0 Bits 3 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Obsolete Reserved (0) Reserved (0) CBWCB (CfgCB or MfgCB) 6 5 4 dCBWTag dCBWDataTransferLength bwCBWFLAGS Reserved (0) bCBWLUN bCBWCBLength 3 2 1 0 DCBWSignature 6.1.2.1 Mfg_load During a mfg_load, the CY7C68300A goes into Manufacturing Test Mode. Manufacturing Test Mode is provided as a means to implement board or system level interconnect tests. During Manufacturing Test Mode operation, all outputs not directly associated with USB operation are controllable. Normal control of the output pins are disabled. Control of the select CY7C68300A IO pins and their three-state controls are mapped to the ATAPI data packet associated with this request. (See the following table for explanation of the required mfg_load data format.) This requires a write of seven bytes. To exit Manufacturing Test Mode, a hard reset (#RESET) is required. The mfg_load and mfg_read vendor-specific commands will be passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this MFGCB is shown below. Byte 0 is a vendor-specific command designator whose value is configurable and set in the configuration data. Byte 1 must be 0x27 to identify MfgCB. Byte 2–15 are reserved and must be set to zero. The data transfer length will be determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransferLength) of the CBW. The type/direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW. Table 6-3. Example MfgCB MfgCB Byte Description 0 bVSCBSignature (set in configuration bytes) 1 bVSCBSubCommand (hardcoded 0x27) 2–15 Reserved (must be zero) 0 0 0 Bits 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 Document #: 38-08031 Rev. *E Page 7 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-4. Mfg_load Data Format Byte 0 0 0 0 0 1 1 1 1 1 2 3 4 5 6 Bit(s) 0 3:1 5:4 6 7 0 1 2 3:6 7 7:0 7:0 7:0 7:0 7:0 Reserved DA[2:0] CS#[1:0] Reserved ARESET# NDIOW NDIOR NDMACK Reserved DD[15:0] Three-state (0 = three-state DD pins, 1 = enable DD pins). DD[7:0] DD[15:8] Reserved Reserved Reserved Test/Three-state Control Function 6.1.2.2 Mfg_read This USB request returns a “snapshot in time” of select CY7C68300A input pins. The input pin states are bit-wise mapped to the ATAPI data associated with this request. CY7C68300A input pins not directly associated with USB operation can be sampled at any time during Manufacturing Test Mode operation. See the following table for an explanation of the mfg_read data format. The data length shall always be eight bytes. Table 6-5. Mfg_read Data Format Byte 0 0 0 0 1 1 1 1 1 1 2 3 4 5 6 7 Bit(s) 0 5:1 6 7 2:0 3 4 5 6 7 7:0 7:0 7:0 7:0 7:0 7:0 INTRQ Reserved. This data should be ignored. VBUS_PWR_VALID ARESET# (output value only) Reserved. This data should be ignored. IORDY DMARQ ATA_EN Reserved. This data should be ignored. DD[15:0] Three-state DD[7:0] DD[15:8] Reserved. This data should be ignored. Reserved. This data should be ignored. Reserved. This data should be ignored. Reserved. This data should be ignored. 6.2 Normal Operation Mode In Normal Operation Mode, the chip behaves as a USB 2.0 to ATA/ATAPI bridge. This includes all typical USB device states (powered, configured, etc.). The USB descriptors are returned according to the values stored in the external EEPROM. An external EEPROM is required for Mass Storage Class BulkOnly Transport compliance, since a unique serial number is required for each device. Also, Cypress requires customers to use their own Vendor and Product IDs for final products. Test/Three-state Control Function Document #: 38-08031 Rev. *E Page 8 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A 6.3 EEPROM Organization The contents of the 256-byte (2048-bit) two-wire serial EEPROM are arranged as follows. The column labeled “Required Contents” contains the values that must be used for proper operation of the CY7C68300A. The column labeled “Suggested Contents” contains suggested values for the bytes that are defined by the manufacturer. Some values, such as Table 6-6. EEPROM Organization EEPROM Address Configuration 0x00 0x01 0x02 I2C-compatible memory device signature (LSB) I2C-compatible memory device signature (MSB) APM Value LSB I2C-compatible memory device signature byte. MSB I2C-compatible memory device signature byte. ATA Device Automatic Power Management Value. If an attached ATA device supports APM and this field contains other than 0x00, the CY7C68300A will issue a SET_FEATURES command to Enable APM with this value during the drive initialization process. Setting APM Value to 0x00 disables this functionality. This value is ignored with ATAPI devices. Time in 128-ms granularity before the CY7C68300A stops polling the ALT STAT register for reset complete and restarts the reset process (0x80 = 16.4 seconds). Value in the first byte of the CBW CB field that designates that the CB is t o be decoded as vendor specific ATA commands instead of the ATAPI command block. See section 5.0 for more detail on how this byte is used. Bits(7:4) Set to 0 Bit (3) Enables a delay of up to 120 ms at each read of the DRQ bit where the device data length does not match the host data length. This allows the CY7C68300A to work with most devices that incorrectly clear the BUSY bit before a valid status is present. Bit (2) Determines if a short packet is sent prior to the STALL of an IN endpoint. The USB Mass Storage Class Bulk-Only Specification allows a device to send a short or zero-length IN packet prior to returning a STALL handshake for certain cases. Certain host controller drivers may require a short packet prior to STALL. 1 = Force a short packet before STALL. 0 = Don’t force a short packet before STALL. Bit (1) Determines if the CY7C68300A is to do a SRST reset during drive initialization.[3] 1 = Perform SRST during initialization. 0 = Don’t perform SRST during initialization. Bit (0) Skip ATA_NRESET assertion.[4] 0 = Allow ARESET# assertion for all resets. 1 = Disable ARESET# assertion except for power-on reset cycles. 0x4D 0x4D 0x00 Field Name Field Description Required Suggested Contents Contents the Vendor ID and device and device serial number, must be customized to meet USB compliance. See section 6.1 for details on how to use vendor-specific ATAPI commands to read and program the EEPROM. The serial EEPROM must be hard-wired to address 0x04. This means that A0 and A1 of the serial EEPROM must be tied to ground and that A2 must be tied to 3.3V. 0x03 ATA Initialization Timeout 0x80 0x04 ATA Command Designator 0x24 0x05 Reserved BUSY Bit Delay 0x07 Short Packet Before Stall SRST Enable Skip Pin Reset Notes: 3. At least one reset must be enabled. Do not set SRST to 0 and Skip Pin Reset to 1at the same time. 4. SRST Enable must be set in conjunction with Skip Pin Reset. Setting this bit causes the CY7C68300A to bypass ARESET# during initialization. All reset events except a power-on reset utilize SRST as the drive mechanism. Document #: 38-08031 Rev. *E Page 9 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0x06 Field Name ATA UDMA Enable Field Description Bit (7) Enable Ultra DMA data transfer support for ATAPI devices. If enabled, and if the ATAPI device reports UDMA support for the indicated modes, the CY7C68300A will utilize UDMA data transfers at the highest negotiated rate possible. 0 = Disable ATA device UDMA support. 1 = Enable ATA device UDMA support. Bit (6) Enable Ultra DMA data transfer support for ATAPI devices. If enabled, and if the ATAPI device reports UDMA support for the indicated modes, the CY7C68300A will utilize UDMA data transfers at the highest negotiated rate possible. 0 = Disable ATAPI device UDMA support. 1 = Enable ATAPI device UDMA support. Bit (5:0) These bits select which UDMA modes, if supported, are enabled. Setting to 1 enables. Multiple bits may be set. The CY7C68300A will operate in the highest enabled UDMA mode supported by the device. The CY7C68300A supports UDMA modes 2 and 4 only. Bit Descriptions 5 Reserved. Must be set to 0. 4 Enable UDMA mode 4. 3 Reserved. Must be set to 0. 2 Enable UDMA mode 2. 1 Reserved. Must be set to 0. 0 Reserved. Must be set to 0. Bits(7:2) Bits(1:0) These bits select which PIO modes, if supported, are enabled. Setting to 1 enables. Multiple bits may be set. The CY7C68300A will operate in the highest enabled PIO mode supported by the device. The CY7C68300A supports PIO modes 0, 3, and 4 only. PIO mode 0 is always enabled by internal logic. Bit Descriptions 1 Enable PIO mode 4. 0 Enable PIO mode 3. Must be set to 0x00. Must be set to 0x00. Must be set to 0x00. Must be set to 0x00. Must be set to 0x00. Must be set to 0x00. Must be set to 0x00. Must be set to 0x00. Length of device descriptor in bytes. Descriptor type. USB Specification release number in BCD. Device class. Device subclass. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x12 0x01 0x00 0x02 0x00 0x00 Page 10 of 21 0x03 Required Suggested Contents Contents 0xD4 ATAPI UDMA Enable UDMA Modes 0x07 Reserved PIO Modes 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved bLength bDescriptor Type bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass Device Descriptor Document #: 38-08031 Rev. *E This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E Field Name bDeviceProtocol bMaxPacketSize0 idVendor (LSB) idVendor (MSB) idProduct (LSB) idProduct (MSB) bcdDevice (LSB) bcdDevice (MSB) iManufacturer Device release number in BCD LSB (product release number). Device release number in BCD MSB (silicon release number). Index to manufacturer string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Index to product string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Index to serial number string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. The USB Mass Storage Class Bulk-Only Transport Specification requires a unique serial number (in upper case, hexidecimal characters) for each device. Number of configurations supported. Length of device descriptor in bytes. Type Descriptor type. USB Specification release number in BCD. USB Specification release number in BCD. Device class. Device subclass. Device protocol. USB packet size supported for default pipe. Number of configurations supported. Reserved for future use. Must be set to zero. Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x01. Index to the configuration string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x01 0x0A 0x06 0x00 0x02 0x00 0x00 0x00 0x40 0x01 0x00 0x09 0x02 0x20 0x00 0x01 0x01 0x00 Device protocol. USB packet size supported for default pipe. Vendor ID. Cypress’s Vendor ID may only be used for evaluation purposes, and not in released products. Product ID. Field Description Required Suggested Contents Contents 0x00 0x40 0xB4 0x04 0x30 0x68 0x01 0x00 0x38 0x1F iProduct 0x4E 0x20 iSerialNumber 0x64 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 bNumConfigurations bLength bDescriptor bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 bNumConfigurations bReserved bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration Device Qualifier High-speed Configuration Descriptor Document #: 38-08031 Rev. *E Page 11 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0x33 Field Name bmAttributes Field Description Device attributes for this configuration. Bit Descriptions 7 Reserved. Must be set to 1. 6 Self-powered. Must be set to 1. 5 Remote wake-up. Must be set to 0. 4–0 Reserved. Must be set to 0. Maximum power consumption for this configuration. Units used are mA*2 (i.e., 0x31 = 98 mA, 0xF9 = 498 mA). 0x00 reported for self-powered devices. Required Suggested Contents Contents 0xC0 0x34 bMaxPower 0x00 High-speed Interface and Endpoint Descriptors Interface Descriptor 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate setting. Number of endpoints. Interface class. Interface subclass. Interface protocol. Index to first interface string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 8. This is a bulk endpoint. Max data transfer size. HS interval for polling (max. NAK rate). Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. HS interval for polling (max. NAK rate). Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The value to use as an argument to Set Configuration to select the configuration. 0x07 0x05 0x88 0x02 0x00 0x02 0x00 0x07 0x05 0x02 0x02 0x00 0x02 0x00 0x09 0x02 0x20 0x00 0x01 0x01 0x50 0x00 0x09 0x04 0x00 0x00 0x02 0x08 0x06 USB Bulk In Endpoint 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value USB Bulk Out Endpoint Full-speed Configuration Descriptor Document #: 38-08031 Rev. *E Page 12 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0x52 Field Name iConfiguration Field Description Index to configuration string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Device attributes for this configuration. Bit Descriptions 7 Reserved. Must be set to 1. 6 Self-powered. Must be set to 1. 5 Remote wake-up. Must be set to 0. 4–0 Reserved. Must be set to 0. Maximum power consumption for the second configuration. Units used are mA*2 (i.e., 0x31 = 98 mA, 0xF9 = 498 mA). 0xC0 Required Suggested Contents Contents 0x00 0x53 bmAttributes 0x54 bMaxPower 0x00 Full-speed Interface and Endpoint Descriptors Interface Descriptor 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D bLength bDescriptorType bInterfaceNumber bAlternateSettings bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate settings. Number of endpoints. Interface class. Interface subclass. Interface protocol. Index to first interface string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 8. This is a bulk endpoint. Max data transfer size. Does not apply to FS bulk endpoints. Must be set to 0. Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. Does not apply to FS bulk endpoints. Must be set to 0. 0x50 0x00 0x09 0x04 0x00 0x00 0x02 0x08 0x06 USB Bulk InEndpoint 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval 0x07 0x05 0x88 0x02 0x40 0x00 0x00 0x07 0x05 0x02 0x02 0x40 0x00 0x00 USB Bulk Out Endpoint String Descriptor Examples (Note: The values in these strings are given as examples only and should not be used in final products. Designers are encouraged to modify the string values to reflect the final product, since they are what users will see with their operating systems.) USB String Descriptor–Index 0 (LANGID) 0x6C 0x6D bLength bDescriptorType LANGID string descriptor length in bytes. Descriptor type. 0x04 0x03 Document #: 38-08031 Rev. *E Page 13 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 Field Name LANGID (LSB) LANGID (MSB) bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString String descriptor length in bytes (including bLength). Descriptor type. Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. 0x03 “C” 0x43 0x00 “y” 0x79 0x00 “p” 0x70 0x00 “r” 0x72 0x00 “e” 0x65 0x00 “s” 0x73 0x00 “s” 0x73 0x00 “ ” 0x20 0x00 “S” 0x53 0x00 “e” 0x65 0x00 “m” 0x6D 0x00 “i” 0x69 0x00 “c” 0x63 0x00 “o” 0x6F 0x00 “n” 0x6E 0x00 “d” 0x64 0x00 “u” 0x75 0x00 “c” 0x63 0x00 “t” 0x74 Field Description Language supported.[5] Required Suggested Contents Contents 0x09 0x04 0x2C USB String Descriptor–Manufacturer Note: 5. See http://www.usb.org for LANGID documentation (the code for English is 0x0409). Document #: 38-08031 Rev. *E Page 14 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 bString bString bString bString bString bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString Field Name (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) String descriptor length in bytes (including bLength). Descriptor type. Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. 0x03 “U” 0x55 0x00 “S” 0x53 0x00 “B” 0x42 0x00 “2” 0x32 0x00 “.” 0x2E 0x00 “0” 0x30 0x00 “ ” 0x20 0x00 “S” 0x53 0x00 “t” 0x74 0x00 “o” 0x6F 0x00 “r” 0x72 0x00 “a” 0x61 0x00 “g” 0x67 0x00 “e” 0x65 0x00 “ ” 0x20 0x00 “D” 0x44 0x00 “e” 0x65 0x00 “v” 0x76 Field Description Required Suggested Contents Contents 0x00 “o” 0x6F 0x00 “r” 0x72 0x00 0x2C USB String Descriptor–Product Document #: 38-08031 Rev. *E Page 15 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 bString bString bString bString bString bString bString Field Name (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Field Description Required Suggested Contents Contents 0x00 “i” 0x69 0x00 “c” 0x63 0x00 “e” 0x65 0x00 USB String Descriptor–Serial Number (Note: The USB Mass Storage Class requires a unique serial number in each device. Not providing a unique serial number will crash the operating system. The serial number must be at least a minimum size of 12 characters. Some hosts will only treat the last 12 characters of the serial number as unique.) 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 bLength bDescriptor Type bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString String descriptor length in bytes (including bLength). Descriptor type. Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) Unicode character. (“NUL”) 0x03 “1” 0x31 0x00 “2” 0x32 0x00 “3” 0x33 0x00 “4” 0x34 0x00 “5” 0x35 0x00 “6” 0x36 0x00 “7” 0x37 0x00 “8” 0x38 0x00 “9” 0x39 0x00 “0” 0x30 0x00 “A” 0x41 0x00 “B” 0x42 0x00 “C” 0x43 0x00 “D” 0x44 0x00 “E” 0x45 0x00 “F” 0x46 0x00 Page 16 of 21 0x22 Document #: 38-08031 Rev. *E This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Table 6-6. EEPROM Organization (continued) EEPROM Address 0xEA to 0xFF Field Name Unused ROM Space Field Description Amount of unused ROM space will vary depending on strings. Required Suggested Contents Contents 0xFF 7.0 PCB Layout Recommendations The following recommendations should be followed to ensure reliable high-performance operation. • At least a four-layer impedance controlled boards are required to maintain signal quality. • Specify impedance targets (ask your board vendor what they can achieve). • To control impedance, maintain trace widths and trace spacing. • Minimize stubs to minimize reflected signals. • Connections between the USB connector shell and signal ground must be done near the USB connector. • Bypass/flyback caps on VBus, near connector, are recommended. • DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 2030mm. • Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. • It is preferred is to have no vias placed on the DPLUS or DMINUS trace routing. • Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. Source for recommendations: • EZ-USB FX2 PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX 2_PCB.pdf. • High-speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf. 8.0 Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the CY7C68300A through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of Via. A Via is a plated through-hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each Via to resist solder flow into the Via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s MicroLeadFrame (MLF) Technology.” This application note can be downloaded from AMKOR’s website from the following URL http://www.amkor.com/products/notes_papers/MLF_AppNote _0301.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 8-1 below displays a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that “No Clean,” type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. 0.017” dia Solder Mask Cu Fill Cu Fill PCB Material 0.013” dia PCB Material Via hole for thermally connecting the QFN to the circuit board ground plane. This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 8-1. Cross-Section of the Area Underneath the QFN Package Document #: 38-08031 Rev. *E Page 17 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Figure 8-2 is a plot of the solder mask pattern and Figure 8-3 is an X-Ray image of the assembly (darker areas indicate solder.) 9.0 Other Design Considerations Certain design considerations must be followed to ensure proper operation of the CY7C68300A. 9.1 Proper Power-up Sequence Power must be applied to the CY7C68300A before, or at the same time as the ATA/ATAPI device. If power is supplied to the drive first, the CY7C68300A will start up in an undefined state. Designs that utilize separate power supplies for the CY7C68300A and the ATA/ATAPI device are not recommended. Figure 8-2. Plot of the Solder Mask (White Area) 9.2 IDE Removable Media Devices The CY7C68300A does not fully support IDE removable media devices. Changes in media state are not reported to the operating system so users will be unable to eject/reinsert media properly. This may result in lost or corrupted data. 9.3 Devices With Small Buffers Figure 8-3. X-ray Image of the Assembly The size of the ATA/ATAPI device’s buffer can greatly affect the overall data transfer performance. Care should be taken to ensure that devices have large enough buffers to handle the flow of data to/from the drive. The exact buffer size needed depends on a number of variables, but a good rule of thumb is: (aprox min buffer size) = (data rate) * (seek time + rotation time + other) where (other) may include things like time to switch heads, power-up a laser, etc. Devices with buffers that are too small to handle the extra data may perform considerably slower than expected. Document #: 38-08031 Rev. *E Page 18 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A 10.0 Absolute Maximum Ratings 11.0 Operating Conditions[6] Storage Temperature .................................. –65°C to +150°C Ambient Temperature with power supplied ....... 0°C to +70°C Supply Voltage to Ground Potential ............... –0.5V to +4.0V DC Input Voltage to Any Input Pin ................................5.25V DC Voltage Applied to Outputs in High-Z State ......................................–0.5V to VCC + 0.5V Power Dissipation .....................................................936 mW Static Discharge Voltage ...........................................> 2000V Max Output Current per IO port ...................................10 mA TA (Ambient Temperature Under Bias) ............. 0°C to +70°C Supply Voltage ...............................................+3.0V to +3.6V Ground Voltage ................................................................. 0V Fosc (Oscillator or Crystal Frequency) ..... 24 MHz ± 100 ppm .................................................................. Parallel Resonant 12.0 VCC VIH VIL II VOH VOL IOH IOL CIN ICC ICC ISUSP TRESET DC Characteristics Description Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Voltage High Output Voltage Low Output Current High Output Current Low Input Pin Capacitance Supply Current Supply Current Suspend Current Reset Time After Valid Power All but D+/D– Only D+/D– USB High Speed USB Full Speed Connected Disconnected VCC min = 3.0V 1.91 235 90 250 30 0 < VIN < VCC IOUT = 4 mA IOUT = –4 mA 2.4 0.4 4 4 10 15 260 150 400 180 Conditions Min. 3.0 2 –0.5 Typ. 3.3 Max. 3.6 5.25 0.8 + 10 Unit V V V µA V V mA mA pF pF mA mA µA µA ms Parameter 13.0 13.1 AC Electrical Characteristics USB Transceiver 13.2 ATA Timing Complies with the USB 2.0 specification. The ATA interface supports ATA PIO modes 0, 3, and 4, and Ultra DMA modes 2 and 4 per the ATA Specification T13/1410D Rev. 3B. 14.0 Ordering Information Part Number Package Type 56-pin SSOP 56-pin QFN CY7C68300A-56PVC CY7C68300A-56LFC CY7C68300A-56PVXC 56-pin Lead(Pb)-free SSOP CY7C68300A-56LFXC 56-pin Lead(Pb)-Free QFN CY4615A EZ-USB AT2 Reference Design Kit Note: 6. If an alternate clock source is input on XTALIN it must be supplied with standard 3.3V signaling characteristics and XTALOUT must be left floating. Document #: 38-08031 Rev. *E Page 19 of 21 This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A 15.0 Package Diagrams .020 28 1 0.395 0.420 0.292 0.299 DIMENSIONS IN INCHES MIN. MAX. 29 56 0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110 GAUGE PLANE .010 0.005 0.010 0.025 BSC 0.110 0.008 0.0135 0.008 0.016 0°-8° 0.024 0.040 51-85062-*C Figure 15-1. 56-lead Shrunk Small Outline Package 056 56-Lead QFN 8 x 8 MM LF56A TOP VIEW BOTTOM VIEW 0.08[0.003] A 7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] N 1 0.80[0.031] DIA. 2 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018] C SIDE VIEW E-PAD 7.70[0.303] 7.80[0.307] 7.90[0.311] 8.10[0.319] (PAD SIZE VARY BY DEVICE TYPE) 0.30[0.012] 0.50[0.020] 0°-12° 0.50[0.020] C 6.45[0.254] 6.55[0.258] 0.24[0.009] 0.60[0.024] (4X) SEATING PLANE Figure 15-2. 56-lead Quad Flatpack No Lead (8 x 8 mm) LF56A 16.0 Disclaimers, Trademarks, and Copyrights Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EZ-USB AT2 is a trademark, and EZ-USB is a registered trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-08031 Rev. *E Page 20 of 21 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 6.45[0.254] 6.55[0.258] 51-85144-*D This part is not recommended for new designs Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI Bridge for new designs CY7C68300A Document History Page Description Title: CY7C68300A EZ-USB AT2™ USB 2.0 to ATA/ATAPI Bridge Document Number: 38-08031 REV. ** *A ECN NO. 124022 124857 Issue Date 02/13/03 06/06/03 Orig. of Change GIR GIR New data sheet Updated overall language/layout for “Final” status Revised description of DPLUS pin in section 2.2 Revised text in sections 2.3.4, 2.3.5, and 2.3.6 Updated ISUSP and TRESET values in section 8.0 Updated Figure 15-2 to include new QFN package drawing number Swapped In and Out bulk endpoints in section 5.3 Minor Change - Rework existing package drawing to improve clarity. Corrected existing ordering part numbers. Added lead-free ordering part numbers Revised data sheet for new two-column format No longer recommended for new designs. Added the “Not Recommended” note at the top in a bigger font and clearer message. Description of Change *B *C 129094 285992 08/18/03 SEE ECN GIR GIR *D *E 384808 397209 SEE ECN SEE ECN GIR ARI Document #: 38-08031 Rev. *E Page 21 of 21