CY7C68310-80AC

CY7C68310 ISD-300LP™ Low-Power USB 2.0 to ATA/ATAPI Bridge IC 1.0 Features • Fixed-function mass storage device–requires no firmware code • USB Mass Storage Class Bulk-Only specification-compliant (version 1.0) • USB 2.0-certified (TID# 40001426) • Integrated USB transceiver • High-speed (480-Mbit) and full-speed (12-Mbit) support • USB Suspend/Resume, Remote Wakeup support • Two power modes of operation–self-powered and USB buspowered • Low power consumption allows for bus-powered operation • VBUS-powered CF support • True USB portable HDD support • Compact 80-pin TQFP package with a Lead-Free option • ATA/ATAPI-6 specification-compliant–provides support for mass storage devices larger than 137GB • 5V tolerant inputs, 3.3V output drive • Flexible USB descriptor and configuration retrieval sources 2 • I C-compatible serial ROM interface • ATA interface using vendor-specific ATA command (FBh) implemented on ATAPI or ATA device • Default on-chip ROM contents for manufacturing/development • 2-Kbyte SRAM data buffer for ATA/ATAPI data transfers • ATA interface supports ATA PIO modes 0–4, UDMA modes 0–4 (multiword DMA not supported). ATA interface operation mode is automatically selected during device initialization or manually programmed with I2C-compatible configuration data • Automatic detection of either Master or Slave ATA/ATAPI devices • Mode Page 5 Support–increased support for formatting removable media devices • ATA Interrupt support for ATAPI devices–offers more robust ATA support across OS platforms • System event notification via Vendor-specific ATA command • Input pin for media cartridge detection or ejection request • USB bus state indications (Reset, FS/HS mode of operation, Suspend/Resume, Bus/Self-powered) • Three General Purpose I/O (GPIO) pins • Multiple LUNs supported within a single ATAPI device • ATA translation provides seamless ATA support with standard MSC drivers • Additional ATA command support provided by vendorspecific ATACBs (ATA command blocks utilizing the MSC Command Block Wrapper) • Provisions to share ATA bus with other hosts (e.g. USB/1394 dual device) • Manufacturing interconnect test support provided with vendor-specific USB commands: • Read/Write access to relevant ASIC pins • Manufacturing Interconnect Test Tools • Utilizes inexpensive 30-Mhz crystal for clock source. 1.1 Functional Block Diagram VBUS D+ D- OSC nEJECT SYSIRQ DRVPWRVLD DISKRDY GPIO Pins (3) nRESET Control LOWPWR CY7C68310 Control Logic nPWR500 VBUSPWRVLD VBUSPWRD ROM 256 Byte EEPROM SCL SDA EEPROM Interface Control 64 Byte RAM 2kByte FIFO Bulk ATA Interface Logic ATAEN ATA Control Figure 1-1. Block Diagram Cypress Semiconductor Corporation Document 38-08030 Rev. *H • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 28, 2004 16-bit Data 30MHz Xtal USB USB HS/FS Control Logic USB 2.0 Xcvr CY7C68310 2.0 Applications 3.0 Introduction The CY7C68310 implements a USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage devices, such as: • Hard drives, including small form factor drives (2.5”, 1.8”, and 1.0”) designed for portable consumer electronics applications • CD-ROM, CD-R/W • DVD-ROM, DVD-RAM, DVD-R/W • MP3 players • Compact flash • Microdrives • Tape drives • Personal video recorders. The CY7C68310 implements a bridge between one USB port and one ATA/ATAPI-based mass storage device port. This bridge adheres to the Mass Storage Class Bulk-Only Transport specification, version 1.0. The USB port of the CY7C68310 is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the CY7C68310 and receives status and data from the CY7C68310 using standard USB protocol. The ATA/ATAPI port of the CY7C68310 is connected to a mass storage device. A 2-Kbyte buffer maximizes ATA/ATAPI data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0–4, and Ultra Mode DMA modes 0–4. The device initialization process is configurable, enabling the CY7C68310 to initialize most ATA/ATAPI devices without software intervention. The CY7C68310 can also be configured to allow software initialization of a device if initialization requirements are not supported by CY7C68310 algorithms. 2.1 • • • • Additional Resources CY4617 – CY7C68310 Mass Storage Reference Design Kit USB Specification version 2.0 ATA Attachment-6 with Packet Interface revision 3b USB Mass Storage Class Bulk-Only Transport specification, Rev. 1.0 4.0 4.1 Pin Assignments Pin Diagram DMARQ VDD33 DD3 VSS VDD25 DD15 DD0 DD2 DD12 DD14 DD13 DD11 DD4 DD10 VSS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD33 nDIOW nDIOR IORDY ATAPUEN nDMACK ATAIRQ DA1 VDD33 DA0 DA2 nCS0 nCS1 nPWR500 SCL SDA_nIMODE DISKRDY VBUSPWRD VBUSPWRVLD VDD25 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 VDD25 DD7 TMC2 TMC1 nATARST nRESET LOWPWR SCANEN GPIO2_nHS GPIO1 GPIO0 ATAEN DRVPWRVLD SYSIRQ nEJECT TEST3 VDD33 XO XI VSS CY7C68310-80AC DD6 DD8 30 29 28 27 26 25 24 23 22 21 TEST1 TEST2 DD5 VDD25 DD1 VDD33 DM RSDM VSS VSS RSDP PVDD25 AVSS AVDD25 AVSS VSS RPU DP VDD25 RREF Figure 4-1. 80-pin TQFP Document 38-08030 Rev. *H TEST0 AVSS DD9 Page 2 of 34 CY7C68310 4.2 Pin Overview Pin Name RPU RSDP DP DM RSDM TEST[0:3] XI XO nEJECT SYSIRQ DRVPWRVLD ATAEN Pin Direction O O I/O I/O O I I O I I I I Pin Type USB Output USB I/O USB I/O USB I/O USB I/O Pin Description D+ pull-up source. Power source for 1.5k pull-up resistor attached to D+ during full-speed operation. USB full-speed output buffer (D+). RSDP also functions as a current sink for termination during high-speed operation. USB high-speed I/O buffer (D+). USB high-speed I/O buffer (D-). USB full-speed output buffer (D-). RSDM also functions as a current sink for termination during high-speed operation. Pin Number 2 5 6 8 9 18–20, 25 22 23 26 27 28 29 5V-tolerant input Active HIGH. ASIC fabrication and manufacturing test mode select. buffer These pins must be tied to GND during normal operation. OSC input (2.5V-tolerant) OSC output 5V-tolerant Schmitt input 5V-tolerant Schmitt input 5V-tolerant Schmitt input 5V-tolerant Schmitt input 3.3V drive, 5V-tolerant, 6-mA IOL, Schmitt input 5V tolerant input buffer high-Z driver, 5V-tolerant, 6-mA IOL 5V-tolerant Schmitt input 3.3V drive, 5V-tolerant, 6-mA IOL 3.3V input 3.3V drive, 5V-tolerant, 6-mA IOL, Schmitt input 30-MHz crystal input. 30-MHz crystal output. Active LOW. Media eject or remote wakeup requested. Tie to +3.3V if functionality is not used. Active HIGH. USB interrupt request. Tie to GND if functionality is not used. Configurable polarity. Device Presence Detect. This pin must not be allowed to float if functionality is not utilized. Active HIGH. ATA interface enable. ‘1’ = normal ATA operation ‘0’ = High-Z ATA interface pins and ATA interface logic halted General purpose I/O pins. The GPIO pins must be tied to GND if functionality is not utilized. If the hs_indicator config bit is set, the GPIO2_nHS pin will reflect the operating speed of the device. ‘1’ = full-speed operation ‘0’ = high-speed operation Active HIGH. ASIC test pin. This pin must be tied to GND during normal operation. Active HIGH. USB suspend indicator. ‘0’ = Chip active. VBUS power up to 100 mA granted. ‘High-Z’ = Chip suspend. VBUS system current limited to USB suspend mode value. Active LOW. Asynchronous chip reset. Active LOW. ATA reset signal. 30–32 GPIO[0:1], GPIO2_nHS I/O 33 34 SCANEN LOWPWR I O 35 36 nRESET nATARST I O 37, 38 56, 54, 52, 49,46, 44, 42, 39, 41, 43, 45, 48, 51, 53, 55, 57 58 62 TMC[1:2] DD[0:15] I I/O Active HIGH. ASIC test pins. These pins must be tied to GND during normal operation. ATA data signals. DMARQ nDIOW I O 5V tolerant Schmitt input 3.3V drive, 5V-tolerant, 6-mA IOL ATA control signal. ATA control signal. Document 38-08030 Rev. *H Page 3 of 34 CY7C68310 4.2 Pin Overview (continued) Pin Name nDIOR Pin Direction O Pin Type 3.3V drive, 5V-tolerant, 6 mA IOL 5V-tolerant Schmitt input 3.3V drive, 5V-tolerant, 6 mA IOL 3.3V drive, 5V-tolerant, 6 mA IOL 5V-tolerant Schmitt input 3.3V drive, 5V-tolerant, 6 mA IOL 3.3V drive, 5V-tolerant, 6 mA IOL high-Z driver, 5V-tolerant, 6 mA IOL high-Z driver, 5V-tolerant, 6 mA IOL high-Z driver, 5V-tolerant, 6 mA IOL, Schmitt input 5V-tolerant Schmitt input 5V-tolerant Schmitt input 5V-tolerant Schmitt input Power Power Power Power Power Power Power ATA control signal. Pin Description Pin Number 63 64 65 IORDY ATAPUEN I O ATA control signal. ATA IORDY pull-up connection. For VBUS-powered systems. 66 nDMACK O ATA control signal. 67 70, 68, 71 ATAIRQ DA[0:2] I O ATA interrupt request. ATA address signals. 72, 73 nCS[0:1] O ATA chip select signals. 74 nPWR500 O Active LOW. VBUS power granted indicator. ‘0’ = VBUS power up to bMaxPower value ‘high-Z’ = bMaxPower value not granted (if more than 100 mA) I2C-compatible clock. This pin may be left as a no-connect pin if the I2C-compatible interface is not utilized. I2C-compatible address/data or nIMODE select. 75 SCL O 76 SDA_nlMODE I/O 77 78 DISKRDY VBUSPWRD I I Configurable polarity. Device ready. Active HIGH. Bus-powered operation select pin. ‘1’ = Bus powered ‘0’ = Self powered Active HIGH. Indicates that VBUS power is present. Digital ground. 2.5V digital supply. 3.3V digital supply. Analog 2.5V supply (PLL). Analog ground. PLL voltage reference. Current source for 2.4k (1%) resistor connected to AVSS. Analog 2.5V supply. 79 1, 4, 10, 21, 47, 60 3, 17, 40, 59, 80 7, 24, 50, 61, 69 11 12,14,16 13 15 VBUSPWRVLD VSS VDD25 VDD33 PVDD25 AVSS RREF AVDD25 I Document 38-08030 Rev. *H Page 4 of 34 CY7C68310 4.3 4.3.1 Detailed Pin Descriptions DP, DM 4.3.2 RSDP, RSDM DP and DM are the high-speed USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB. See section 15.0 for PCB layout guidelines. RSDP and RSDM are the full-speed USB signaling pins, and they should be tied to the DP and DM pins through 39Ω resistors. RSDP and RSDM also function as current sinks for termination during high-speed operation. 4.3.3 TEST[0:3] The test pins control the various test modes of the CY7C68310. Most test modes are reserved for ASIC fabrication, but the following table outlines the test modes available for device manufacturing environments. The test pins must be tied to GND for normal operation. Table 4-1. CY7C68310 Test Modes Test Mode 0000 0001 0010 Reserved. Limbo Mode. All output pins set to high-Z during Limbo mode operation with the exception of the XO pin. The XO pin output cell does not have high-Z control (always enabled), and must be disabled or disconnected by other means. To enter Limbo Mode, nRESET must be toggled after the Test pins are set to ‘0010’. Input xnorTree Mode. This mode tests the connectivity of all dedicated inputs and outputs. While in the Input xnorTree Mode of operation, all bi-directional pins are wired as chain outputs. The results of the connectivity procedure will be seen on all bidirectional pins. Chain Inputs (in order): VBUSPWRVLD, VBUSPWRD, DISKRDY, ATAIRQ, IORDY, DMARQ, nRESET, ATAEN, DRVPWRVLD, SYSIRQ, nEJECT Chain Outputs (in order): GPIO[2:0], DD[15:0], SDA_nIMODE. Bi-di xnorTree Mode. This mode test the connectivity of all bi-directional inputs. While in the Bi-di xnor Tree Mode of operation, all bi-directional pins are wired as inputs and become part of the xnor Tree chain. The results of the connectivity procedure will be seen on all output only pins. Chain Inputs: GPIO[0], GPIO[1], GPIO[2], DD[7], DD[8], DD[6], DD[0], DD[5], DD[10], DD[4], DD[11], DD[3], DD[12], DD[2], DD[13], DD[1], DD[14], DD[0], DD[15], SDA_nIMODE. Chain Outputs: nPWR500, nATARST, nDIOW, nDIOR, nDMACK, ATAPUEN, nCS[1:0], DA[2:0], LOWPWR, SCL Description Normal Mode. This is the default mode of operation. 0011 0100 0101–1111 Reserved. 4.3.4 XI, XO enabled by the USB host, a state change on this pin will immediately cause the CY7C68310 to perform a USB remote wakeup event. 4.3.6 SYSIRQ The CY7C68310 requires a 30-MHz signal to derive internal timing. Typically a 30-MHz (2.5V tolerant, parallel-resonant fundamental mode) crystal is used, but a 30-MHz (2.5V, 50% duty cycle) square wave from another source can also be used. If a crystal is used, connect the pins to XI and XO, and also through 20pF capacitors to GND as shown in Figure 8-1. If an alternate clock source is used, apply it to XI and leave XO open. 4.3.5 nEJECT The nEJECT input pin provides a means to communicate an Eject button push to the ATA/ATAPI device via event notification as well as a way to cause a USB Remote-wakeup. During normal operation, asserting nEJECT for 10ms indicates that a media eject has been requested. If the CY7C68310 is in a suspend state, and if remote wakeup is The SYSIRQ pin provides a way for systems to request service from host software by use of the USB Interrupt pipe. If the CY7C68310 has no pending interrupt data to return, USB interrupt pipe data requests are NAKed. If pending data is available, CY7C68310 returns 16 bits of data indicating the state of the DISKRDY pin, the HS_MODE signal (that indicates whether CY7C68310 is operating in high-speed or full-speed), the VBUSPWRD pin, the User-Defined values from bits [7:3] of address 0xE of the configuration space, and the GPIO Pins. Table 4-2 shows the bitmap for the data returned on the interrupt pipe, and the figure beneath it depicts the latching algorithm incorporated by CY7C68310. Document 38-08030 Rev. *H Page 5 of 34 CY7C68310 Table 4-2. USB Interrupt Pipe Data Bitmap USB Interrupt Data Byte 1 7 0 4.3.7 6 0 5 0 4 0 No No NAK Request Yes Int_Data = 0 and SYSIRQ=0? Return Interrupt Data Set Int_Data = 0 USB Interrupt Data Byte 0 1 USB High-Speed 0 VBUSPWRD 7 USER_DEF[4] 6 USER_DEF[3] 5 USER_DEF[2] 4 USER_DEF[1] 3 USER_DEF[0] 2 GPIO[2] 1 GPIO[1] 0 GPIO[0] 3 0 2 DISKRDY Yes No No USB Interrupt Pipe Polled? SYSIRQ=1? Yes Yes Latch State of IO Pins Set Int_Data = 1 Int_Data = 1? Figure 4-2. SYSIRQ Latching Algorithm DRVPWRVLD 4.3.8 ATAEN DRVPWRVLD can be used with removable devices (such as compact flash) to indicate that the media device is present. Pin polarity and function enable are controlled by bits 4 and 2, respectively, of EEPROM address 0x0B. When DRVPWRVLD is deasserted, the CY7C68310 will remove the pull-up on D+ (causing the CY7C68310 to drop off the USB), suspend all ATA state machine activity, drive all ATA interface signals to ‘0’ (assuming ATAEN = ‘1’), and enter into a low-power state. The CY7C68310 will remain in this state until DRVPWRVLD is asserted, at which time it will enable the D+ pull-up, allow resume of ATA state machine activity, and begin to drive the ATA interface pins (assuming ATAEN = ‘1’). The ATAEN pin allows ATA bus sharing with other host devices. Deasserting ATAEN causes the CY7C68310 to highZ all ATA bus interface pins and suspend ATA state machine activity, otherwise leaving the CY7C68310 operational (USB operation continues). Asserting ATAEN causes the CY7C68310 to reset the drive and resume normal operation. To disable USB operation and the ATA interface, the DRVPWRVLD signal can be used in conjunction with ATAEN to force the CY7C68310 into a low-power state until normal operation is resumed. Note that disabling the ATA bus with the ATAEN pin during the middle of a data transfer will result in Document 38-08030 Rev. *H Page 6 of 34 CY7C68310 data loss and may cause the operating system on the host computer to crash. 4.3.9 GPIO Pins 4.3.16 VBUSPWRD The VBUSPWRD input pin indicates whether the device will report itself as bus-powered or self-powered. VBUSPWRD also qualifies the use of nPWR500. Based upon the state of this pin at start-up, the CY7C68310 will request the amount of current specified in the bMaxPower field of the USB Configuration Descriptor. If VBUSPWRD is asserted, the CY7C68310 will report that the device is bus-powered. If VBUSPWRD is deasserted, the CY7C68310 will report that the device is selfpowered. 4.3.17 VBUSPWRVLD (assuming ATAEN = '1'). DISKRDY is filtered for 25 ms on the asserting edge and cleared asynchronously on the deasserting edge. The GPIO pins allow for a general purpose Input/Output interface. Configuration bytes 0x0E and 0x0F contain the settings for the GPIO pins. See section 6.3 for details of how to use the vendor-specific commands to utilize the GPIO functionality. The status of the GPIO pins is also returned by a USB interrupt event. See section 4.3.6 for SYSIRQ details. Alternatively, if the hs_indicator config bit is set (bit 4 of EEPROM address 0x0F), the GPIO2_nHS pin will reflect the operating speed of the device. 4.3.10 LOWPWR LOWPWR is an output pin that, when in a high-Z state, indicates that the CY7C68310 is in a suspend state. When LOWPWR output is driven ‘0’, the CY7C68310 is active. 4.3.11 nRESET Asserting nRESET for a minimum of 1 ms after power rails are stable will reset the entire chip. An RC reset circuit should be used that ensures that no spurious resets occur. 4.3.12 ATAPUEN VBUSPWRVLD (USB VBUS Power Valid) indicates that VBUS power is present at the USB connector. VBUSPWRVLD qualifies driving the system’s 1.5KΩ pull-up resistor on D+ (the USB specification only allows the device to source power to D+ when the host is powered). VBUSPWRVLD is conditioned so that it is only detected after valid chip configuration bits have been loaded. 5.0 5.1 Functional Overview USB Signaling Speeds This output provides control for the required host pull-up resistors on the ATA interface. ATAPUEN is driven ‘0’ when the ATA bus is inactive. ATAPUEN is driven ‘1’ when ATA bus is active. ATAPUEN is set to a high-Z state along with all other ATA interface pins when ATAEN is deasserted. 4.3.13 nPWR500 The CY7C68310 operates at two of the three signal rates that are defined in the Universal Serial Bus Specification Revision 2.0: • Full-speed, with a signaling bit rate of 12 Mbits/sec. • High-speed, with a signaling bit rate of 480 Mbits/sec. nPWR500 is an external pin that, when asserted, indicates VBUS current may be drawn up to the limit specified by the bMaxPower field of the USB configuration descriptors. nPWR500 will only be asserted if VBUSPWRD is also asserted. If the CY7C68310 enters a low-power state, nPWR500 is deasserted. When normal operation is resumed, nPWR500 is restored accordingly. The nPWR500 pin should never be used to control power sources for the CY7C68310. 4.3.14 SCL, SDA_nIMODE 5.2 ATA Interface If an external EEPROM device is used to store configuration information, the clock and data pins for the I2C-compatible port should be connected to the configuration EEPROM and to VCC through 2.2kΩ resistors as shown in Figure 8-1. If configuration information is to be obtained from the attached ATA/ATAPI device (IMODE), SCL should be left as a noconnect and SDA_nIMODE should be tied to GND. 4.3.15 DISKRDY The ATA/ATAPI port on the CY7C68310 is compliant with the Information Technology–AT Attachment with Packet Interface–6 (ATA/ATAPI-6) Specification, T13/1410D Rev 2a. The CY7C68310 supports both ATAPI packet commands as well as ATA commands (by use of ATA Command Blocks), as outlined in Sections 5.2.1 and 5.2.2. Refer to the USB Mass Storage Class (MSC) Bulk Only Transport Specification for information on Command Block formatting. Additionally, the CY7C68310 translates ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices with generic Mass Storage Class BOT drivers. The CY7C68310 also provides a vendor-specific “event notify” ATA command to automatically communicate certain USB and system events to the attached device. 5.2.1 ATA Command Block (ATACB) This input pin indicates the attached device is powered and ready to begin communication with the CY7C68310. DISKRDY polarity can be set using EEPROM address 0x05, bit 0. DISKRDY qualifies the start of the CY7C68310 initialization sequence. A state change from ‘0’ to ‘1’ on DISKRDY will cause the CY7C68310 to wait for 25 ms before asserting nATARESET and re-initializing the device. The ATA interface state machines remain inactive and all of the ATA interface signals are driven logic '0' if DISKRDY is not asserted The ATA Command Block (ATACB) functionality provides a means of passing ATA commands and ATA register accesses for execution. ATACB commands are transferred in the Command Block Wrapper Command Block (CBWCB) portion of the Command Block Wrapper (CBW). The ATACB is distinguished from other command blocks by the first two bytes of the command block matching the wATACBSignature. Only command blocks that have a valid wATACBSignature are interpreted as ATA Command Blocks. All other fields of the CBW and restrictions on the CBWCB remain as defined in the Document 38-08030 Rev. *H Page 7 of 34 CY7C68310 USB Mass Storage Class Bulk-Only Transport Specification. The ATACB must be 16 bytes in length. The following table and text defines the fields of the ATACB. Table 5-1. ATACB Field Descriptions Byte 0 Field Name bVSCBSignature Field Description This field indicates to the CY7C68310 that the ATACB contains a vendorspecific command block. This value of this filed must match the value in EEPROM address 0x06h for this vendor-specific command to be recognized. This field must be set to 0x024h for ATACB commands. This field controls the execution of the ATACB according to the bitfield values: Bit 7 IdentifyPacketDevice - This bit indicates that the data phase of the command will contain ATAPI (0xA1h) or ATA (0xECh) IDENTIFY device data. Setting IdentifyPacketDevice when the data phase does not contain IDENTIFY device data will result in unspecified device behavior. 0 = Data phase does not contain IDENTIFY device data 1= Data phase contains ATAPI or ATA IDENTIFY device data Bit 6 UDMACommand - This bit enables supported UDMA device transfers. Setting this bit when a non-UDMA capable device is attached will result in undetermined behavior. 0 = Do not use UDMA device transfers (only use PIO mode) 1= Use UDMA device transfers Bit 5 DEVOverride - This bit determines whether the DEV bit value is taken from the CY7C68310 configuration data or from the ATACB. 0 = The DEV bit will be taken from EEPROM address 0x05h, bit 5 1= The DEV bit will be taken from the ATACB field 0x0B, bit 4 Bit 4:3 DPErrorOverride - These bits control the Device and Phase Error override feature. These bits shall not be set in conjunction with bmATACBTaskFileRead. 00 = Data accesses are halted if a device or phase error is detected 01 = Data accesses are halted if a device error is detected, but not a phase error 10 = Data accesses are halted if a phase error is detected, but not a device error 11 = Neither device or phase errors will result in halting of data accesses Bit 2 PollAltStatOverride - This bit determines whether or not the Alternate Status register will be polled and the BSY bit will be used to qualify the start of ATACB operation. 0 = The AltStat register will be polled until BSY=0 before proceeding with the ATACB operation 1= The ATACB operation will be executed without polling the AltStat register Bit 1 DeviceSelectionOverride - This bit determines when the device selection will be performed in relation to the command register write accesses. 0 = Device selection will be performed prior to command register write accesses 1 = Device selection will be performed following command register write accesses 1 2 bVSCBSubCommand bmATACBActionSelect Document 38-08030 Rev. *H Page 8 of 34 CY7C68310 Table 5-1. ATACB Field Descriptions Byte Field Name Field Description Bit 0 TaskFileRead - This bit determines whether or not the taskfile register data selected in bmATACBRegisterSelect is returned. If this bit is set, the dCBWDataTransferLength field must be set to 8. 0 = Execute ATACB command and data transfer (if any) 1 = Only read taskfile registers selected in bmATACBRegisterSelect and return 0x00h for all others. The format of the 8 bytes of returned data is as follows: • Address offset 0x00 (3F6h) - Alternate Status • Address offset 0x01 (1F1h) - Features / Error • Address offset 0x02 (1F2h) - Sector Count • Address offset 0x03 (1F3h) - Sector Number • Address offset 0x04 (1F4h) - Cylinder Low • Address offset 0x05 (1F5h) - Cylinder High • Address offset 0x06 (1F6h) - Device / Head • Address offset 0x07 (1F7h) - Command / Status 3 bmATACBRegisterSelect This field controls which of the taskfile register read or write accesses occur. Taskfile read data will always be 8 bytes in length, and unselected register data will be returned as 0x00h. Register accesses occur in sequential order as outlined below (0 to 7): Bit 0 (3F6h) Device Control / Alternate Status Bit 1 (1F1h) Features / Error Bit 2 (1F2h) Sector Count Bit 3 (1F3h) Sector Number Bit 4 (1F4h) Cylinder Low Bit 5 (1F5h) Cylinder High Bit 6 (1F6h) Device / Head Bit 7 (1F7h) Command / Status 4 bATACBTransferBlockCount This value indicates the maximum requested block size in 512-byte increments. This value must be set to the last value used for the “Sectors per block” in the SET_MULTIPLE_MODE command. Legal values are 0, 1, 2, 4, 8, 16, 32, 64, and 128 where 0 indicates 256 sectors per block. A command failed status will be returned if an illegal value is used in the ATACB. These bytes contain ATA register data used with ATA command or PIO write operations. Only registers selected in bmATACBRegisterSelect are required to hold valid data when accessed. The registers are as follows: • ATACB Address Offset 0x05h (3F6h) - Device Control • ATACB Address Offset 0x06h (1F1h) - Features • ATACB Address Offset 0x07h (1F2h) - Sector Count • ATACB Address Offset 0x08h (1F3h) - Sector Number • ATACB Address Offset 0x09h (1F4h) - Cylinder Low • ATACB Address Offset 0x0Ah (1F5h) - Cylinder High • ATACB Address Offset 0x0Bh (1F6h) - Device • ATACB Address Offset 0x0Ch (1F7h) - Command These bytes must be set to 0x00h for ATACB commands. 5-12 bATACBTaskFileWriteData 13-15 Reserved Document 38-08030 Rev. *H Page 9 of 34 CY7C68310 5.2.2 ATA Command Block 2 (ATACB2) wATACB2Signature. Only command blocks that have a valid wATACB2Signature are interpreted as ATACB2 commands. All other fields of the CBW and restrictions on the CBWCB shall remain as defined in the USB Mass Storage Class BulkOnly Transport Specification. The ATACB2 must be 16 bytes in length. The following table and text defines the fields of the ATACB2. The ATA Command Block 2 (ATACB2) functionality provides a means of passing ATA commands and ATA register accesses for execution. ATACB2 allows for 48-bit commands. ATACB2 commands are transferred in the CBWCB portion of the CBW. The ATACB2 is distinguished from other command blocks by the first two bytes of the command block matching the Table 5-2. ATACB2 Field Descriptions Byte 0 Field Name bVSCBSignature Field Description This field indicates to the CY7C68310 that the ATACB contains a vendorspecific command block. This value of this filed must match the value in EEPROM address 0x06h for this vendor-specific command to be recognized. This field must be set to 0x025h for ATACB2 commands. This field controls which of the taskfile register read or write accesses occur. Taskfile read data will always be 12 bytes in length, and unselected register data will be returned as 0x00h. Register accesses occur in sequential order as outlined below (0 to 7): Bit 0 (3F6h) - Alternate Status (read only, unaffected by write commands) Bit 1 (1F1h) - Features / Error Bit 2 (1F2h) - Sector Count Bit 3 (1F3h) - LBA Low (Sector Number) Bit 4 (1F4h) - LBA Mid (Cylinder Low) Bit 5 (1F5h) - LBA High (Cylinder High) Bit 6 (1F6h) - Device / Head (see bmATACB2ActionSelect1) Bit 7 (1F7h) - Command / Status 1 2 bVSCBSubCommand bmATACB2RegisterSelect 3 bmATACB2ActionSelect1 This field controls the execution of the ATACB2 according to the bitfield values: Bit 7 IdentifyDevice - This bit indicates that the data phase of the command will contain ATAPI (0xA1h) or ATA (0xECh) IDENTIFY device data. Setting IdentifyDevice when the data phase does not contain IDENTIFY device data will result in undetermined device behavior. 0 = Data phase does not contain IDENTIFY device data 1= Data phase contains ATAPI or ATA IDENTIFY device data Bit 6 UDMACommand - This bit enables supported UDMA device transfers. Setting this bit when a non-UDMA capable device is attached will result in undetermined behavior. 0 = Do not use UDMA device transfers (only use PIO mode) 1= Use UDMA device transfers Bit 5 DEVOverride - This bit determines whether the DEV bit value is taken from the CY7C68310 configuration data or from the ATACB2. 0 = The DEV bit will be taken from EEPROM address 0x05h, bit 5 1= The DEV bit will be taken from bATACB2DeviceHeadData[5] Bit 4 DErrorOverride - This bit controls the device error override feature. This bit should not be set during a bmATACB2ActionSelect TaskFileRead. 0 = Data accesses are halted if a device error is detected 1 = Data accesses are not halted if a device error is detected Bit 3 PErrorOverride - This bit controls the phase error override feature. This bit should not be set during a bmATACB2ActionSelect TaskFileRead. 0 = Data accesses are halted if a phase error is detected 1 = Data accesses are not halted if a phase error is detected Bit 2 PollAltStatOverride - This bit determines whether or not the Alternate Status register will be polled and its BSY bit will be used to qualify the start of ATACB operation. 0 = The AltStat register will be polled until BSY=0 before proceeding with the ATACB operation 1= The ATACB operation will be executed without polling the AltStat register Document 38-08030 Rev. *H Page 10 of 34 CY7C68310 Table 5-2. ATACB2 Field Descriptions Byte Field Name Field Description Bit 1 DeviceSelectionOverride - This bit determines when the device selection will be performed in relation to the command register write accesses. 0 = Device selection will be performed prior to command register accesses 1 = Device selection will be performed following command register accesses Bit 0 TaskFileRead - This bit determines whether or not the taskfile register data selected in bmATACB2RegisterSelect is returned. If this bit is set, the dCBWDataTransferLength field must be set to 12. 0 = Execute ATACB2 command and data transfer (if any) 1 = Only read taskfile registers selected in bmATACBRegisterSelect and return 0x00h for all others. The format of the 12 bytes of returned data is as follows: • Address offset 0x00h (3F6h) Alternate Status (HOB=0) • Address offset 0x01h (1F6h) Device / Head (HOB=0) • Address offset 0x02h (1F1h) Error (HOB=0) • Address offset 0x03h (1F2h-M) Sector Count (HOB=1) • Address offset 0x04h (1F3h-M) LBA Low (Sector Number) (HOB=1) • Address offset 0x05h (1F4h-M) LBA Mid (Cylinder Low) (HOB=1) • Address offset 0x06h (1F5h-M) LBA High (Cylinder High) (HOB=1) • Address offset 0x07h (1F2h-L) Sector Count (HOB=0) • Address offset 0x08h (1F3h-L) LBA Low (HOB=0) • Address offset 0x09h (1F4h-L) LBA Mid (HOB=0) • Address offset 0x0Ah (1F5h-L) LBA High (HOB=0) • Address offset 0x0Bh (1F7h) Status (HOB=0) 4 bATACB2TransferBlockCount[7:4] These bits indicate the DRQ block size in 512-byte increments. This value is log base 2 of the block size. Legal values are 0 (1 sector per block) through 8 (256 sectors per block). A command failed status will be returned if an illegal value is used in the ATACB2. For commands using multiple sector PIO data transfers, the number of sectors per block must equal the current Multiple Sector Setting of the drive. These bits should be set to ‘0’ for non-multiple, non-UDMA commands. bmATACB2ActionSelect2[3:0] This field controls the execution of the ATACB according to the bitfield values: Bits 3-1 Reserved - These bits must be set to ‘0’ Bit 0 48-bit-write - Determines whether or not M data is used to read 1F2-1F5 0 = Do not read or write 1F2-1F5 with “-M” data 1 = Read or write 1F2-1F5 with “-M” data 5 bATACB2DeviceHeadData The contents of this field are used for writing the Device Head register when Byte 2, Bit 6 of the ATACB2 is set to ‘1’. Otherwise, the value written will be determined by the bridge. Bits 7-5 DevHead - Data used to write to Device Head register. Bit 4 DEVOverride - This bit reflects the state of Byte 3, Bit 5 of the ATACB2. Bits 3-0 DevHead - Data used to write to Device head register. 6-15 bATACB2TaskFileWriteData These bytes contain ATA register data used with ATA command or PIO write operations. Only registers selected in bmATACB2RegisterSelect are required to hold valid data when accessed. The registers are as follows: • • • • • • • • • • ATACB2 Address offset 6h (1F1h) Features ATACB2 Address offset 7h (1F2h-M) Sector Count ATACB2 Address offset 8h (1F3h-M) LBA Low (Sector Number) ATACB2 Address offset 9h(1F4h-M) LBA Mid (Cylinder Low) ATACB2 Address offset Ah (1F5h-M) LBA High (Cylinder High) ATACB2 Address offset Bh (1F2h-L) Sector Count ATACB2 Address offset Ch (1F3h-L) LBA Low ATACB2 Address offset Dh (1F4h-L) LBA Mid ATACB2 Address offset Eh (1F5h-L) LBA High ATACB2 Address offset Fh (1F7h) Command Document 38-08030 Rev. *H Page 11 of 34 CY7C68310 5.2.3 Vendor-specific EVENT_NOTIFY Command firmware supports the EVENT_NOTIFY command. The command code is specified by configuration address 0x02. Setting this byte to 0x00 disables the EVENT_NOTIFY feature. The vendor-specific EVENT_NOTIFY command enables the CY7C68310 to communicate the occurrence of certain USB and system events to the attached device if the device’s Table 5-3. Notification Register Read Values Register Error Sector Count LBA Low (Sector Number) LBA Mid (Cylinder Low) LBA High (Cylinder High) Device/Head Status BUSY N/A N/A 7 6 5 4 N/A N/A N/A nSTATE0 nSTATE1 N/A N/A 3 2 1 0 DRQ N/A N/A N/A The nSTATE0 and nSTATE1 values are read from the device and stored for use as the STATE0 and STATE1 values during the next execution of the event notification command. The nSTATE0 and nSTATE1 values provide temporary non-volatile storage for devices whose power is controlled by nPWR500 (typically bus-powered systems). This allows the device to Table 5-4. Notification Register Write Values Register Features Sector Count LBA Low (Sector Number) LBA Mid (Cylinder Low) LBA High (Cylinder High) Device/Head Command 7 USB Reset 6 Class Specific Reset 5 USB Suspend store information prior to entering a USB Suspend state for retrieval after resuming from the USB Suspend state. Note that a USB Reset from the host may interrupt the collection of data. The device must accommodate the potential for this occurrence. The BSY and DRQ bits must be cleared by the device upon the completion of an event notification command. 4 USB Resume 3 Reserved SelfPowered N/A STATE0 STATE1 N/A 2 Reserved BusPowered 1 Eject Button Pressed USB High-Speed 0 Eject Button Released USB Full-Speed Reserved Reserved Reserved Reserved Specified in Configuration byte 0x02 ration data should not be confused with the USB Configuration Descriptor data. The STATE0 and STATE1 values are written with the value of nSTATE0 and nSTATE1 obtained from the previously completed event notification command. Assertion of nRESET resets STATE0 and STATE1 to 0x00. 6.0 Configuration 6.1 CY7C68310 Configuration and USB Descriptor Sources CY7C68310 configuration and USB descriptor data can be retrieved from three sources. Table 6-1 indicates the method of determining which data source is used. Certain timing parameters and operational modes for the CY7C68310 are configurable. Some USB configuration and descriptor values are also configurable. CY7C68310 configu- Document 38-08030 Rev. *H Page 12 of 34 CY7C68310 Table 6-1. CY7C68310 Configuration and USB Descriptor Sources I2C-compatible I2C Signature SDA_nIMODE = 0 Device Present Check Passes CY7C68310 Configuration and USB Descriptor Retrieval Method No No N/A In this mode, the CY7C68310 uses internal ROM contents for USB descriptor information and configuration register values. This mode is for debug/manufacturing operation only. Not for shipping products. In this mode, the CY7C68310 uses internal ROM contents for USB descriptor information. Configuration register values are loaded from internal ROM. This is not a valid mode of operation. The CY7C68310 retrieves all Descriptor and Configuration values from the vendor-specific Identify (FBh) data. The CY7C68310 is configured using internal ROM values until FBh data becomes available. The CY7C68310 uses internal ROM contents for USB descriptor information. Configuration register values are loaded from internal ROM. In this mode of operation, any CY7C68310 vendor-specific configuration access causes the CY7C68310 to recheck the signature field. Once the signature check passes, SROM data is returned for USB descriptors requests. This is not a valid mode of operation. The CY7C68310 retrieves all Descriptor and Configuration values from the I2C-compatible memory device. The CY7C68310 is configured using these values. 6.1.3 Internal ROM Contents Yes N/A No Yes N/A Yes No Yes No No Yes Yes 6.1.1 I2C-compatible Device The CY7C68310 provides support for the 24LCXXB family of EEPROMs. Following the release of nRESET, the CY7C68310 waits 50 ms and then checks for I2C-compatible device presence. If an I2C-compatible device is present but does not pass signature check, the CY7C68310 re-tests the signature with each vendor-specific USB load or read access of configuration bytes 0 and 1. Once the signature check passes, I2C-compatible data is returned for USB descriptor requests. If an I2C-compatible device is detected initially, it is always assumed present until the next reset cycle (nRESET). If an I2C-compatible device is present, a lack of an ACK response when required causes the CY7C68310 to stall that USB request. The CY7C68310 will attempt the access again with the next USB request. 6.1.2 IMODE The CY7C68310 also contains an internal set of CY7C68310 configuration and USB descriptors. The internal descriptors may only be used during manufacturing, as the internal ROM values disable some features required for normal operation to aid use in a manufacturing environment. Also, the internal ROM descriptors do not provide a unique serial number (required for USB Mass Storage Class compliance), and therefore cannot be used for shipping products. See Table 62 for the organization of the internal ROM contents. An external I2C-compatible memory device or utilization of the vendor-specific FBh identify command is required to correctly configure the CY7C68310 for operation and provide a unique serial number for MSC compliance. 6.2 EEPROM Organization Configuration and descriptor data can also be supplied by an attached mass storage device (IMODE) through a vendorspecific Identify (FBh) ATA command. The CY7C68310 provides 256 bytes of internal RAM for FBh data storage. Unlike operation with an external I2C-compatible memory device, IMODE operation requires the attached device first be initialized and FBh data retrieved before the CY7C68310 can allow USB enumeration. To meet USB specification requirements, IMODE operation must be limited to systems that draw 100 mA or less from VBUS prior to USB configuration. CY7C68310 configuration and USB descriptor data can be supplied from an I2C-compatible serial memory device. The CY7C68310 can address 2 Kbytes of I2C-compatible data, but CY7C68310 configuration and USB descriptor information are limited to 512 bytes maximum. Unused register space in the I2C-compatible serial memory device may be used for product specific data storage. Note that no descriptor is allowed to span multiple pages within the I2C-compatible serial memory device. Document 38-08030 Rev. *H Page 13 of 34 CY7C68310 Table 6-2. EEPROM Organization I2C Address 0x00 0x01 0x02 Field Name Field Description Required I2C Data 0x4B 0x50 0x00 Example I2C Data CY7C68310 Configuration Data I2C memory device Signature LSB I2C memory device Signature byte. (LSB) I2C memory device Signature MSB I2C memory device Signature byte. (MSB) Event Notification Bits (7:0) ATAPI event notification command. The value of this register (if other than 0x00) is used to identify the vendor-specific Event Notification command (see Section 5.2.3). Setting this field to 0x00 disables this feature. Bits (7:0) ATA device Automatic Power Management value. If an attached ATA device supports APM and this field contains other than 0x00, the CY7C68310 will issue a SET FEATURES command to enable APM with this register value during the drive initialization. Time in 128-millisecond granularity before the CY7C68310 stops polling the ALT STAT register for reset complete and restarts the reset process (0x80 = 16.4 seconds). Bit (7) – Read only USB bus mode of operation. ‘0’ = USB is operating in full-speed mode (12 Mbit/sec) ‘1’ = USB is operating in high-speed mode (480 Mbit/sec) ATAPI Command Block Size Bit (6) CBW Command Block Size. ‘0’ = 12 byte ATAPI CB ‘1’ = 16 byte ATAPI CB Master/Slave Selection Bit (5) Device number selection. This bit is valid only when “Skip ATA/ATAPI Device Initialization” is active. Otherwise, the value of this bit is ignored. ‘0’ = Drive 0 (master) ‘1’ = Drive 1 (slave) ATAPI Reset Bit (4) ATAPI reset during drive initialization. Setting this bit causes the CY7C68310 to issue an ATAPI reset during device initialization. ATA_NATAPI Bit (3) – Read only. Indicates if an ATA or ATAPI device is detected. ‘0’ = ATAPI device ‘1’ = ATA device or possible device initialization failure Force USB FS Bit(2) Force USB full-speed only operation. Setting this bit prevents the CY7C68310 from negotiating HS operation during USB reset events. ‘0’ = Normal operation – allow HS negotiation during USB reset 0x03 APM Value 0x00 0x04 ATA Initialization Timeout 0x80 0x05 USB Bus Mode 0x00 Document 38-08030 Rev. *H Page 14 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address Field Name Field Description ‘1’ = USB FS only – do not allow HS negotiation during USB reset VS/MSC SOFT_RESET Bit(1) Vendor-specific/MSC SOFT_RESET control. ‘0’ = Vendor-specific USB command utilized for SOFT_RESET ‘1’ = Mass Storage Class USB command utilized for SOFT_RESET DISKRDY Polarity Bit (0) DISKRDY active polarity. DISKRDY Polarity is ignored if IMODE is set to ‘1’. During IMODE operation DISKRDY polarity is active HIGH. ‘0’ = Active HIGH polarity ‘1’ = Active LOW polarity 0x06 ATA Command Designator Value in CBW CB field that designates if the CB is decoded as vendor-specific ATA/CFG commands instead of the ATAPI command block. Bits (7:1)– must be set to ‘0’. Bit (0) This bit enables the CY7C68310 to accommodate ATAPI devices that take longer to initialize than what is allowed in the ATA/ATAPI-6 specification. ‘1’ = Retry ATAPI commands ‘0’ = Normal ATAPI timing 0x08 Initialization Status Bit (7) – Read only Drive Initialization Status. If set, indicates the drive initialization sequence state machine is active. Force ATA Device Bit (6) Allows software to manually enable ATA Translation with devices that do not support CY7C68310 device initialization algorithms. Force ATA Device must be set to ‘1’ in conjunction with Skip ATA/ATAPI Device Initialization and ATA Translation Enable. Skip ATA/ATAPI Device Initial- Bit (5) ization Forces the CY7C68310 to skip device initialization upon startup. This bit should be cleared for IMODE operation. The USB device driver must initialize the attached device (if required) when this bit is set. For ATAPI devices, the host driver must issue an IDENTIFY command utilizing ATA. ‘0’ = normal operation ‘1’ = only reset the device and write the device control register prior to processing commands Reserved Last LUN Identifier 0x09 ATAEN Bits (4:3) – must be set to ‘0’. Bits (2:0) Maximum number of LUNs device supports. Bit (7) – Read only. Holds the current logic state of the ATAEN pin. 0x01 0x00 0x24 Required I2C Data Example I2C Data 0x07 Reserved Retry ATAPI 0x01 Document 38-08030 Rev. *H Page 15 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address Field Name Reserved SRST Enable Bit (0) Soft-reset during drive initialization. ‘0’ = Disable soft-reset functionality ‘1’ = Enable soft-reset during drive initialization 0x0A ATA Data Assert Bits (7:4) ATA cycle times are calculated using Data Assert and Data Recover values. Standard values for ATA-compliant devices and a 30.0-MHz system clock (in binary): mode 0 mode 1 mode 2 mode 3 mode 4 ATA Data Recover Bits (3:0) Standard recover values and cycle times for ATA-compliant devices and a 30.0 MHz system clock (in binary): mode 0 mode 1 mode 2 mode 3 mode 4 0x0B ATA Data Set-up Bits (7:5) Set-up time is only incurred on the first data cycle of a burst. Standard values for ATA-compliant devices and a 30.0 MHz system clock are (in binary): mode 0 mode 1 mode 2 mode 3 mode 4 Drive Power Valid Polarity Bit (4) Controls the polarity of DRVPWRVLD pin. ‘0’ = Active LOW (“connector ground” indication) ‘1’ = Active HIGH (power indication from device) Override PIO Timing Bit (3) This field is used in conjunction with ATA Data Set-up, ATA Data Assertion, ATA Data Recover, and PIO Mode Selection fields. ‘0’ = Use timing information acquired from the Drive ‘1’ = Override device timing information with configuration values Drive Power Valid Enable Bit (2) 010 001 001 001 000 (2+1)*33.33 = 133 ns (1+1)*33.33 = 66 ns (1+1)*33.33 = 66 ns (1+1)*33.33 = 66 ns (0+1)*33.33 = 33 ns 1100 0111 0011 0010 0000 (4+1)+(12+1)*33.33 = 600 ns (3+1)+(7+1)*33.33 = 400 ns (2+1)+(3+1)*33.33 = 233 ns (2+1)+(2+1)*33.33 = 200 ns (2+1)+(0+1)*33.33 = 133 ns 0x00 0101 0011 0011 0010 0010 (5+1)*33.33 = 200 ns (3+1)*33.33 = 133 ns (3+1)*33.33 = 133 ns (2+1)*33.33 = 100 ns (2+1)*33.33 = 100 ns 0x20 Field Description Bits (6:1) – must be set to ‘0’. Required I2C Data Example I2C Data Document 38-08030 Rev. *H Page 16 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address Field Name Field Description Enable for the DRVPWRVLD pin. DRVPWRVLD is typically only be enabled in applications where the CY7C68310 is VBUS powered. ‘0’ = pin disabled (most systems) ‘1’ = pin enabled ATA Read Kludge Bit(1) PIO data read high-Z control. Enabling this will high-Z the ATA data bus during PIO read operations while addressing the data register. In most applications this bit is set to ‘0.’ ‘0’ = Normal operation as per ATA/ATAPI interface specification ‘1’ = High-Z DD[15:0] during PIO data register reads IMODE 0x0C SYSIRQ DISKRDY ATA Translation Enable Bit (0) – Read only This bit reflects the state of the IMODE input pin at start-up. Bits(7) – Read only This bit reflects the current logic state of the SYSIRQ input. Bit(6) – Read only This bit reflects the current logic state of the DISKRDY input. Bit(5) Enable ATAPI to ATA protocol translation enable. If enabled, AND if an ATA device is detected, ATA translation is enabled. If Skip ATA/ATAPI Device Initialization is set ‘1,’ Force ATA Device must also be set ‘1’ in order to utilize ATA translation. ‘0’ = ATA Translation Disabled ‘1’ = ATA Translation Enable ATA UDMA Enable Bit(4) Enable Ultra Mode data transfer support for ATA devices. If enabled, AND the ATA device reports UDMA support, the CY7C68310 will utilize UDMA data transfers. ‘0’ = Disable ATA device UDMA support ‘1’ = Enable ATA device UDMA support ATAPI UDMA Enable Bit(3) Enable Ultra Mode data transfer support for ATAPI devices. If enabled, AND the ATAPI device reports UDMA support, the CY7C68310 will utilize UDMA data transfers. ‘0’ = Disable ATAPI device UDMA support ‘1’ = Enable ATAPI device UDMA support ROM UDMA Mode Bits(2:0) ROM UDMA Mode indicates the highest UDMA mode supported by the product. The CY7C68310 will utilize the lesser of ROM UDMA Mode and the highest mode supported by the device. UDMA read operation mode timing is controlled by the device. mode 0 mode 1 mode 2 mode 3 mode 4 000 001 010 011 100 133.3 ns per 16-bit word write 100 ns per 16-bit word write 66.7 ns per 16-bit word write 66.7 ns per 16-bit word write 33.3 ns per 16-bit word write 0x3C Required I2C Data Example I2C Data Document 38-08030 Rev. *H Page 17 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0x0D Field Name PIO Mode Selection Bits (7:5) PIO Mode Selection. The PIO mode reported back to the device if the Override PIO Timing configuration bit is set. mode 0 mode 1 mode 2 mode 3 mode 4 Skip Pin Reset Bit (4) Skip nATARST assertion. Setting this bit prevents the CY7C68310 from asserting nATARST during initialization of the ATA/ATAPI device. If this bit is set to ‘1’, SRST Enable (address 0x09, bit 0) must also be set to ‘1’. ‘0’ = Allow nATARST assertion ‘1’ = Disable nATARST assertion Reserved 0x0E SYSIRQ User-defined Bits Bits (3:0) – must be set to ‘0’. Bits (7:3) SYSIRQ USER_DEF[4:0] bits. The value of these bits will be returned to the host via the USB interrupt pipe as stated in Section 4.3.6. General Purpose IO Bits(2:0) GPIO[2:0] pin values. When the GPIO pins are configured as outputs, writing to these bits will set the logic value of the GPIO pins to ‘0’ or ‘1’. Reading this address, regardless of whether the GPIO pins are set to input or output, returns the logic value from the GPIO pins. 0x0F ATAPI IRQ Disable Bit (7) Disables the use of the ATAIRQ signal with ATAPI devices. ‘0’ = ATAIRQ use enabled ‘1’ = ATAIRQ use disabled Reserved Int Reason Disable Bit (6) – must be set to ‘0’. Bit (5) Setting to a ‘1’ causes CY7C68310 to ignore the contents of the interrupt reason register when talking to an ATAPI device. Bit (4) Enables GPIO2_nHS pin to indicate the current operating speed of the device (if output is enabled). ‘0’ = normal GPIO operation ‘1’ = high-speed indicator enable Reserved General Purpose IO Pin Enable Bit (3) – must be set to ‘1’. Bits (2:0) GPIO[2:0] high-Z control. These bits have precedence over bit 4 of this byte. ‘0’ = Output enabled (GPIO pin is an output). ‘1’ = high-Z (GPIO pin is an input). 0x07 0x00 000 001 010 011 100 Field Description Required I2C Data Example I2C Data 0x90 HS Indicator Enable Document 38-08030 Rev. *H Page 18 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D bLength bDescriptor Type bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor (LSB) idVendor (MSB) idProduct (LSB) idProduct (MSB) bcdDevice (LSB) bcdDevice (MSB) Device release number in BCD lsb (product release number). Device release number in BCD msb (silicon release number). This field entry is always returned from internal ROM contents, regardless of the descriptor source. Index to manufacturer string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Index to product string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. Index to serial number string. This entry must equal half of the address value where the string starts or 0 if the string does not exist. The USB Mass Storage Class Bulk Only Transport Specification requires a unique serial number. Number of configurations supported. Length of device descriptor in bytes. Descriptor type. USB specification release number in BCD. Device class. Device subclass. Device protocol. Maximum USB packet size supported. Number of configurations supported. Reserved. Must be set to 0. Length of Configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. 0x40 0x01 0x00 0x09 0x02 0x27 0x00 0x01 0x0A 0x06 0x00 0x02 0x00 0x00 0x00 Product ID. Device class. Device subclass. Device protocol. Maximum USB packet size supported. Vendor ID. 0x40 0xB4 0x04 0x31 0x68 0x00 0x01 Field Name Field Description Length of device descriptor in bytes. Descriptor type for device descriptor. USB Specification release number in BCD. Required I2C Data 0x12 0x01 0x00 0x02 0x00 0x00 0x00 Example I2C Data USB Device Descriptor 0x1E iManufacturer 0x49 0x1F iProduct 0x5F 0x20 iSerialNumber 0x73 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F bNumConfigurations bLength bDescriptorType bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 bNumConfigurations bReserved bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) USB Device Qualifier Descriptor USB Standard Configuration Descriptor (VBUSPWRD Asserted) Document 38-08030 Rev. *H Page 19 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0x30 0x31 0x32 Field Name bNumInterfaces bConfiguration Value iConfiguration Field Description Number of interfaces supported. The CY7C68310 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02. Index to the configuration string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On board default 7 Reserved. Set to ‘1’ ‘1’ 6 Self powered ‘0’ = Bus-powered device 5 Remote wake-up ‘0’ 4:0 Reserved. Set to ‘0’ ‘0’ Maximum power consumption for this configuration. Units used are mA*2 (i.e., 0x31 = 98 mA, 0xF9 = 498 mA). Length of Configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The CY7C68310 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02. Index to the configuration string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On board default 7 Reserved. Set to ‘1’ ‘1’ 6 Self powered ‘0’ = Bus-powered device 5 Remote wake-up ‘0’ 4:0 Reserved. Set to ‘0’ ‘0’ Maximum power consumption for this configuration. Units used are mA*2 (i.e., 0x31 = 98 mA, 0xF9 = 498 mA). Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate settings. Number of endpoints. Interface class. Interface subclass. Interface protocol. Index to first interface string. This entry must equal half of the address value where the string starts or zero if the string does not exist. 0x09 0x04 0x00 0x00 0x03 0x08 0x06 0x50 0x00 0x80 or 0xA0 0x80 or 0xA0 Required I2C Data 0x01 0x02 0x00 Example I2C Data 0x33 bmAttributes 0x34 bMaxPower 0xF9 USB Other Speed Configuration Descriptor (VBUSPWRD Asserted) 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfigurationValue iConfiguration 0x09 0x07 0x27 0x00 0x01 0x02 0x00 0x3C bmAttributes 0x3D bMaxPower 0xF9 USB Interface Descriptor (High-speed) 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 bLength bDescriptorType bInterfaceNumber bAlternateSettings bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Document 38-08030 Rev. *H Page 20 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval Reserved bLength bDescriptorType bInterfaceNumber bAlternateSettings bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface High-speed interval for polling (max NAK rate). Reserved. Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate settings Number of endpoints. Interface class. Interface subclass. Interface protocol. Index to first interface string. This entry must equal half of the address value where the string starts or zero if the string does not exist. Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 1. This is a bulk endpoint. Max data transfer size. 0x07 0x05 0x01 0x02 0x40 0x00 High-speed interval for polling (max NAK rate). Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 3. This is an interrupt endpoint. Max data transfer size. High-speed interval for polling (max NAK rate). Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. Field Name Field Description Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 1. This is a bulk endpoint. Max data transfer size. Required I2C Data 0x07 0x05 0x01 0x02 0x00 0x02 0x01 0x07 0x05 0x82 0x02 0x00 0x02 0x01 0x07 0x05 0x83 0x03 0x02 0x00 0x0C 0x00 0x09 0x04 0x00 0x00 0x03 0x08 0x06 0x50 0x00 Example I2C Data USB Bulk Out Endpoint (High-speed) USB Bulk In Endpoint (High-speed) USB Interrupt Endpoint (High-speed) USB Interface Descriptor (Full-speed) USB Bulk Out Endpoint (Full-speed) 0x66 0x67 0x68 0x69 0x6A 0x6B bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) Document 38-08030 Rev. *H Page 21 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0x6C bInterval Field Name Field Description High-speed interval for polling (max NAK rate). Does not apply to FS bulk endpoints, set to zero. Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. High-speed interval for polling (max NAK rate). Does not apply to FS bulk endpoints, set to zero. Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 3. This is an interrupt endpoint. Max data transfer size. High-speed interval for polling (max NAK rate). Reserved. LANGID descriptor length. Descriptor type. Language supported (0x0409 = US English). CY7C68310 only supports one language code Required I2C Data 0x00 Example I2C Data USB Bulk In Endpoint (Full-speed) 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval 0x07 0x05 0x82 0x02 0x40 0x00 0x00 USB Interrupt Endpoint (Full-speed) 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval Reserved bLength bDescriptorType LANGID (lsb) LANGID (msb) bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfigurationValue iConfiguration 0x07 0x05 0x83 0x03 0x02 0x00 0xFF 0x00 0x04 0x03 0x09 0x04 0x09 0x02 0x27 0x00 0x01 0x02 0x00 USB String Descriptor – Index 0 (LANGID) USB Standard Configuration Descriptor (VBUSPWRD Deasserted) Length of Configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The CY7C68310 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02. Index to the configuration string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit Description On board default 7 Reserved. Set to ‘1’ ‘1’ 6 Self powered. ‘1’ = Self-powered device 5 Remote wake-up. ‘0’ 4:0 Reserved. Set to ‘0’ ‘0’ Maximum power consumption for this configuration. Units used are mA*2 (i.e., 0x31 = 98 mA, 0xF9 = 498 mA). 0xC0 or 0xE0 0x87 bmAttributes 0x88 bMaxPower 0x31 Document 38-08030 Rev. *H Page 22 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfigurationValue iConfiguration Field Name Field Description Length of Configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The CY7C68310 only supports one interface. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x02. Index to the configuration string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Device attributes for this configuration. Configuration characteristics: Bit 7 6 5 4:0 0x91 bMaxPower Description Reserved. Set to ‘1’ Self powered Remote wake-up Reserved. Set to ‘0’ On board default ‘1’ ‘1’ = Self-powered device ‘0’ ‘0’ 0x31 0xC0 or 0xE0 Required I2C Data 0x09 0x07 0x27 0x00 0x01 0x02 0x00 Example I2C Data USB Other Speed Configuration Descriptor (VBUSPWRD Deasserted) 0x90 bmAttributes Maximum power consumption for this configuration. Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA). String descriptor length in bytes. Descriptor type. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. 0x03 USB String Descriptor – Manufacturer 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString 0x2C 0x43 (“C”) 0x00 0x79 (“y”) 0x00 0x70 (“p”) 0x00 0x72 (“r”) 0x00 0x65 (“e”) 0x00 0x73 (“s”) 0x00 0x73 (“s”) 0x00 0x20 (“ ”) 0x00 0x53 (“S”) 0x00 0x65 (“e”) 0x00 Document 38-08030 Rev. *H Page 23 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0x1B 0xB4 0xB5 0xB6 0xB7 0xB8 0x1B 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0x1C 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString Field Name Field Description Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. String descriptor length in bytes. Descriptor Type. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Required I2C Data Example I2C Data 0x6D (“m”) 0x00 0x69 (“i”) 0x00 0x63 (“c”) 0x00 0x6F (“o”) 0x00 0x6E (“n”) 0x00 0x64 (“d”) 0x00 0x75 (“u”) 0x00 0x63 (“c”) 0x00 0x74 (“t”) 0x00 0x6F (“o”) 0x00 0x72 (“r”) 0x00 0x2A 0x03 0x55 (“U”) 0x00 0x53 (“S”) 0x00 0x52 (“B”) 0x00 0x20 (“ ”) 0x00 0x53 (“S”) 0x00 0x74 (“t”) 0x00 0x6F (“o”) 0x00 0x72 (“r”) 0x00 0x61 (“a”) 0x00 USB String Descriptor – Product Document 38-08030 Rev. *H Page 24 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bLength bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString Field Name Field Description Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. String descriptor length in bytes. Descriptor type. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Required I2C Data Example I2C Data 0x67 (“g”) 0x00 0x65 (“e”) 0x00 0x20 (“ ”) 0x00 0x41 (“A”) 0x00 0x64 (“d”) 0x00 0x61 (“a”) 0x00 0x70 (“p”) 0x00 0x74 (“t”) 0x00 0x65 (“e”) 0x00 0x72 (“r”) 0x00 0x1A 0x03 0xXX 0x00 0xXX 0x00 0xXX 0x00 0xXX 0x00 0xXX 0x00 0xXX 0x00 0xXX 0x00 0xXX 0x00 0xXX 0x00 0xXX 0x00 USB String Descriptor – Serial Number Document 38-08030 Rev. *H Page 25 of 34 CY7C68310 Table 6-2. EEPROM Organization (continued) I2C Address 0xFC 0xFD 0xFE 0xFF bString bString bString bString Field Name Field Description Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Required I2C Data Example I2C Data 0xXX 0x00 0xXX 0x00 6.3 Programming the EEPROM 2 Programming of the I C memory device can be accomplished using an external device programmer, CY7C68310 supported vendor-specific USB commands, or an in-system programmer such as a bed of nails. Table 6-3 shows the format of the vendor-specific commands used to program the EEPROM via Table 6-3. EEPROM-related Vendor-specific Commands Label LOAD_CONFIG_DATA READ_CONFIG_DATA bmRequestType bRequest 0x40 0xC0 0x01 0x02 USB. Any vendor-specific USB write request to the Serial ROM device configuration space will simultaneously update internal configuration register values as well. If the I2C device is programmed without vendor specific USB commands, CY7C68310 must be synchronously reset (nRESET) before configuration data is reloaded. wValue wIndex wLength Data Configuration Data Configuration Data Data Destination Starting Address Data Length Data Source Starting Address Data Length The CY7C68310 supports a subset of the “slow mode” specification (100 KHz) required for 24LCXXB EEPROM family device support. Features such as “Multi-Master,” “Clock Synchronization” (the SCL pin is output only), “10-bit addressing,” and “CBUS device support” are not supported. Vendor-specific USB commands allow the CY7C68310 to address up to 2 Kbytes of data (although configuration/descriptor information is limited to 512 bytes of register space). 6.3.1 LOAD_CONFIG_DATA value must be evenly divisible by eight. Writes to I2Ccompatible memory devices must not cross 256-byte page boundaries, i.e., start and finish write addresses must have equal modulo 256 values. Write operations with beginning and end addresses that do not fall in the same 256-byte page will result in a STALL condition. Illegal values for wValue as well as attempts to write to an I2C-compatible memory device when none is connected will result in a STALL condition. 6.3.2 READ_CONFIG_DATA This request enables configuration data writes to the data source specified by the wValue field. The wIndex field specifies the starting address and the wLength field denotes the data length in bytes. Legal values for wValue are as follows: • 0x0000 Configuration bytes, address range 0x2 – 0xF • 0x0002 External I2C memory device. Configuration byte writes must be constrained to addresses 0x2 through 0xF, as shown in Table 6-2. Attempts to write outside this address space will result in a STALL condition. Configuration byte writes only overwrite CY7C68310 Configuration Byte registers, the original data source remains unchanged (I2C-compatible memory device, FBh identify data, or internal ROM). Single byte writes to the I2C-compatible memory devices can start at any address. Writes greater then a single byte must only start on eight-byte boundaries, meaning that the address This USB request allows data retrieval from the data source specified by the wValue field. Data is retrieved beginning at the address specified by the wIndex field. The wLength field denotes the length in bytes of data requested from the data source. Legal values for wValue are as follows: • 0x0000 Configuration bytes, addresses 0x0 – 0xF only • 0x0001 Internal ROM • 0x0002 External I2C-compatible memory device • 0x0003 Vendor-specific identify (FBh) data Illegal values for wValue will result in a STALL condition on the USB port. Attempted reads from an I2C-compatible memory device when none is connected or attempted reads from FBh data when not in IMODE will result in a STALL condition. Attempts to read configuration bytes with starting addresses greater than 0xF will also result in a STALL condition. Document 38-08030 Rev. *H Page 26 of 34 CY7C68310 7.0 7.1 Timing Characteristics I2C-compatible Memory Device Interface Timing Thigh Tlow SCL TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO SDA OUT TBUF TDSU SDA IN I2C-compatible Device Parameter Clock high time Clock low time Start condition hold time Start condition set-up time Data output hold time Data output set-up time Stop condition set-up time Required data valid before clock Min time bus must be free before next transmission Figure 7-1. I2C Interface Timing Symbol Thigh Tlow THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TDSU TBUF Value 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 5066 ns 500 ns 5066 ns 7.2 USB Interface Timing The CY7C68310 transceiver complies to the timing characteristics as stated in the USB Specification version 2.0. The CY7C68310 can operate at either the high-speed or full-speed signalling rate. frequency is measured at one half of the 2.5V power source (VDD25). The CY7C68310 internal PLL can be clocked using either a 30-MHz (±0.005%) fundamental-mode crystal or a 2.5V, 50% duty-cycle square wave. The recommended external clock source for the CY7C68310 is the PRE XH30PRF10BL crystal (10-pF load capacitance). 7.3 ATA/ATAPI Interface Timing 7.5 Reset Timing The ATA interface supports ATA PIO modes 0 to 4, and Ultra DMA modes 0 to 4, per the ATA Attachment – 6 with Packet Interface revision 3b. All input signals on the ATA/ATAPI port are considered asynchronous and are synchronized to the chip's internal system clock. All output signals are clocked using the chip’s internal system clock, for which there is no external reference. Thus, the output signals should also be considered asynchronous. The PIO mode used for data register accesses is retrieved from the device or specified in the CY7C68310 configuration bytes. The CY7C68310 requires an off-chip power-on reset circuit. nRESET must be held asserted for a minimum of 1 ms after power is stable to cause a chip reset. 8.0 External Circuitry Requirements 7.4 External Clock Source Timing Certain external components are required for proper CY7C68310 operation. The following figure details the minimum required circuitry for normal operation. Additional components may be required to support configurable CY7C68310 features, if utilized. The CY7C68310 derives its internal system clock from an external clock source. The external clock input signal Document 38-08030 Rev. *H Page 27 of 34 CY7C68310 3.3V 3.3V RPU 1.5KΩ SDA SCL RREF SCANEN TMC[1:2] DP D+ 39Ω D39Ω 39KΩ VBUS 62KΩ 30MHz 100Ω 0.1µF 1.5KΩ 1.5KΩ CY7C68310 RSDP DM RSDM XO VBUSPWRVLD 2.4KΩ (1%) AVSS XI 9pF 9pF Figure 8-1. External Circuitry Requirements 8.1 ATA Interface Termination Design practices as outlined in the ATA/ATAPI-6 specification for signal integrity should be followed with systems that utilize a ribbon cable interconnect between the CY7C68310’s ATA interface and the attached ATA/ATAPI device, especially if Ultra DMA Mode is utilized. 9.0 port Manufacturing Interconnect Test Sup- 8.2 Power Supply Regulation At no time should the 3.3V power rail drop below the 2.5V rail for proper device operation. Care should be taken to ensure that the power rails rise and fall without allowing the 3.3V supply to drop below the 2.5V supply. The recommended method is to cascade voltage regulating circuits such that the 2.5V supply is powered from the 3.3V supply. Manufacturing Test Mode is provided as a means to implement board- and system-level interconnect tests. During Manufacturing Test Mode operation, all outputs not associated directly with USB operation are controllable. Normal state machine and register control of output pins are disabled. Two vendorspecific USB requests (LOAD_MFG_DATA and READ_MFG_DATA) are used in Manufacturing Test Mode operation. 9.1 LOAD_MFG_DATA 8.3 Pull-ups/Pull-downs on High-Z Pins Certain output pins act as open-drain and remain at a high-Z state unless asserting a ‘0.’ These pins include SCL, SDA, LOWPWR, and nPWR500. If their functionality is utilized, these pins must be tied to pull-up resistors to avoid floating while in a high-Z state. These pins can be left as no-connects if the functionality is not utilized. Table 9-1. LOAD_MFG_DATA Command Format Label LOAD_MFG_DATA bmRequestType 0x40 bRequest 0x05 This USB request is used to enable and control Manufacturing Test Mode operation. While in Manufacturing Test Mode, individual pins may be asserted or deasserted depending upon the contents of the data field. The DD and GPIO pins may also be set to a high-Z state in preparation for READ_MFG_DATA command operations. Control of the select CY7C68310 I/O pins and their high-Z controls are mapped to the USB data packet associated with this request. wValue Disable/Enable wIndex Starting Address wLength Data Length Data Mfg. Test Data Legal values for wValue are as follows: • 0x0000 Normal operation mode – returns CY7C68310 to normal operation regardless of previous command data sets (power-on reset default). • 0x0001 Manufacturing Test Mode – manufacturing test registers control specific CY7C68310 outputs cells to enable board level testing in the manufacturing environment. Legal values for wLength are as follows: • 0x0000 Valid only when wValue = 0x0000; used when disabling Manufacturing Test Mode of operation • 0x0007 Valid only when wValue = 0x0001. For proper Manufacturing Test Mode operation, wLength must equal 0x0007. Any data packet lengths greater than 7 will result in a STALL condition. Document 38-08030 Rev. *H Page 28 of 34 CY7C68310 Table 9-2. Bit-wise Mapping of LOAD_MFG_DATA Test Data Byte 0 0 0 0 0 0 0 0 1 1 1 1 1 2 3 4 4 4 4 5 0 1 2 3 4 5 6 7 0 2:1 5:3 6 7 7:0 7:0 2:0 3 6:4 7 7:0 Bit(s) LOWPWR Reserved – Value will not affect output nPWR500 nATARST nDIOW nDIOR nDMACK ATAPUEN Reserved – Value will not affect output nCS[1:0] DA[2:0] SCL DD_EN – ‘1’ = Enable output (set for writes), ‘0’ = high-Z DD[15:0] (set for reads) DD[7:0] DD[15:8] GPIO[2:0] Reserved – Value will not affect output GPIO_EN[2:0] – ‘1’ = Enable output (set for writes), ‘1’ = high-Z GPIO[2:0] (set for reads) Reserved – Value will not affect output Reserved – Value will not affect output not associated directly with USB operation can be sampled at any time during normal or Manufacturing Test Mode operation. This request is independent of normal CY7C68310 state machine control or Manufacturing Test Mode write operations. Test/High-Z Control Register Name 9.2 READ_MFG_DATA This USB request returns a “snapshot in time” of selected input pins. The input pin states are bit-wise mapped to the USB data packed associated with this request. CY7C68310 input pins Table 9-3. READ_MFG_DATA Command Format Label READ_MFG_DATA bmRequestType 0xC0 bRequest 0x06 wValue 0x00 wIndex 0x00 wLength Data Length Data Mfg. Test Data Legal values for wValue are as follows: •0x0000wValue must be set to 0x0000. Legal values for wLength are as follows: • 0x0001–0x0008 Any wLength value greater than 0x0008 will result in a STALL response. Document 38-08030 Rev. *H Page 29 of 34 CY7C68310 Table 9-4. Bit-wise Mapping of READ_MFG_Data Test Data Byte 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 3 4 5 5 5 5 6 6 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 4:3 7:5 7:0 7:0 2:0 3 4 7:5 0 1 2:7 7:0 Bit(s) DRVPWRVLD VBUSPWRVLD VBUSPWRD DISKRDY SYSIRQ IORDY DMARQ nEJECT ATAIRQ Will always return ‘1’ LOWPWR Reserved – Disregard value nPWR500 nATARST nDIOW nDIOR nDMACK ATAPUEN Reserved – Disregard value nCS[1:0] DA[2:0] DD[7:0] DD[15:8] GPIO[2:0] Will always return ‘0’ DD_EN GPIO_EN[2:0] MFG_SEL (manufacturing test mode enable) ATAEN Will always return ‘1’ Will always return ‘1’ Pin Name 10.0 Absolute Maximum Ratings Storage Temperature ................................................................................................................................................ –65 to 150°C Ambient Temperature with power supplied ..................................................................................................................... 0 to 70°C Supply Voltage to Ground Potential ...........................................................................................................................–0.5 to 5.5 V DC Input Voltage to Any Input Pin .............................................................................................................................–0.5 to 5.5 V DC Voltage Applied to Outputs in high-Z ...................................................................................................................–0.5 to 5.5 V Power Dissipation .............................................................................................................................................................235 mW Static Discharge Voltage (Meets NEC ASIC ESD specifications IEC-GQ-6002-01 and IEC-6005-01) ...........................> 2000 V Max Output Current per I/O port ..........................................................................................................................................20 mA Latch-up Current .............................................................................................................................................................> 200 mA Document 38-08030 Rev. *H Page 30 of 34 CY7C68310 11.0 Operating Conditions Operating temperature.................................................................................................................................................... 0 to 70°C 12.0 VDD VDDA VDDIO VIH VIL VOH VOL IOH IOL InCFG ICC DC Characteristics Description Digital voltage supply Analog voltage supply I/O cell voltage supply Input high voltage Input low voltage Output high voltage at IOH Output low voltage at IOL Source current at VOH Sink current at VOL Unconfigured Full-speed current High-speed Configured idle Full-speed High-speed Configured operational Full-speed High-speed Compact Flash 2.5” HDD (See Note) 3.5” HDD (See Note) 2.5V Supply 3.3V Supply 2.5V Supply 3.3V supply 2.5V Supply 3.3V Supply 2.5V Supply 3.3V Supply 2.5V Supply 3.3V Supply 2.5V Supply 3.3V Supply 6 6 40 60 36 2 55 2 53 11 65 6 73 9 74 19 250 0.7 10 Min. 2.25 2.25 3.0 2.0 –0.5 2.4 0.4 Typ. 2.50 2.50 3.3 Max. 2.75 2.75 3.6 VDDIO + 0.5 0.8 Unit V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA µA Parameter ISUP ISLP Current in USB suspend (inactive, connected) Current in Sleep mode (inactive, unconnected) Note: All values in this table assume 25°C ambient temperature and nominal voltage unless otherwise stated. All “Configured operational” measurements assume a 50/50 read/write duty cycle. 13.0 Ordering Information [Package Type 80-Lead TQFP 80-Lead TQFP Lead-Free Package CY7C68310 Mass Storage Reference Design Kit Part Number CY7C68310-80AC CY7C68310-80AXC[1] CY4617 Note: 1. The Lead-Free option should be used for new designs. It is recommended that existing designs migrate to Lead-Free parts. Document 38-08030 Rev. *H Page 31 of 34 CY7C68310 14.0 Package Diagram 80-lead Thin Plastic Quad Flat Pack (12 x 12 x 1.0 mm) A8012x12 51-85175-** Figure 14-1. 80-pin TQFP Package Diagram 15.0 • Isolate the DP and DM traces from all other signal traces by no less than 10 mm. The CY7C68310 contains high-speed analog circuitry that is • The DP and DM common mode trace impedance should be sensitive to system noise. In particular, noise on both analog controlled to 45Ω with total differential impedance controlled and digital power supplies must be minimized to ensure to 90Ω (±10%). reliable, high-performance operation. Special attention should • The VDD power plane should be as solid as possible with also be given to the design of the frequency generation, direct paths from the voltage regulator to all discrete comvoltage reference, and USB interface circuits. Cypress recomponents. A four layer board is required with inner layers mends using the following guidelines in designing any product dedicated to power and ground planes. Digital ground that uses the CY7C68310. should cover one entire layer of the design. • The 3.3V power rail must remain above the 2.5V rail at all • Analog and digital power planes must be isolated using intimes for proper device operation. ductors. • DP and DM trace lengths should be kept to within 2 mm of • Ceramic or tantalum capacitors are required. Do not use each other and must not exceed 37 mm in total length, with electrolytic capacitors. Electrolytic capacitors have higher a preferred length of 20–30 mm. lead inductance and series resistance values that have • Maintain a solid ground plane under the DP and DM traces. been observed to contribute to increased power supply Do not allow the plane to be split under these traces. noise. • Do not place vias on the DP or DM traces. • Adequate bypass capacitance must be implemented very near to the CY7C68310 power pins. One ceramic bypass capacitor per power/ground pair is recommended. • All termination and pull-up resistors (including DP and DM) should be placed within 5 mm of the CY7C68310 pins. • The crystal and RREF external resistor components should be placed as near the CY7C68310 pins as possible. PCB Layout Recommendations Document 38-08030 Rev. *H Page 32 of 34 CY7C68310 16.0 Disclaimers, Trademarks, and Copyrights Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ISD-300LP is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document 38-08030 Rev. *H Page 33 of 34 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C68310 Document History Page Description Title: CY7C68310 ISD-300LP™ Low-Power USB 2.0 to ATA/ATAPI Bridge IC Document Number: 38-08030 REV. ** *A *B *C *D ECN No. Issue Date 118297 120307 123509 126049 126323 09/18/02 12/12/02 04/04/03 04/07/03 05/21/03 Orig. of Change BHA GIR GIR CVR GIR New Data Sheet Revised for Preliminary status Revised to include first silicon information Post to external website CY7C68310-80AC Updated Suspend Current and included Sleep Mode in Section 12.0 Added ESD Testing Methodology and Power Dissipation values to Section 10.0 Revised for Final status Changed Static Discharge voltage to > 2000V(1) Replaced previous Status Discharge footnotes with the following: “1. Meets NEC ASIC ESD specifications IEC-GQ-6002-01 and IEC-6005-01” Changed DC Specification ISLP