CY7C955

PRELIMINARY CY7C955 AX™ ATM-SONET/SDH Transceiver Features • WAN and LAN ATM physical layer device • Provides complete physical layer transport of ATM cells at: — STS−3c/ STM −1 rate of 155.52 MHz — STS−1 rate of 51.84 MHz • Compliant with ATM Forum User Network Interface 3.1 specification • UTOPIA ATM interface • ATM cell processing including: — HEC generation/verification — Cell scrambling/descrambling — Rate adaption/idle cell filtering — Local Flow Control — Cell alignment • SONET frame processing including: — Compliant with Bellcore GR−253, I.432, T1.105, and G.709 for Jitter Tolerance and Jitter Generation — Frame generation/recovery — SONET scrambling/descrambling — Frequency justification/pointer processing • Complete line interface including: — Clock and data recovery — Transmit timing derived from receiver or byte-rate source — SONET compliant PLL — 100K PECL compatible I/O Alarm indications including: • — Loss Of Signal — Out Of Frame, Loss Of Frame — Line Far End Receive Failure — Line Alarm Indication Signal — B1 Parity Error — Loss Of Cell Alignment — Loss Of Receive Data • Controller interface for internal interrupt and configuration registers including: — Error monitoring — Status indication — Device configuration • 0.65µ Low Power CMOS • 128-pin PQFP Functional Description The Cypress Semiconductor CY7C955 is a Transceiver chip designed to carry ATM cells across SONET/SDH systems. On the transmit side, ATM cells coming from the Utopia interface are being mapped into SONET/SDH frames and then serialized for transmission over fiber or twisted pair (through an optical module or an equalizer chip). On the receive side, serial SONET/SDH datastreams coming from an optical module or an equalizer chip are being recovered by the intergrated clock and data recovery phase-locked loop, framed, processed, and presented as parallel ATM cells on the Receive Utopia Interface. The CY7C955 can be used in a Network Interface Card (NIC) design to connect the segmentation and Reassembly (SAR) chip to the optical modules or equalizer chip. The CY7C955 can also be used in work group or enterprise switches to connect the I/O FIFOs of the switch fabric to the optical module or equalizer in the interface boards. The applications of the CY7C955 include adapters, switches, routers, hubs, and proprietary systems. TABLE OF CONTENTS Features Functional Description Pin Descriptions Pin Configuration Description Transmit Section Receive Section Controller Interface (CI) Loopback Operation SONET Overhead Description CY7C955 Register Map Electrical Characteristics Capacitance AC Test Loads and Waveforms Switching Characteristics 1 1 2 7 8 8 10 12 16 17 18 60 61 61 61 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 29, 1999 PRELIMINARY TABLE OF CONTENTS (continued) Switching Waveforms Functional Timing Diagram Interface Termination and Biasing Schemes Filter Pin Configuration Ordering Information Package Diagram CY7C955 63 69 73 75 76 77 TDAT[7:0] TXPRTY TSOC TFCLK TWRENB TCA TCP TGFC XOFF Transmit UTOPIA I/F Transmit FIFO 4 Cell by 8 bit D[7:0] A[7:0] ALE RDB WRB CSB INTB RSTB RALM Transmit ATM Cell Processor Transmit Path Overhead Processor Transmit Line Overhead Processor TCLK TFPO Transmit Section Overhead Processor TBYP RATE0 RATE1 Controller Interface Configuration and Status Register File Error Monitoring Transmit Clock Multiplier & Transmit Buffer TXD± TXC± TRCLK± Rate Selection SONET/SDH Clock Recovery Receive UTOPIA I/F Receive FIFO 4 Cell by 8 bit Receive ATM Cell Processor Receive Path Overhead Processor Receive Line Overhead Processor Receive Section Overhead Processor ALOS± RRCLK± RXD± RXDO± TSEN RDAT[7:0] RXPRTY RSOC RFCLK RRDENB RCA RCP RGFC RCLK RFP RBYP 7C955−1 Pin Descriptions CY7C955 ATM-SONET/SDH Transceiver Transmit Utopia Interface Name TDAT[7:0] TPRTY TSOC Pin 87−94 95 96 I/O Input Input Input Description Transmit Utopia data: Byte-wide data driven from the ATM to PHY layer. TDAT[7] is the MSB. Transmit Utopia Data Parity: Data parity calculated over TDAT[7:0]. Odd parity is assumed unless the TXPTYP bit (Reg–63, bit 7) is set to even parity Transmit Utopia Start of Cell: Assert TSOC HIGH when TDAT[7:0] contains the first byte of an ATM cell. If TSOC is asserted sooner than 53 writes after the previous SOC, an error condition will be generated. This input is optional after the first TSOC pulse. Transmit Utopia Clock: Data transfer clock. Data is transferred to the AX on the rising edge of TFCLK when TWRENB is asserted (LOW). Transmit Utopia Data Enable: Enables the TFCLK input for data transfer to the AX. This signal is active LOW. TFCLK TWRENB 84 85 Input Input 2 PRELIMINARY Transmit Utopia Interface (continued) Name TCA Pin 86 I/O Output Description CY7C955 Transmit Utopia Cell Available: An active state on this signal indicates that the Transmit FIFO can accept at least N more cells (53 octets) of data where N and the active state of the signal (HIGH or LOW) are programmable through the configuration registers (Reg−63H and Reg−01H). In a special case, if Reg–63H bit2−3 is set to 00, Reg−01H, bit 3 is set to 0, and TCALEVEL0 (Reg–63H, bit 1) set to 0. TCA will behave as an active HIGH FULL indicator. Transmit ATM Interface Name XOFF Pin 50 I/O Input Description Transmit Idle Cell: A HIGH state on this pin will force the ATM Cell Processor to send an IDLE cell even if there are cells to send in the Transmit FIFO. XOFF is an asynchronous input and has an integrated pull down resistor. Transmit Generic Flow Control: This bit serial input provides the ability to overwrite the four bits of the ATM cell header GFC field. These bits may be optionally written during the four TCLK clock periods following the assertion of the TCP output. Transmit Start Of GFC: This indicates that the first bit of the GFC for the next cell read from the Transmit FIFO is expected on the TGFC pin during the next rising edge of TCLK. TGFC 52 Input TCP 51 Output Transmit Clock Generator Name TRCLK± Pin 9−10 I/O Differential In Description Transmit Input Clock: Accepts either a differential PECL, or a TTL or a CMOS byte rate reference connected to TRCLK− with TRCLK+ grounded for the Transmit frequency multiplier PLL. Optionally, this input can accept also the bit rate reference when TBYP is true (held HIGH). In this mode the Transmit frequency multiplier is bypassed and the bit rate clock is used directly for transmit side clocking. Transmit Output Clock: Provides clock output for the transmit data. TXD± is updated on the falling edge of this signal. In the default setting, TXC is disabled if RATE0 is HIGH and a 51.84-MHz clock if RATE0 is LOW. XORTXC (Reg−04H, bit 6) can be used to invert the default setting such that TXC is a 155.52-MHz clock if RATE0 is HIGH and is disabled when RATE0 is LOW. Transmit Data Output: Accepts NRZ encoded output data. This signal is updated on the falling edge of TXC±. Transmit Clock Bypass: When this input is held HIGH the transmit frequency multiplier is disabled and TRCLK± input is used directly for transmit side clocking. When this input is held LOW the transmit frequency multiplier multiplies the TRCLK± input by 8, 24, or 8/3 (depending on the TREFSEL (Reg−06H, bit 0) setting to provide the internal bit rate clock. RATE: When the RATE0 input is HIGH the Transmit frequency generator and the Receive clock recovery are selected to operate at the STS −3c/STM−1 rate of 155.52 MHz. When the RATE0 pin is LOW, the Transmit frequency generator and the Receive clock recovery are selected to operate at the STS−1 rate of 51.84 MHz. RATE1 is for factory testing use only and should be tied HIGH. Both RATE0 and RATE1 have integrated pull-up resistors. Transmit Byte Reference: Byte rate reference clock derived from the transmit line bit rate. Transmit Frame Reference. This signal is an 8-kHz frame rate reference that goes HIGH during the transmission of the first A1 byte of the SONET/SDH frame. TFPO is updated by the rising edge of TCLK. TXC± 13−14 Differential Out TXD± TBYP 15−16 2 Differential Out Input RATE0 RATE1 97−98 Input TCLK TFPO 54 53 Output Output Receive Clock Recovery Name RXD± Pin 25−26 I/O Differential In Description Receive Input Data: These line receiver inputs are connected to an internal Receive PLL that recovers the embedded clock and data information. The incoming data rate can be within one of two frequency ranges depending on the state of the RATE0 pin. 3 PRELIMINARY Receive Clock Recovery (continued) Name RXDO± Pin 22−23 I/O Differential Out Description CY7C955 Receive Output Data: These differential outputs represent the retimed version of the input data stream (RXD±) in normal mode and the buffered version of the input datastream (RXD±) in bypass mode. This output pair can be used as inputs to decision feedback equalizers to correct for baseline wander. RXDO can be turned off to save power by setting RXDOD (Reg−04H, bit 7) to 1. Receive Clock: These inputs are used to clock in the differential data (RXD ±) when the Receive clock recovery block is bypassed (RBYP=HIGH). If RBYP is LOW, RRCLK is multiplied by 8, 24, or 8/3 depending on the setting of RREFSEL (Reg−07H, bit 0) and use as a reference for the Receiver PLL. Refer to the section on “Interface Termination and Bias of Schemes” for connection examples to these pins. Receive Clock Bypass: When this input is HIGH the Receiver clock recovery block is bypassed. In this mode the device does not recover clock and data from the Receive input data stream (RXD±) but instead uses the RRCLK± inputs to clock the differential data into the device. When this input is LOW the Receiver clock recovery block recovers the clock and data from the input data stream. In this mode a byte-rate clock is expected on the RRCLK± inputs. Receive Byte Reference: Provides a byte-rate reference derived from the recovered bit- rate Receive clock. RALM, RCP, and RGFC are aligned with this clock. Receive Frame Reference: This output provides a frame-rate reference clock aligned to the SONET/SDH frame alignment bytes. RFP will pulse HIGH for one RCLK cycle every 125 seconds even at OOF and LOF situations. NC. This pin is for factory testing only. These are the PLL filter pins. Connect a 0.47-µF capacitor across LF– and LFO. RRCLK± 33−34 Differential In RBYP 41 Input RCLK RFP 57 58 Output Output LF+ LF–, LFO 42 43, 44 Input Input Receive ATM Interface Name RGFC Pin 59 I/O Output Description Receive Generic Flow Control: This output provides the four bits of the current ATM cell header GFC locations at each successive RCLK pulse. The RCP output indicates the first GFC bit location. This output is forced LOW if the ATM Cell Processor has lost cell delineation. Receive Interrupt: This active HIGH signal is aligned with the RCLK byte-rate clock and signals the presence of LAIS, PAIS, LOS, LOF, LOP, or LCD. Receive Start Of GFC: This output indicates the first bit of the GFC presented on the RGFC output. This output goes HIGH for 1 RCLK cycle 6 byte times after the corresponding cell is written into the Receive FIFO. RALM RCP 63 60 Output Output Receive Utopia Interface Name RDAT[7:0] RPRTY RSOC RFCLK RRDENB RCA Pin No 70−71 74−79 82 83 67 68 69 I/O Output Output Output Input Input Output Description Receive Utopia Data: Byte-wide data driven from the PHY to ATM layer. RDAT[7] is the MSB Receive Utopia Data Parity: Data parity calculated over RDAT[7:0]. Odd parity is assumed unless the TXPRTY bit is set to even parity by Reg−50H, bit 6. Receive Utopia Start of Cell: Asserted HIGH when RDAT[7:0] contains the first byte of an ATM cell. Receive Utopia Clock: Data transfer clock. Data is transferred from the AX on the rising edge of RFCLK when RRDENB is asserted (LOW). Receive Utopia Enable: Enables the RFCLK input for data transfers from the AX. Receive Utopia Cell Available: An active signal indicates that the Receive FIFO contains at least 1 or 4 more bytes of data. RCA is controlled by RCAINV (Reg−01H, bit 2) and RCALEVEL0 (Reg−59H, bit 2). 4 PRELIMINARY Receive Utopia Interface (continued) Name TSEN Pin No 66 I/O Input Description CY7C955 Receive Output Enable: This output operates in conjunction with the RRDENB output. When TSEN is HIGH and RRDENB is HIGH the Receive UTOPIA data bus (RDAT[7:0], RPRTY, and RSOC) is three-stated. When TSEN is HIGH and RRDENB is LOW the data bus is driven with the requested data. When TSEN is LOW the data bus will not three-state. Controller Interface Name D[7:0] A[7:0] ALE Pin No 110−112 115−118 119−126 127 I/O I/O Input Input Description Data[7:0]: Bidirectional data bus used to transfer data to and from the internal configuration, status, and error monitoring registers. Address[7:0]: Address bus used to select the internal register for reading or writing. Address Latch Enable: When this input is LOW the address is latched from the A[7:0] inputs. When this input is HIGH, the input is transparent. ALE has an integrated pullup resistor. Read: This active LOW signal is used to read the internal register. The AX drives D[7:0] when RDB and CSB are both LOW. Write: This active LOW signal is used to write the internal registers. Data is latched into the specified address register on the rising edge of WRB when CSB is LOW. Select: This active LOW device select has to be enabled during register accesses. Interrupt: This active LOW open drain output transitions LOW when an unmasked interrupt source is active. This output transitions HIGH when the appropriate register has been read. This interrupt signals the most critical error states of the device including Loss of Pointer, Line Alarm Indication Signal (LAIS), Line Far End Receive Failure (LFERF), Loss of Frame (LOF), Out of Frame (OOF), Loss of Signal (LOS), and many others. Carrier Detect: This differential input controls the recovery function of the Receive PLL and can be driven by the carrier detect output from optical modules or from external transition detection circuitry. When this input is at a Logic Low, the input data stream (RXD±) is recovered normally by the Receive Clock Recovery PLL. When this input is at a Logic High, the Receive PLL no longer aligns to RXD±, but instead aligns with the RRCLK * 8 frequency and the LOS alarm register (RDOOLV) will be set. Besides differential PECL, the ALOS − input can be set to accept single ended PECL input if ALOS+ is tied to GND. ALOS− has to be decoupled. Reset: This active LOW signal provides a device reset. This line can be pulled LOW to put the CY7C955 into the power-down mode. RSTB has an integrated pull-up resistor. Factory test pin. Must be LOW for normal operation. VCLK has an integrated pull-down resistor. RDB WRB CSB INTB 105 104 100 108 Input Input Input Output ALOS± 27−28 Differential In RSTB 101 Input VCLK 99 Input Transmit Power Name TXVDD Pin No 12 I/O Power Description The Transmit Pad Power supplies the TXD± outputs. TXVDD is physically isolated from the other device power pins and should be well regulated +5V DC and noise-free for good performance when driving category 5 unshielded twist pair cabling. The power pin for the transmit clock synthesizer reference circuitry. TAVD1 should be connected to analog +5V. The power pin for the transmit clock synthesizer oscillator. TAVD2 should be connected to analog +5V. The power pin for the transmit PECL inputs. TAVD3 should be connected to analog +5V. Power for TXC ± and RXDO ±. TAVD1 TAVD2 TAVD3 TVDDO 4 6 8 18 Power Power Power Power 5 PRELIMINARY Receive Power Name RAVD1 RAVD2 RAVD3 RAVD4 Core Power Name VDDI VDDO Pin No 20, 61, 107 55, 73, 81, 114 I/O Power Power Description Pin No 30 36 24 32 I/O Power Power Power Power Description CY7C955 The power pin for receive clock and data recovery block reference circuitry. RAVD1 should be connected to analog +5V. The power pin for receive clock and data recovery block active loop filter and oscillator. RAVD2 should be connected to analog +5V. The power pin for the RXD± and ALOS± PECL inputs. RAVD3 should be connected to analog +5V. The power pin for the RRCLK± PECL inputs. RAVD4 should be connected to analog +5V. The core power pins should be connected to a well decoupled +5V DC in common with VDDO. The pad ring power pins should be connected to a well decoupled +5V DC in common with VDDI. Ground Name TAVS1 TAVS2 TAVS3 TXVSS Pin No 5 7 11 17 I/O Ground Ground Ground Ground Description The ground pin for the transmit clock synthesizer reference circuitry. TAVS1 should be connected to analog GND. The ground pin for the transmit clock synthesizer oscillator. TAVS2 should be connected to analog GND. The ground pin for the transmit PECL inputs. TAVS3 should be connected to analog GND. The transmit pad ground is the return path for the TXC± and TXD± outputs. TXVSS is physically isolated from the other device ground pins and should be noise-free for good performance when driving category 5 unshielded twisted pair cabling. The ground pin for receive clock and data recovery block reference circuitry. RAVS1 should be connected to analog GND. The ground pin for receive clock and data recovery block active loop filter and oscillator. RAVS2 should be connected to analog GND. The ground pin for the RRCLK ± PECL inputs. RAVS3 should be connected to analog GND. The ground pin for the RSD± and ALOS± PECL inputs. RAVS4 should be connected to analog GND. This pin is grounded for TXC± and RXDO±. The core ground (VSSI) pins should be connected to GND in common with VSSO. The pad ring ground (VSSO) pins should be connected to GND in common with VSSI. RAVS1 RAVS2 RAVS3 RAVS4 RVSSO VSSI VSSO 31 37 29 35 21 19, 62, 106,48 56, 72, 80, 113, 49 1, 38, 39, 46, 47, 64, 65, 102, 103, 128 40, 3, 46 Ground Ground Ground Ground Ground Ground Ground VSS Ground These pins must be connected to GND for correct operation. ATP1, ATP2, ATP3 I/O These Analog Test Points (ATPx) are for factory testing use only. These pins have to be tied to GND for correct chip operation. 6 PRELIMINARY Pin Configuration 128-pin PQFP Top View D[7] D[6] D[5] D[4] VDDO VSSO D[3] D[2] D[1] D[0] INTB VDDI VSSI RDB WRB VSS VSS ALE A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] CY7C955 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS TBYP ATP2 TAVD1 TAVS1 TAVD2 TAVS2 TAVD3 TRCLK– TRCLK+ TAVS3 TXVDD TXC+ TXC– TXD+ TXD– TXVSS TVDDO VSSI VDDI RVSS RXDO+ RXDO– RAVD3 RXD– RXD+ ALOS– ALOS+ RAVS3 RAVD1 RAVS1 RAVD4 RRCLK– RRCLK+ RAVS4 RAVD2 RAVS2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 108 107 106 105 104 103 CY7C955 AX ATM SONET / SDH TRANSCEIVER 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS RSTB CSB VSS RATE[0] RATE[1] TSOC TPRTY TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TCA TWRENB TFCLK RSOC RPRTY VDDO VSSO RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] VDDO VSSO RDAT[1] RDAT[0] RCA RRDENB RFCLK TSEN VSS 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSS ATP1 RBYP LF+ LF− LFO ATP3 VSS VSS VSSI VSSO XOFF TCP TGFC TFPO TCLK VDDO VSSO RCLK RFP RGFC RCP VDDI 7 VSSI RALM VSS 7C955−2 PRELIMINARY Description Transmit Section Transmit Utopia Interface (TUI) The transmit interface provides a simple access from the external environment to the ATM Transceiver. The operation of this interface is compliant with the Utopia interface specification. The interface provides a 9-bit by 4-cell FIFO to decouple the system interface from the ATM physical layer timing. 9-bit words are clocked into the device through a clocked FIFO system interface. These 9 bits include an 8-bit data word along with a Start Of Cell (SOC) indication. The interface also provides full and almost full indications (TCA). Maximum clock rate for this interface is 33 MHz. Transmit ATM Cell Processor (TACP) The ATM cell processor provides HEC generation, idle/unassigned cell header modification, payload scrambling, and GFC insertion. HEC Generator The Header Error Check (HEC) code is contained in the last byte of the ATM cell header and is capable of single error correction and multiple error detection. When optionally generated, the Transmit ATM Cell Processor calculates a CRC−8 over the first four bytes of the ATM cell header using the polynomial x8 + x2+ x + 1. The coset x6 + x4 + x2 + 1 is added (modulo 2) to the residue of this function. The HEC is calculated in accordance with ANSI T1.624 −1993 and CCITT Recommendation I.432. This HEC sequence is placed in the 5th byte of the ATM cell header. Idle/Unassigned Cell Header Modification Idle (Unassigned) cells are sent by the ATM cell processor whenever a complete cell is not contained within the Transmit FIFO. This transforms the non-continuous cell input stream into a continuous stream of assigned and unassigned cells. The ATM cell processor provides the ability to overwrite the Generic Flow Control (GFC), the Payload Type Indication (PTI), and the Cell Loss Priority (CLP) fields of Idle (Unassigned) cells with the values contained in the corresponding configuration registers. VPI and VCI are set to zero in Idle (Unassigned) cells. Payload Scrambler The 48 bytes of the ATM payload are scrambled using a parallel implementation of the polynomial x43 + 1 as described in CCITT Recommendation I.432. The scrambler can be optionally deselected. GFC Insertion The transmitted GFC field of an ATM cell can be derived from different sources. For assigned cells, the default is from pins TDAT[7:0]. For Idle (Unassigned) cells, the default is from GFC[3:0] (Reg−61H, bit 7−bit 4). However, if any bit of TGFCE[3:0] (Reg−67H, bit 7−bit4) is set, the corresponding transmitted GFC location will instead be taken from the serial TGFC (pin 52) input following the functional timing specifications described in the section on Transmit GFC Serial Link Interface. CY7C955 Transmit SONET Path Overhead Processor (TPOP) The SONET path overhead processor provides payload pointer alignment (H1, H2), path overhead insertion, and insertion of the Synchronous Payload Envelope (SPE). ATM cells (both assigned and unassigned) are inserted into the SPE for transmission in the SONET frame SONET Overhead Insertion The SONET/SDH STS −3c/STM−1 frame structure is shown in Figure 1 and the SONET STS−1 frame structure is shown in Figure 2. The SONET frame occurs once every 125 µs and is transmitted beginning with the A1 bytes, followed by the A2 bytes, C1 bytes, 261 bytes (87 bytes for STS−1) of the Synchronous Payload Envelope (SPE), B1 bytes, etc., until the entire frame is transmitted. The TPOP generates the H1 and H2 bytes that indicate the beginning of the SPE and the H4 byte that indicates the ATM cell offset within the SPE. The default initial value for H1 and H2 pointer is 522, meaning that the first byte of the SPE (J1) corresponding to a frame actually starts after the C1 byte of the next frame. In the default case described above, a 6h is present in the New Data Flag (NDF) portion of the first H1 (bits 0−4), a 2h is present in bits 5−7 and a 0Ah is present in the first H2 byte. The remaining H1 bytes for STS −3c/STM−1 are set to 93h and the remaining H2 bytes are set to FFh which is the concatenation indication for the J1 pointer. The Pointer Action byte, H3, is set to 00h. During Path AIS all of the H1 and H2 bits are set to 1. The STS path trace J1 is set to all zeros. The path BIP−8 (B3) byte provides path error monitoring. This function calculates the bit-interleaved parity-8 code using even parity over the previous SPE before scrambling and is inserted into the current B3 byte before scrambling. Bit-interleaved parity-8 forces the number of 1s in the xth bit of every byte in the previous SPE plus the xth bit of the B3 byte in the current SPE to be an even number. The path signal level indicator, C2, defaults to 13h. The path status, G1, has several functions. Bits 1 through 4 are used to indicate Far End Block Errors (FEBE) derived by counting the number of BIP−8 errors occurred in the last frame received. Valid codes are 0 through 8. If more than 8 errors have accumulated since the last, frame the maximum value is sent with the current frame, the FEBE counter is decremented by 8, and the remaining errors are sent with the next frame. FEBE may be inserted through register control for diagnostic purposes. Bits 1 through 4 can also be used to transmit Far End Receive Failures by setting these bits to 9 (1001). This error indicates to the far end that cell delineation has been lost. Bit 5 can be used to generate a yellow alarm condition. The default value for this bit is 0 (no alarm). The multi-frame indicator, H4, is used to indicate the first ATM cell and may take on values of 00 to 34h. The remaining bytes, F2, Z3, Z4, and Z5, are not used by the SONET path processing and are set to 00h upon transmission. When operating in STS −1 mode, SPE columns 30 and 59 can be configured as fixed stuff columns. 8 PRELIMINARY . CY7C955 Section A1 A1 A1 A2 B1 D1 E1 D2 A2 A2 C1 C1 C1 Path J1 B3 C2 G1 F2 Payload H4 Z3 Z4 Z5 HD1 HD2 HD3 HD4 HEC PAYLOAD F1 D3 H2 H2 H3 H3 H3 K2 D6 D9 D12 Z2 E2 B2 B2 B2 K1 Line D4 D7 D10 D5 D8 D11 Payload Z1 Z1 Z1 Z2 Z2 9 Bytes 261 Bytes 7C955−3 Figure 1. STS −3c/STM−1 Framing Format Section A1 A2 B1 E1 C1 Path F1 D1 D2 D3 H1 H2 B2 K1 Line H3 K2 J1 B3 C2 G1 F2 Payload H4 Z3 Z4 Z5 HD1 HD2 HD3 HD4 HEC PAYLOAD D4 D5 D6 D7 D8 D9 D10D11 D12 Z1 Z2 E2 Payload 3 Bytes 87 Bytes 9 Bytes 7C955−4 Figure 2. STS−1 Framing Format 9 9 Bytes H1 H1 H1 H2 PRELIMINARY Transmit SONET Line Overhead Processor (TLOP) The Transmit SONET line overhead processor (TLOP) provides BIP−8/24 generation and line level alarms. The BIP−8/24 code is calculated as if the STS−3c frame was composed of three STS−1s. The first B2 byte is calculated over the first STS−1 frame, the second B2 byte over the second STS−1 frame and the third B2 byte over the third STS−1 frame. Each B2 bit is calculated over the line and SPE portions of the previous frame before scrambling using even parity and inserted into the current frame before scrambling. For STS−1 RATE, a BIP−8 is calculated over the entire SPE and line overhead and placed in B2. The Line Alarm Indication Signal (LAIS), is asserted by changing all bits of the SONET frame into 1 before scrambling. LAIS generation is controlled by a register setting (Reg−14H, bit 0). The Line Far End Receive Failure (LFERF), also called Line RDI, is indicated by placing a 110 pattern in bits 6,7, and 8 of the first K2 byte. LFERF can be asserted under register (Reg−20H, bit 0) control. The Line Far End Block Errors (LFEBE) are located in the third Z2 byte and indicate the number of B2 errors in the previous frame interval. Legal values for this byte are 00h through 18h. All bytes of the line data communication channel (D4−D12) and all other unused bytes are encoded to 00h. Transmit SONET Section Overhead Processor (TSOP) The Transmit SONET Line Overhead Processor (TSOP) provides A1,A2 framing pattern generation, section BIP −8 (B1) insertion, section level alarm insertion, and frame scrambling. The A1 and A2 bytes provide a framing pattern for frame alignment. All A1 bytes are coded to F6h and all A2 bytes are coded to 28h. These bytes are not scrambled upon transmission. The STS−1 identification bytes, C1, are used for framing and de-interleaving purposes and are coded the order in their appearance in the STS−3c frame. The first C1 byte is coded to 01h, the second to 02h, and the third to 03h. The section BIP−8 (B1) is the byte-interleaved parity-8 calculated over all bytes of the previous frame after scrambling and inserted into the current frame before scrambling. The bytes of the section data communication channel, D1−D3 and the remaining unused bytes are set to 00h. The frame is scrambled prior to transmission with the generating polynomial x7 + x6 + 1. The A1, A2, and C1 bytes are not scrambled. The scrambler runs continuously through the frame and resets at the beginning of the next transmission frame. The scrambler may be optionally disabled. Transmit Clock Generator (TCG) The TCG accepts a byte-rate transmit clock from TRCLK that operates at either 19.44 MHz for STS −3c/STM−1 RATE or at 6.48 MHz for STS−1 RATE. The Transmit PLL multiplies this byte-rate reference by eight to produce the bit-rate clock used by the parallel-to-serial converter. Optionally a bit-rate source can be taken from an external source (TBYP = 1) or from the Receive Clock Recovery block when in loop-time mode (LOOPT = 1). In loop-time mode the recovered clock is used to provide timing to the transmitter. Parallel to Serial Converter (PSC) CY7C955 The PSC converts the parallel data from the TSOP to serial data. The bit rate clock is derived from the Transmit Clock Generator. The serialized data and aligned output clock are presented to the Transmit Output Multiplexer. Transmit Output Multiplexer (TOM) The TOM selects between the serialized output data stream and associated clock provided by the PSC and the recovered data and clock from the Receive Clock Recovery block for transmission based on the state of the local loop back enable (LLE) register (Reg−05H, bit 2). When LLE = 1 the recovered data and recovered clock is selected for output on the transmit data lines (TXD±) and the transmit clock lines (TXC ±). The output signal is 100K compatible differential Positive-referenced ECL (PECL) signal capable of driving any copper or fiber based media with impedances as LOW as 50Ω. Receive Section Receive Clock Recovery (RCR) The RCR provides clock and data recovery from an incoming differential PECL data stream. Clock and data are recovered from the incoming differential PECL data stream without the need for external buffering and AC-coupling. The built-in line receiver inputs have a wide common-mode range (2.5−5V) and the ability to receive signals with as little as 200 mV differential voltage. They are compatible with all PECL signals. They are compatible with all PECL signals driven by optical modules or twisted-pair equalizers. The Receive PLL uses the RRCLK as a byte-rate reference. This input is multiplied by 8 and is used to improve PLL lock time and to provide a center frequency for operation in the absence of input data stream transitions. The receiver can recover clock and data in two different frequency ranges depending on the state of the RATE0 pin. To insure accurate data and clock recovery, the received data stream must be within 1000 ppm of RRCLK * 8 (The PLL will declare Out Of Lock if the data rate is different from REFCLK x 8 by more than 2000 ppm. The PLL will remain Out Of Lock until the data rate pulls back to within 700 ppm of REFCLK x 8 frequency). The standards, however, specify that the RRCLK*8 frequency accuracy be within 20−100 ppm. The wider frequency tolerance range of the CY7C955 is an advantage that allows for higher frequency tolerance in bench testing setups. A Loss of Signal (ROOLV = 1) is declared when no transitions have been detected on the incoming data stream for more than 512 bit-times. LOS is cleared when two valid framing patterns (A1, A2) have been found and the intervening data does not contain a period that violates the minimum transitions limit. Serial to Parallel Conversion (SPC) The SPC converts bit serial data to byte serial data from either the recovered received data or the transmit data from the PSC depending on the state of the DLE register (Reg−05H, bit 1). When DLE =1 transmit data is used for serial to parallel conversion. The SPC also provides SONET framing by scanning the incoming data for the SONET framing pattern A1, A2. For STS−1 RATE the framer looks for the pattern F628h and for STS−3 RATE the framer looks for the pattern F6F6F6282828h. Out of Frame (OOF) is declared when four consecutive frames contain a framing error. OOF clears when two frames contain valid framing characters. Loss of Frame 10 PRELIMINARY (LOF) is declared when the OOF condition fails to clear within 3 ms. LOF clears after 3 ms of frames with valid framing characters. Receive SONET Section Overhead Processor (RSOP) The RSOP provides descrambling, SONET section alarm indication, and error monitoring. The data is descrambled using the generating polynomial 1 + x6 + x7. The A1, A2, and C1 bytes are not descrambled. The scrambling process may be disabled under register control. The BIP−8 value calculated over the previous scrambled frame is compared with the B1 byte of the current frame section overhead after descrambling. If the two values do not match, the B1PAR output is taken HIGH. Up to 64,000 errors can be detected per second (8000 frames/second * 8 bit-errors (max)/frame). Errors are recorded in a 16-bit saturating counter that can be read through the controller interface. Receive SONET Line Overhead Processor (RLOP) The RLOP provides SONET line alarm indications and error monitoring. A Line Alarm Indication Signal (LAIS) is asserted when a 111 pattern is detected for five consecutive frames in bits 6,7, and 8 of the first K2 byte of the Automatic Protection Switching channel. LAIS is removed when anything other than a 111 pattern is received for five consecutive frames. A Line Far End Receive Failure (LFERF) or Line RDI is indicated with a 110 pattern is detected for five consecutive frames in bits 6,7, and 8 of the first K2 byte. LFERF is removed when anything other than a 110 pattern is received for five consecutive frames. The BIP−24 (BIP −8 for STS−1 RATE) value calculated over the previous line overhead and SPE is compared with the B2 bytes of current frame. Up to 192,000 errors can be detected per second (3 channels/frame * 8 errors (max)/channel * 8000 frames/second). Errors are recorded in a 20-bit saturating counter that can be read through the controller interface. Far End Block Errors (FEBE) are detected by examining the value in the third Z2 byte. This value (0−18h) is added to the count in an 18-bit saturating counter that can be read through the controller interface. Receive SONET Path Overhead Processor (RPOP) The RPOP provides pointer interpretation, SPE extraction, SONET path alarm indications, and error monitoring. The payload location is determined by examining the values in the H1 and H2 bytes of the line overhead which indicate the J1 byte of the SPE. The RPOP can process a J1 byte located anywhere in the SPE. Loss of Pointer (LOP) is set when a valid pointer value has not been found within eight consecutive frames. This register bit is cleared when a valid pointer is found for three consecutive frames. Path Alarm Indication Signal (PAIS) (Reg30H, bit 3) is set when the H1 and H2 bytes are set to all ones for 3 consecutive frames. This register bit is cleared when a valid pointer is found for three consecutive frames. PAIS does not cause LOP to be set. The SPE location CY7C955 is provided to the Receive ATM Cell Processor for cell extraction. The BIP−8 value calculated over the previous SPE is compared with the B3 byte of the current path overhead. Up to 65,535 errors can be detected per second. Errors are recorded in a 16-bit saturating counter that can be read through the controller interface. Path Far End Block Errors (PFEBE) are detected by examining the value in bits 1 through 4 of G1. This value (0−8h) is added to the count in a 16-bit saturating counter that can be read through the controller interface. Path Far End Receive Failures (PFERF) are detected by examining the value in bits 1 through 4 of G1. If this value is 9h for two consecutive frames, PFERF is set. This register bit is cleared when anything other than 9h appears for two consecutive frames. Path Remote Defect Indication (Path RDI) is detected by examining bit 5 of G1. If this value is 1h for 5 consecutive frames, PYEL is set. This register bit is cleared when a 0 appears in bit 5 for 5 consecutive frames. Receive ATM Cell Processor (RACP) The RACP block provides cell delineation, HEC checking and correcting, cell filtering for idle/unassigned cells, cell payload descrambling, status indications, and error monitoring. Cell delineation is performed by comparing the HEC sequence calculated over the first four bytes of the SPE to the fifth byte. If these values match, cell boundary has been determined. If not, the calculation advances one byte further into the payload (bytes 2−5) and the check is performed again. The HEC sequence is a CRC−8 calculated over the first 4 octets of the ATM cell header using the polynomial x8 + x2 + x + 1. The coset x6 + x4 + x2 + 1 is added (modulo 2) to the residue before comparison with the received sequence. This is the HUNT state of the cell delineation process. When a valid match has occurred the process enters the PRESYNC state. When 7 consecutive matches occur the process enters the SYNC state. If 6 consecutive incorrect HEC matches are detected the process moves back to the HUNT state. The average time for cell delineation is 93µs for STS−1 and 31µs for STS−3C. The HEC sequence is used not only to check for cell alignment, but also to insure that integrity of the ATM header. The HEC is used to correct single bit errors and to detect multiple bit errors. This feature can be disabled. The register file contains two saturating 8-bit counters for HEC errors; one for cells with single bit errors and another for multiple-bit errors. Cells with multiple bit errors are optionally discarded. Figure 3 shows the state diagram for HEC. The RACP optionally discards Idle/Unassigned cells. These cells contain a VPI/VCI address of 0h. Also, a Header Mask and Header Match register are provided to allow cells with a particular header characteristic in GFC, PTI and CLP to be filtered. The payload of valid cells are descrambled using the polynomial x43 +1. The cell headers are not descrambled since they 11 PRELIMINARY were not scrambled upon transmission. The descrambling feature can be disabled. CY7C955 ATM DELINEATION SYNC STATE Apparent Multi-Bit Error (Drop Cell) No Errors Detected Pass Cell CORRECTION MODE DETECTION MODE Errors Detected (Drop Cell) ALPHA consecutive HECs (From HUNT state) Single Bit Error (Correct Error and Pass Cell) No Errors Detected (Pass Cell) DELTA consecutive HECs (From PRESYNC state) Figure 3. HEC Verification State Diagram Receive Utopia Interface (RUI) The RUI provides a simple access from the external environment to the ATM Transceiver. The operation of this interface is compliant with the Utopia interface specification that is being standardized by the ATM Forum. The interface provides a 10 bit by 4 cell FIFO to decouple the system interface from the ATM physical layer timing. Ten bit words are clocked out from the device through a clocked FIFO style interface. These 10 bits include an 8-bit data word along with an parity bit (RXPRTY) and a Start Of Cell (SOC) indication. The interface also provides a cell available (RCA) indication and a read enable (RRDENB) control. RCA allows the FIFO to indicate empty and almost empty conditions and RRDENB allows the downstream circuit to pause the reading process in case the downstream cannot accept anymore read. If the Receive FIFO overflows, FIFO reset will occur and up to 4 cells may be lost because of the operation. Byte Rate Oscillator Receive Serial Data Carrier Detect Controller Interface Receive Parallel Data Packet Reassembly or ATM Switch Core Packet Segmentation or ATM Switch Core 7C955−5 Controller Interface (CI) The CI interface provides external access to the internal register file, device resetting and external input for the carrier detect signal. The ALOS input allows an external carrier detect from an optical module to cause an interrupt to the controller. The INTB and RALM pins can be configured to interrupt the external controller whenever any of several different error conditions occur. RALM signals the most important error conditions such as LOS, LOF, line AIS, path AIS, LCD, and LOP. INTB may indicate all possible errors depending on the state of the mask registers. INTB provides notification of the individual processing block that generated the error condition. The error register contained in each block will determine the exact cause of the interrupt. Fiber or Copper Media Interface Clock and Data Recovery and Receive Equalization Frequency Multiplication & Transmit Buffering Receive Start of Cell Receive Parity Read Strobe Fiber or Copper Media Interface Buffered Transmit Data SONET/SDH Overhead Processing ATM Cell Processing Transmit Parallel Data Transmit Start of Cell Transmit Parity Write Strobe CY7C955 ATM− SONET/SDH Transceiver (AX) Figure 4. SONET/SDH and ATM Interface 7C955−6 12 PRELIMINARY CY7C955 F6H A1 NOTE 1 F6H A1 00H F6H A1 00H 28H A2 00H E1 00H D2 0AH H2 00H K1 00H D5 00H D8 00H D11 00H Z2 28H A2 00H 28H A2 00H 01H C1 00H F1 00H D3 00H H3 00H K2 00H D6 00H D9 00H D12 00H E2 02H C1 00H 03H C1 00H B1 00H D1 62H H1 00H 00H 00H 00H 00H 00H 93H H1 93H H1 [NOTE 1] FFH H2 00H FFH H2 00H 00H H3 00H 00H H3 00H [NOTE 1] [NOTE 1] B2 00H D4 00H D7 00H D10 00H Z1 B2 00H B2 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Z1 00H Z1 00H Z2 [NOTE 1] 00H 00H 7C955−7 Z2 Note: 1. B1, B2, Z2, G1, H4, and B3 are variables. Figure 5. Default Values for the Transmitted Section and Line STS−3C/STM−1 Overhead 13 PRELIMINARY CY7C955 F6H A1 NOTE 1 F6H A2 00H E1 00H D2 0AH H2 00H K1 00H D5 00H D8 00H D11 NOTE 1 00H C1 00H F1 00H D3 00H H3 00H K2 00H D6 00H D9 00H D12 00H E2 7C955−8 B1 00H D1 62H H1 NOTE 1 B2 00H D4 00H D7 00H D10 00H Z1 Z2 Figure 6. Default Values for the Transmitted Section and Line STS−1 Overhead 14 PRELIMINARY CY7C955 00H J1 NOTE 1 B3 13H C2 NOTE 1 G1 00H F2 NOTE 1 H4 00 H Z3 00H Z4 00H Z5 7C955−9 Figure 7. Default Values for the Transmitted Path Overhead 15 PRELIMINARY Loopback Operation CY7C955 TDAT[7:0] TXPRTY TSOC TFCLK TWRENB TCA Transmit UTOPIA I/F Transmit FIFO 4 Cell by 8 bit D[7:0] A[7:0] ALE RDB WRB CSB INTB RSTB VCLK RALM Transmit ATM Cell Processor Transmit Path Overhead Processor Transmit Line Overhead Processor Transmit Section Overhead Processor TBYP RATE0 RATE1 TCP TGFC XOFF TCLK TFPO Controller Interface Configuration and Status Register File Error Monitoring Transmit Clock Multiplier & Transmit Buffer TXD± TXC± TRCLK± Rate Selection SONET/SDH Clock Recovery Receive UTOPIA I/F Receive FIFO 4 Cell by 8 bit TSEN RDAT[7:0] RXPRTY RSOC RFCLK RRDENB RCA Receive ATM Cell Processor Receive Path Overhead Processor Receive Line Overhead Processor Receive Section Overhead Processor ALOS± RRCLK± RXD± RXDO± RCP RGFC RCLK RFP RBYP High Speed Line Loopback 7C955−10 TDAT[7:0] TXPRTY TSOC TFCLK TWRENB TCA TCP TGFC XOFF Transmit UTOPIA I/F Transmit FIFO 4 Cell by 8 bit D[7:0] A[7:0] ALE RDB WRB CSB INTB RSTB VCLK RALM Transmit ATM Cell Processor Transmit Path Overhead Processor Transmit Line Overhead Processor TCLK TFPO Transmit Section Overhead Processor TBYP RATE0 RATE1 Controller Interface Configuration and Status Register File Error Monitoring Transmit Clock Multiplier & Transmit Buffer TXD± TXC± TRCLK± Rate Selection SONET/SDH Clock Recovery Receive UTOPIA I/F Receive FIFO 4 Cell by 8 bit TSEN RDAT[7:0] RXPRTY RSOC RFCLK RRDENB RCA Receive ATM Cell Processor Receive Path Overhead Processor Receive Line Overhead Processor Receive Section Overhead Processor ALOS± RRCLK± RXD± RXDO± RCP RGFC Diagnostic Loopback RCLK RFP RBYP 7C955−11 16 PRELIMINARY SONET Overhead Description Signal Values A1, A2 Description CY7C955 The frame alignment bytes mark the beginning of a SONET frame. They are transmitted every 125 µs in both OC−1 and OC3c speeds. Transmit Side: In OC−1, A1(F6H) and A2 (28H) are inserted into the transmitted stream at the beginning of every frame. These bytes are not scrambled by the frame synchronous SONET scrambler. Receive Side: The receiver will search for and frame onto the incoming A1, A2 bytes. This is the identification byte for the STS data stream. Transmit Side: In OC−1, C1 is transmitted as OH. In OC −3c, the sequence C1, C1, C1 of every frame is transmitted as 01H, 02H, 03H. These bytes are not scrambled by the frame-synchronous SONET scrambler. Receive side: The receiver will ignore C1. This is the section bit interleave parity byte. Transmit Side: B1 is calculated using the BIP −8 algorithm described in I.432. It is inserted into the SONET data stream before the frame synchronous SONET scrambler. Receive Side: Received B1 error events are accumulated in the SBE [15:0] (Reg−12H and Reg−13H). These are the pointer value byte. These bytes are used to locate the beginning of the Synchronous Payload Envelope (SPE) in the SONET/SDH frame. Transmit side: H1, H2 contains the normal new data flag (0110) together with 522 (decimal) as the fixed pointer value field. The concatenation indication byte is also inserted (H1* = 93, H2* = FF). Receive Side: H1 and H2 are used to locate the beginning of the SPE. If a valid pointer cannot be found, CY7C955 will indicate a Loss of Pointer State. Path AIS is detected by an all-ones pattern in H1 and H2 bytes. This is the pointer action byte. Transmit Side: H3 will be all zeroes. Receive Side: Synchronous Payload Data will be stuffed in the H3 byte if a negative stuff event occurs. This byte is ignored otherwise. This is the line bit interleaved parity bytes, it is used to monitor line errors. Transmit Side: B2 is calculated over all bits of the line overhead and the SPE capacity of the previous frame before the frame is being scrambled. The B2 byte itself is then placed in the current frame before scramble. This is the identity line layer maintenance signal. Transmit Side: Bits 6, 7, and 8 of this byte are ‘110’ before scrambling when Line Remote Defect Indication is true. The whole of K2 is an all-one pattern before scrambling if Line AIS is inserted. Receive Side: Bits 6, 7, and 8 of the K2 byte are being examined to determine the presence of AIS, and RDI signals. Access to APs registers will be available in future revisions. This is the growth byte. It is used to provide far end block error function useful for remote performance monitoring. Transmit Side: The number of B2 errors detected in the last frame is inserted. Z2 is a number from 0−24 indicating 0−24 errors. Receive Side: A legal (0−24) Z2 number will be added to the line FEBE counter. This is the interleaved parity byte. Transmit Side: B3 is calculated over all bits of the SPE of the previous frame before scrambling and is placed in the current frame before scrambling. This provides path error monitoring capability for the link. Receive Side: The value in B3 is accumulated in a register. This is the path signal label byte for indicating the contents of the SONET payload. Transmit Side: It’s fixed value is 13H. This indicates the payload is ATM. Receive Side: The receive side expects C2 to be 13H. If the data is not 13H for 3 consecutive frames, an interrupt (if enabled) will be generated. This is the path status byte. Transmit Side: Path remote defect Indication (Path RDI) together with the number of B3 errors in the last frame are inserted into G1 before scrambling for transmission. G1 is a number from 0−8, indicating 0−8 errors. Receive side: A legal G1 value (0−8) will be accumulated in the FEBE counter. Path remote defect indication is also detected through this byte. This is the cell offset byte. Transmit Side: This byte indicates the offset in bytes between the H4 byte and the first cell byte after H4. Receive Side: H4 byte is ignored. C1 B1 H1, H2 H3 B2 K2 Z2 B3 C2 G1 H4 17 PRELIMINARY CY7C955 Register Map Address Reg−00H Reg−01H Reg−02H Reg−04H Reg−05H Reg−06H Reg−07H Reg−10H Reg−11H Reg−12H Reg−13H Reg−14H Reg−15H Reg−18H Reg−19H Reg−1AH Reg−1BH Reg−1CH Reg−1DH Reg−1EH Reg−1FH Reg−20H Reg−21H Reg−30H Reg−31H Reg−33H Reg−37H Reg−38H Reg−39H Reg−3AH Reg−3BH Reg−3CH Reg−40H Reg−41H Reg−45H Reg−46H Reg−48H Reg−49H Reg−50H Reg−51H Reg−52H Reg−53H Reg−54H Master Reset/Type/Identify Register Master Configuration Register Master Interrupt Register Master Clock Monitor Register Master Control Register Transmit Clock Synthesis Control Register Receive Clock Synthesis Control Register Receive Section Overhead Processor Control Register Receive Section Overhead Processor Status Register LSB of the Receive Section Overhead Processor Status BIP-8 Counter MSB of the Receive Section Overhead Processor Status BIP-8 Counter Transmit Section Overhead Processor Control Register Transmit Section Overhead Processor Control Error Insertion Register Receive Line Overhead Processor Control and Status Register Receive Line Overhead Processor Interrupt Enable and Status Register Line BIP−8/24 Register Line BIP−8/24 Register Line BIP−8/24 Register Line Far-End Block Error Register Line Far-End Block Error Register Line Far-End Block Error Register Transmit Line Overhead Processor Register Transmit Line Overhead Processor Error Insertion Register Receive Path Overhead Processor Interrupt Register Receive Path Overhead Processor Register Receive Path Overhead Processor Interrupt Enable Register Receive Path Signal Label Register Path BIP−8 (B3) Register Path BIP−8 (B3) Register Path Far-End Block Error Register Path Far-End Block Error Register Path Far-End Block Error Register Transmit Path Overhead Processor Error Insertion Register Transmit Path Overhead Processor Pointer Control Register Transmit Path Overhead Processor Arbitrary Payload Pointer Register Transmit Path Overhead Processor Arbitrary Payload Pointer Register Transmit Path Overhead Processor Path Signal Label Register Transmit Path Overhead Processor Arbitrary Path Status Register Receive ATM Cell Processor Control and Status Register Receive ATM Cell Processor Interrupt Register Receive ATM Cell Processor Match Header Pattern Register Receive ATM Cell Processor Match Header Mask Register Receive ATM Cell Processor Correctable HCS Error Count Register Register CY7C955 18 PRELIMINARY CY7C955 Register Map (continued) Address Reg−55H Reg−56H Reg−57H Reg−58H Reg−59H Reg−60H Reg−61H Reg−62H Reg−63H Reg−64H Reg−65H Reg−66H Reg−67H Reg−80H Register Receive ATM Cell Processor Uncorrectable HCS Error Count Register Receive ATM Cell Processor Receive Cell Counter Register Receive ATM Cell Processor Receive Cell Counter Register Receive ATM Cell Processor Receive Cell Counter Register Receive ATM Cell Processor Receive Configuration Register Transmit ATM Cell Processor Control and Status Register Transmit ATM Cell Processor Unassigned Cell Header Register Transmit ATM Cell Processor Unassigned Cell Payload Register Transmit ATM Cell Processor FIFO Control Register Transmit ATM Cell Processor Transmit Cell Counter Register Transmit ATM Cell Processor Transmit Cell Counter Register Transmit ATM Cell Processor Transmit Cell Counter Register Transmit ATM Cell Processor Transmit Configuration Register CY7C955 Test Control Register CY7C955 REG−00H BIT POSITION 7 6 5 4 3 2 1 0 Master Reset / Type / Identity Register NAME RESET TYPE[2] TYPE[1] TYPE[0] ID[3] ID[2] ID[1] ID[0] READ/WRITE R/W R R R R R R R 0 0 1 1 1 1 1 1 DEFAULT RESET This is the master reset bit. Toggling this register has the same effect as toggling the RSTB pin, except that RSTB will reset all registers to their default values, while writing a 1 to this register will only reset all other registers (but not itself) to their default values. Leaving a 1 in this register puts the AX in power-down mode. 0: 1: Normal mode. Reset / Power Down Mode. TYPE[2:0] These bits differentiate the AX with other Cypress products. ID[3:0] These bits show the revision number of the CY7C955. 19 PRELIMINARY REG − 01H BIT POSITION 7 6 5 4 3 2 1 0 AUTOFEBE Unused AUTOFEBE AUTOLRDI AUTOPRDI TCAINV RCAINV RXDINV Unused R/W R/W R/W R/W R/W R/W 1 1 1 0 0 0 Master Configuration Register NAME READ/WRITE CY7C955 DEFAULT This bit controls whether Far End Block Error (FEBE) is transmitted when line or path BIP error is being detected on the receive data stream. 0: 1: Do not generate line or path FEBE error in response to incoming line or path BIP error. Generate line or path FEBE error in response to incoming line or path BIP error. AUTOLRDI This bit controls whether Line Remote Defect Indication (LRDI) is transmitted when an incoming alarm is being detected. 0: 1: Do not insert line RDI when line AIS, Loss of Frame (LOF) or Loss of Signal (LOS) is being detected. Insert line RDI when line AIS, Loss of Frame (LOF) or Loss of Signal (LOS) is being detected. AUTOPRDI This bit controls whether STS Path Remote Defect Indication (PRDI) is transmitted when an incoming alarm is being detected. 0: 1: Do not insert STS path RDI when Loss of Signal (LOS), Loss of Pointer (LOP), STS path AIS, Loss of Frame (LOF), line AIS, or Loss of Cell Delineation (LCD) is being detected. Insert STS path RDI when Loss of Signal (LOS), Loss of Pointer (LOP), STS path AIS, Loss of Frame (LOF), line AIS, or Loss of Cell Delineation (LCD) is being detected. TCAINV This bit controls the polarity of TCA. 0: 1: TCA is active HIGH. TCA is active LOW. RCAINV This bit controls the polarity of RCA. 0: 1: RCA is active HIGH. RCA is active LOW. RXDINV This bit controls the interpretation of the differential pair RXD. 0: 1: Logical 1 is represented by RXD+ HIGH and RXD− LOW. Logical 0 is represented by RXD+ HIGH and RXD− LOW. 20 PRELIMINARY REG − 02H BIT POSITION 7 6 5 4 3 2 1 0 TROOLI This is the Transmit Reference Out Of Lock Interrupt. This bit resets when Reg−02H is being read. 1: 0: LCDI TROOLV (Reg−06H, bit 3) has changed state since Reg−02H was last read. TROOLV (Reg−06H, bit 3) has not changed state since Reg−02H was last read. TROOLI LCDI RDOOLI TACPI RACPI RPOPI RLOPI RSOPI Master Interrupt Register NAME READ/WRITE R R R R R R R R CY7C955 DEFAULT This is the Loss of Cell Delineation Interrupt. It has to be enabled by bit 7 of Reg−05H. This bit resets when Reg−02H is being read. 1: 0: Loss of cell delineation is entered or exited since Reg−02H was last read. There is no change in the loss of cell delineation state. RDOOLI This is the Receive Data Out Of Lock Interrupt. This bit resets when Reg−02H is being read. 1: 0: TACPI This is the Transmit ATM Cell Processor Interrupt. This bit resets when Reg−02H is being read. This register is a logical OR of all the Transmit ATM Cell Processor (TACP) interrupts Reg−60H and 63H. 1: 0: FOVRI, TSOCI, or TXPRTYI is HIGH. FOVRI, TSOCI, and TXPRTYI are all LOW. RDOOLV (Reg−07H, bit 3) has changed state since Reg−02H was last read. RDOOLV (Reg−07H, bit 3) has not changed state since Reg−02H was last read. RACPI This is the Receive ATM Cell Processor Interrupt. This bit resets when Reg−02H is being read. This register is a logical OR of all the Receive ATM Cell Processor (RACP) interrupts of Reg−51H. 1: 0: OOCDI, CHCSI, or UHCSI is HIGH. OOCDI, CHCSI, and UHCSI are all LOW. RPOPI This is the Receive Path Overhead Processor Interrupt. This bit resets when Reg−02H is being read. This register is a logical OR of all the Receive Path Overhead Processor (RPOP) interrupts of Reg−31H. 1: 0: PSLI, LOPI, PAISI, PRDII, BIPEI, or FEBEI is HIGH. PSLI, LOPI, PAISI, PRDII, BIPEI, and FEBEI are all LOW. RLOPI This is the Receive Line Overhead Processor Interrupt. This bit resets when Reg−02H is being read. This register is a logical OR of all the Receive Line Overhead Processor (RLOP) interrupts of Reg−19H. 1: 0: FEBEI, BIPEI, LAISI, or RDII is HIGH. FEBEI, BIPEI, LAISI, and RDII are all LOW. RSOPI This is the Receive Section Overhead Processor Interrupt. This bit resets when Reg−02H is being read. This register is a logical OR or all the Receive Section Overhead Processor (RSOP) interrupts or Reg−11H. 1: 0: BIPEI, LOSI, LOFI, or OOFI is HIGH. BIPEI, LOSI, LOFI, and OOFI are all LOW. 21 PRELIMINARY REG − 04H BIT POSITION 7 6 5 4 3 2 1 0 RXDOD RXDOD XORTXC Unused Unused RRCLKA TRCLKA RCLKA TCLKA R R R R Master Clock Monitor Register NAME READ/WRITE R/W R/W 0 0 CY7C955 DEFAULT This bit is used to turn off the RXDO output in case it is not needed. This helps save power and reduce power supply noise. 1: 0: 1: 0: RXDO output is disabled. RXDO is the retimed buffered output of RXDXORTXC. TXC is disabled if RATE0 is LOW, and TXC is a 155.52-MHz clock if RATE0 is HIGH. TXC is a 51.84-MHz clock if RATE0 is LOW, and TXC is disabled if RATE0 is HIGH. XORTXC is used to invert the default-on status of the TXC output. RRCLKA This bit can be read to check for RRCLK transitions; when HIGH, this bit stays HIGH until Reg−04H is being read. 1: 0: RRCLK+ has a LOW to HIGH transition since this register was last read. RRCLK+ has no LOW to HIGH transitions since this register was last read. TRCLKA This bit can be read to check for TRCLK transitions; when HIGH, this bit stays HIGH until Reg−04H is being read. 1: 0: TRCLK+ has a LOW to HIGH transition since this register was last read. TRCLK+ has no LOW to HIGH transitions since this register was last read. RCLKA This bit can be read to check for RCLK transitions; when HIGH, this bit stays HIGH until Reg−04H is being read. 1: 0: RCLK has a LOW to HIGH transition since this register was last read. RCLK has no LOW to HIGH transitions since this register was last read. TCLKA This bit can be read to check for TCLK transitions; when HIGH, this bit stays HIGH until Reg−04H is being read. 1: 0: TRCLK+ has a LOW to HIGH transition since this register was last read. TRCLK+ has no LOW to HIGH transitions since this register was last read. 22 PRELIMINARY REG − 05H BIT POSITION 7 6 5 4 3 2 1 0 LCDE This bit enables a change in the Loss of Cell Delineation state to generate an interrupt on pin INTB. 0: 1: LCDV This bit shows the present loss of cell delineation state of the Receive ATM Cell overhead Processor (RACP). 0: 1: RACP is in SYNC state for longer than 4 ms. INTB will not be affected by a transition in LCDV (Reg−05H, bit 6). INTB will go LOW when there is a transition in LCDV (Reg−05H, bit 6). LCDE LCDV FIXPTR Unused Unused LLE DLE LOOPT R/W R/W R/W 0 0 0 Master Control Register NAME READ/WRITE R/W R R/W 1 0 CY7C955 DEFAULT RACP is out of cell delineation for more than 4 ms and there are no detected LOS, LOP, Path AIS, and Line AIS. FIXPTR This bit controls the operation of the transmit payload pointer adjustment function. 0: 1: LLE This bit controls the line loop-back path of the CY7C955; DLE and LLE cannot be both set to 1. 0: 1: DLE This bit controls the diagnostic loop-back path of the CY7C955; DLE and LLE cannot be both set to 1. 0: 1: Normal operation. The transmitted data steam is being looped back to the received data stream. Normal operation. RXD+ and RXD− are connected to TXD+ and TXD − internally. The setting in Reg−41H can control the payload pointer adjustment operations. The transmit payload pointer is fixed at 522. LOOPT This bit enables loop timing. 0: 1: The transmitted data stream derives its clock from TRCLK. The clock to use depends on the setting of TREFSEL (Reg−06H, bit 0) and on the level of pins TBYP and RATE0. The transmitted data stream derives its clock from RRCLK if the clock and data recovery function of the receiver is not active and from RXD if the clock and data recovery function is active. Again, the clock to use in RRCLK depends on the setting of RREFSEL (Reg−07H), RBYP, and RATE0. 23 PRELIMINARY REG − 06H BIT POSITION 7 6 5 4 3 2 1 0 TROOLV This bit is the Transmit Reference Out Of Lock Status register. 0: 1: Unused Unused Unused Unused TROOLV Unused TROOLE TREFSEL R/W R/W 0 0 R Transmit Clock Synthesis Control Register NAME READ/WRITE CY7C955 DEFAULT The divided-down synthesized transmit clock is within 2930 ppm of TRCLK or RRCLK (in loop timing mode). The divided-down synthesized transmit clock is not within 2930 ppm of TRCLK or RRCLK (in loop timing mode). TROOLE This bit is the Transmit Reference Out Of Lock Interrupt Enable register. 0: 1: INTB, the interrupt pin, will not be affected by transmit out of lock. INTB, the interrupt pin, will pull LOW when there is a state change of TROOLV. TREFSEL This bit is the Transmit Reference Select. This bit is ignored in transmit bypass mode (TBYP = 1). 0: TRCLK expects a 19.44-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM −1), the transmit PLL will multiply the TRCLK frequency by 8 times. If RATE0 is LOW (51.84 Mbps, STS−1), the transmit PLL will multiply the TRCLK frequency by 8/3 times to clock the transmitter. TRCLK expects a 6.48-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM−1), the transmit PLL will multiply the TRCLK frequency by 24 times. If RATE0 is LOW (51.84 Mbps, STS−1), the transmit PLL will multiply the TRCLK frequency by 8 times to clock the transmitter. 1: 24 PRELIMINARY REG − 07H BIT POSITION 7 6 5 4 3 2 1 0 RROOLV This bit is the Receive Reference Out Of Lock Status register. 0: 1: Unused Unused Unused Unused RROOLV Unused RROOLE RREFSEL R/W R/W 0 0 R Receive Clock Synthesis Control Register NAME READ/WRITE CY7C955 DEFAULT The divided-down recovered clock is within 2930 ppm of RRCLK, and there is at least one transition on RXD during the last 80 bit-periods. The divided-down recovered clock is not within 2930 ppm of RRCLK, or there are no transitions on RXD within the last 80 bit-periods. RROOLE This bit is the Receive Reference Out Of Lock Interrupt Enable register. 0: 1: INTB, the interrupt pin, will not be affected by receiver out of lock. INTB, the interrupt pin, will go LOW when there is a state change of RROOLV. RREFSEL This bit is the Receiver Reference Select. This bit is ignored in receiver bypass mode (RBYP = 1). 0: RRCLK expects a 19.44-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM −1), the recovered clock is divided down 8 times before comparing with RRCLK. If RATE0 is LOW (51.84 Mbps, STS−1), the recovered clock is divided down 3/8 times before comparing with RRCLK. RRCLK expects a 6.480-MHz reference clock. If RATE0 is HIGH (155.52 Mbps, STS−3c/STM −1), the recovered clock is divided down 24 times before comparing with RRCLK. If RATE0 is LOW (51.84 Mbps, STS−1), the recovered clock is divided down 8 times before comparing with RRCLK. 1: 25 PRELIMINARY REG − 10H BIT POSITION 7 6 5 4 3 2 1 0 DDS This bit controls whether SONET descrambling is done on the receive data stream. 0: 1: FOOF This bit can be used to manually put the Receive Section Overhead Processor out of frame. 0: 1: No action. The Receive Section Overhead Processor will detect an out of frame alarm at the next frame boundary. Descrambling is performed. Descrambling is not performed. Unused DDS FOOF Unused BIPEE LOSE LOFE OOFE R/W R/W R/W R/W 0 0 0 0 R/W W 0 0 CY7C955 Receive Section Overhead Processor Control Register NAME READ/WRITE DEFAULT BIPEE This bit controls whether a section BIP−8 error (B1) generates an interrupt. 0: 1: LOSE This bit controls whether a Loss of Signal alarm generates an interrupt. 0: 1: LOFE This bit controls whether a Loss of Frame alarm generates an interrupt. 0: 1: OOFE This bit controls whether an Out of Frame alarm generates an interrupt. 0: 1: The interrupt pin, INTB, is not affected by the out of frame alarm. The interrupt pin, INTB, will go LOW upon receiving an out of frame alarm. The interrupt pin, INTB, is not affected by the loss of frame alarm. The interrupt pin, INTB, will go LOW upon receiving a loss of frame alarm. The interrupt pin, INTB, is not affected by the loss of signal alarm. The interrupt pin, INTB, will go LOW upon receiving a loss of signal alarm. The interrupt pin, INTB, is not affected by section BIP−8 errors. The interrupt pin, INTB, will go LOW upon receiving a section BIP−8 error. 26 PRELIMINARY REG − 11H BIT POSITION 7 6 5 4 3 2 1 0 BIPEI This is the section BIP−8 interrupt bit. This bit resets when Reg−11H is being read. 0: 1: LOSI This is the Loss of Signal (LOS) interrupt bit. This bit resets when Reg−11H is being read. 0: 1: LOFI This is the Loss of Frame (LOF) interrupt bit. This bit resets when Reg−11H is being read. 0: 1: OOFI This is the Out of Frame (OOF) interrupt bit. This bit resets when Reg−11H is being read. 0: 1: LOSV This bit shows the Loss of Signal (LOS) status of the CY7C955. 0: 1: LOFV This bit shows the Loss of Frame (LOF) status of the CY7C955. 0: 1: OOFV This bit shows the Out of Frame (OOF) status of the CY7C955. 0: 1: The Receive Section Overhead Processor is in frame. The Receive Section Overhead Processor is in an out of frame state. The Receive Section Overhead Processor is not in a Loss of Frame state. The Receive Section Overhead Processor is not in a loss of signal state. The Receive Section Overhead Processor is in a loss of signal state. No change in the OOF status. There is a change in the OOF status since Reg −11H was last read. No change in the LOF status. There is a change in the LOF status since Reg−11H was last read. No change in the LOS status. There is a change in the LOS status since Reg−11H was last read. No section BIP −8 error is detected since Reg−11H was last read. Section BIP −8 error is detected since Reg−11H was last read. Unused BIPEI LOSI LOFI OOFI LOSV LOFV OOFV R R R R R R R CY7C955 Receive Section Overhead Processor Status Register NAME READ/WRITE DEFAULT The Receive Section Overhead Processor is in a Loss of Frame state. LOF is declared when OOF has lasted for more than 3 ms. LOFV stays HIGH until the Receive Section Overhead Processor is in frame for more than 3 ms. 27 PRELIMINARY REG − 12H BIT POSITION 7 6 5 4 3 2 1 0 SBE[15:0] SBE[7] SBE[6] SBE[5] SBE[4] SBE[3] SBE[2] SBE[1] SBE[0] LSB of the Receive Section Overhead Processor Status BIP−8 counter NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 CY7C955 DEFAULT Reg−12H and Reg−13H will load the number of BIP−8 errors from an internal counter approximately 1 µs after a write operation is done to Reg−12H, Reg−13H, or Reg−00H. At that time (1 µs after the write operation), these two registers are updated and the internal BIP−8 error counter is reset to zero to begin another round of error accumulation. Reading Reg−12H and Reg−13H after the write yields the number of BIP−8 (B1) errors accumulated since the counter was last written to, if overflow has not occurred. REG − 13H BIT POSITION 7 6 5 4 3 2 1 0 SBE[15:0] Reg−12H and Reg−13H will load the number of BIP−8 errors from an internal counter approximately 1 µs after a write operation is done to Reg−12H, Reg−13H, or Reg−00H. At that time (1 µs after the write operation), these two registers are updated and the internal BIP−8 error counter is reset to zero to begin another round of error accumulation. Reading Reg−12H and Reg−13H after the write yields the number of BIP−8 (B1) errors accumulated since the counter was last written to if overflow has not occurred. SBE[15] SBE[14] SBE[13] SBE[12] SBE[11] SBE[10] SBE[9] SBE[8] MSB of the Receive Section Overhead Processor Status BIP−8 counter NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT 28 PRELIMINARY REG − 14H BIT POSITION 7 6 5 4 3 2 1 0 DS This bit controls whether SONET scrambling is done to the transmit data stream. 0: 1: LAIS This bit controls whether line Alarm Indication Signal (AIS) is being inserted into the transmit data stream. 1: 0: Scrambling is performed. Scrambling is not performed. Unused DS Unused Unused Unused Unused Unused LAIS R/W 0 R/W 0 CY7C955 Transmit Section Overhead Processor Control Register NAME READ/WRITE DEFAULT All bits in the SONET frame (excluding the section overhead) are converted to a 1 prior to SONET scrambling. This operation begins immediately at the next frame boundary. No line AIS is transmitted. REG − 15H BIT POSITION 7 6 5 4 3 2 1 0 DLOS Transmit Section Overhead Processor Error Insertion Register NAME Unused Unused Unused Unused Unused DLOS DBIP8 DFP R/W R/W R/W 0 0 0 READ/WRITE DEFAULT This bit generates a continuous loss of signal error in the transmit data stream. 0: 1: Normal operation. TXD transmits all zeros. DBIP8 This bit generates a continuous section BIP−8 (B1) error in the transmit data stream. 0: 1: DFP This bit generates a framing byte error in the transmit data stream. 0: 1: Normal operation. The most significant bit of the section overhead framing byte is converted from 1 to 0. In other words, F6H becomes H in the first A1 byte of the section overhead. Normal operation. B1 byte is inverted. 29 PRELIMINARY REG − 18H BIT POSITION 7 6 5 4 3 2 1 0 BIPWORD This bit controls how many times a B2 error is recorded. 0: 1: The B2 error counter increments only once per frame on receiving B2 bit-errors. BIPWORD Unused Unused Unused Unused Unused LAISV RDIV R R 0 0 CY7C955 Receive LIne Overhead Processor Control and Status Register NAME READ/WRITE R/W 0 DEFAULT The B2 error counter increments once for every bit error represented in the B2 word. Note that in STS−3c, there could be at most 24 B2 bit-errors per frame, and in STS−1, there could be, at most, 8 B2 bit-errors per frame. LAISV This bit is the Line Alarm Indication Signal (LAIS) status register. 0: 1: RDIV This bit is the Remote Defect Indication status register. 0: 1: No remote defect indication (RDI) detected. Remote defect indication (RDI) has been detected. No Line AIS detected. Line AIS has been detected. Line AIS is triggered by LOS or LOF. 30 PRELIMINARY REG − 19H BIT POSITION 7 6 5 4 3 2 1 0 FEBEE This bit controls whether line far end block error generates an interrupt by asserting INTB LOW. 0: 1: Line far-end block error will not generate an interrupt. Line far-end block error will generate an interrupt. FEBEE BIPEE LAISE RDIE FEBEI BIPEI LAISI RDII CY7C955 Receive Line Overhead Processor Interrupt Enable and Status Register NAME READ/WRITE R/W R/W R/W R/W R R R R 0 0 0 0 DEFAULT BIPEE This bit controls whether BIP−24 (B2) error generates an interrupt by asserting INTB LOW. 0: 1: BIP−24 error will not generate an interrupt. BIP−24 error will generate an interrupt. LAISE This bit controls whether line alarm indication signal (LAIS) error generates an interrupt by asserting INTB LOW. 0: 1: RDIE This bit controls whether a remote defect indication alarm detection generates an interrupt by asserting INTB LOW. 0: 1: A change in the RDIV state (Reg−18H, bit 0) will not generate an interrupt. A change in the RDIV state (Reg−18H, bit 0) will generate an interrupt. LAIS error will not generate an interrupt. LAIS error will generate an interrupt. FEBEI This is the line far-end block error interrupt bit. This bit resets when Reg−19H is being read. 0: 1: BIPEI This is the section BIP−24 (B2) interrupt bit. This bit resets when Reg−19H is being read. 0: 1: LAISI This is the Line Alarm Indication Signal (LAIS) interrupt bit. This bit resets when Reg−19H is being read. 0: 1: RDII This is the Remote Defect Indication (RDI) interrupt bit. This bit resets when Reg−19H is being read. 0: 1: No line remote defect indication has been detected since Reg−19H was last read. Line remote defect indication has been detected since Reg−19H was last read. No LAIS has been detected since Reg−19H was last read. LAIS has been detected since Reg−19H was last read. No line BIP−24 (B2) error has been detected since Reg−19H was last read. Line BIP −24 (B2) error has been detected since Reg−19H was last read. No line far-end block error has been detected since Reg−19H was last read. Line far-end block error has been detected since Reg−19H was last read. 31 PRELIMINARY REG − 1AH BIT POSITION 7 6 5 4 3 2 1 0 LBE[19:0] LBE[7] LBE[6] LBE[5] LBE[4] LBE[3] LBE[2] LBE[1] LBE[0] Line BIP−8/24 Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 CY7C955 DEFAULT Reg−1AH to Reg−1CH will be loaded with the number of BIP −8/24 (B2) errors from an internal counter approximately 1 µs after a write operation is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal BIP−8/24 error counter reset to zero to begin another round of error accumulation. Reading Reg−1AH, Reg−1BH, and Reg−1CH after the write yields the number of BIP−8/24 (B2) errors accumulated since the counter was last reset, if overflow has not occurred. REG − 1BH BIT POSITION 7 6 5 4 3 2 1 0 LBE[19:0] Reg−1AH to Reg−1CH will be loaded with the number of BIP −8/24 (B2) errors from an internal counter approximately 1 µs after a write operation is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal BIP−8/24 error counter is reset to zero to begin another round of error accumulation. Reading Reg−1AH, Reg−1BH, and Reg−1CH after the write yields the number of BIP−8/24 (B2) errors accumulated since the counter was last reset, if overflow has not occurred. LBE[15] LBE[14] LBE[13] LBE[12] LBE[11] LBE[10] LBE[9] LBE[8] Line BIP−8/24 Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT 32 PRELIMINARY REG − 1CH BIT POSITION 7 6 5 4 3 2 1 0 LBE[19:0] Unused Unused Unused Unused LBE[19] LBE[18] LBE[17] LBE[16] R R R R 0 0 0 0 Line BIP−8/24 Register NAME READ/WRITE CY7C955 DEFAULT Reg−1AH to Reg−1CH will be loaded with the number of BIP −8/24 (B2) errors from an internal counter approximately 1 µs after a write operation is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal BIP−8/24 error counter is reset to zero to begin another round of error accumulation. Reading Reg−1AH, Reg−1BH, and Reg−1CH after the write yields the number of BIP−8/24 (B2) errors accumulated since the counter was last reset, if overflow has not occurred. REG − 1DH BIT POSITION 7 6 5 4 3 2 1 0 LFE[19:0] Reg−1DH, Reg−1EH, and Reg−1FH will be loaded with the number of line FEBE (Z2) errors from an internal counter approximately 1 µs after a write operation is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal line FEBE error counter is reset to zero to begin another round of error accumulation. Reading Reg−1DH, Reg−1EH, and Reg−1FH after the write yields the number of line FEBE (Z2) errors accumulated since the counter was last reset, if overflow has not occurred. LFE[7] LFE[6] LFE[5] LFE[4] LFE[3] LFE[2] LFE[1] LFE[0] Line Far End Block Error Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT 33 PRELIMINARY REG − 1EH BIT POSITION 7 6 5 4 3 2 1 0 LFE[19:0] LFE[15] LFE[14] LFE[13] LFE[12] LFE[11] LFE[10] LFE[9] LFE[8] CY7C955 Line Far End Block Error Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT Reg−1DH, Reg−1EH, and Reg−1FH will be loaded with the number of line FEBE (Z2) errors from an internal counter approximately 1 µs after a write operation is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal line FEBE error counter are reset to zero to begin another round of error accumulation. Reading Reg−1DH, Reg−1EH, and Reg−1FH after the write yields the number of line FEBE (Z2) errors accumulated since the counter was last reset, if overflow has not occurred. REG − 1FH BIT POSITION 7 6 5 4 3 2 1 0 LFE[19:0] Reg−1DH, Reg−1EH, and Reg−1FH will be loaded with the number of line FEBE (Z2) errors from an internal counter approximately 1 µs after a write operation is done to Reg−1AH, Reg−1BH, Reg−1CH, Reg−1DH, Reg−1EH, Reg−1FH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal line FEBE error counter are reset to zero to begin another round of error accumulation. Reading Reg−1DH, Reg−1EH, and Reg−1FH after the write yields the number of line FEBE (Z2) errors accumulated since the counter was last reset, if overflow has not occurred. Unused Unused Unused Unused LFE[19] LFE[18] LFE[17] LFE[16] Line Far End Block Error Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT 34 PRELIMINARY REG − 20H BIT POSITION 7 6 5 4 3 2 1 0 RDI This bit controls whether line far end receive failure (RDI) is being inserted into the transmit data stream. 0: 1: Transmit 000 in bits 6, 7, and 8 of K2. Transmit 110 in bits 6, 7, and 8 of K2. Unused Unused Unused Unused Unused Unused Unused RDI R/W 0 CY7C955 Transmit Line Overhead Processor Register NAME READ/WRITE DEFAULT REG − 21H BIT POSITION 7 6 5 4 3 2 1 0 DBIP Transmit Line Overhead Processor Error Insertion Register NAME Unused Unused Unused Unused Unused Unused Unused DBIP R/W 0 READ/WRITE DEFAULT This bit generates a continuous line BIP−8/24 (B2) error in the transmit data stream. 0: 1: Normal operation. Insert BIP8/24 (B2) error by inverting the B2 byte. 35 PRELIMINARY REG − 30H BIT POSITION 7 6 5 4 3 2 1 0 LOP This bit is the Loss of Pointer (LOP) alarm register. 0: 1: PAIS This bit is the path Alarm Indication Signal (AIS) register. 0: 1: PRDI This bit is the path Far-End Receive Failure (RDI) alarm register. 0: 1: No path far-end receive failure (RDI) alarm detected. Path far-end receive failure (RDI) alarm detected. No path alarm indication signal detected. Path alarm indication signal detected. No loss of pointer alarm detected. Loss of pointer alarm detected. Unused Unused LOP Unused PAIS PRDI Unused Unused R R R CY7C955 Receive Path Overhead Processor Interrupt Register NAME READ/WRITE DEFAULT 36 PRELIMINARY REG − 31H BIT POSITION 7 6 5 4 3 2 1 0 PSLI This is the Path Signal Label (PSL) register interrupt bit. This bit resets when Reg−31H is being read. 0: 1: LOPI This is the Loss of Pointer (LOP) interrupt bit. This bit resets when Reg−31H is being read. 0: 1: PAISI This is the path Alarm Indication Signal (AIS) interrupt bit. This bit resets when Reg−31H is being read. 0: 1: PRDII This is the path Far-End Receive Failure (RDI) alarm interrupt bit. This bit resets when Reg−31H is being read. 0: 1: BIPEI This is the BIP−8 (B3) error interrupt bit. This bit resets when Reg−31H is being read. 0: 1: No BIP −8 (B3) error detected since Reg−31H was last read. BIP−8 (B3) error has been detected since Reg−31H was last read. No change in the path far-end receive failure alarm since Reg−31H was last read. There is a change in the path far-end receive failure alarm since Reg−31H was last read. No change in the path alarm indication signal since Reg−31H was last read. There is a change in the path alarm indication signal since Reg−31H was last read. No change in the loss of pointer state since Reg−31H was last read. There is a change in the loss of pointer state since Reg−31H was last read. No change in the path signal label since Reg−31H was last read. There is a change in the path signal label since Reg−31H was last read. PSLI Unused LOPI Unused PAISI PRDII BIPEI FEBEI R R R R R CY7C955 Receive Path Overhead Processor Register NAME READ/WRITE R DEFAULT FEBEI This is the path Far-End Block Error (FEBE) interrupt bit. This bit resets when Reg−31H is being read. 0: 1: No path far-end block error detected since Reg−31H was last read. Path far-end block error has been detected since Reg−31H was last read. 37 PRELIMINARY REG − 33H BIT POSITION 7 6 5 4 3 2 1 0 PSLE PSLE Unused LOPE Unused PAISE PRDIE BIPEE FEBEE R/W R/W R/W R/W 0 0 0 0 R/W 0 CY7C955 Receive Path Overhead Processor Interrupt Enable Register NAME READ/WRITE R/W 0 DEFAULT This bit controls whether a change in the Path Signal Label (PSL) generates an interrupt by asserting INTB LOW. 0: 1: LOPE This bit controls whether a loss of pointer generates an interrupt by asserting INTB LOW. 0: 1: A change in the loss of pointer state will not generate an interrupt. A change in the loss of pointer state will generate an interrupt. A change in the path signal label (PSL) will not generate an interrupt. An interrupt will be generated if more than two consecutive non-13H C3 bytes are being detected in the path overhead. PAISE This bit controls whether Path Alarm Indication Signal (PAIS) error generates an interrupt by asserting INTB LOW. 0: 1: PAIS error will not generate an interrupt. PAIS error will generate an interrupt. PRDIE This bit controls whether a path Remote Defect Indication (RDI) generates an interrupt by asserting INTB LOW. 0: 1: A change in the path remote defect indication state will not generate an interrupt. A change in the path remote defect indication state will generate an interrupt. BIPEE This bit controls whether BIP−8 (B3) error generates an interrupt by asserting INTB LOW. 0: 1: BIP−8 (B3) error will not generate an interrupt. BIP−8 (B3) error will generate an interrupt. FEBEE This bit controls whether line far end block error generates an interrupt by asserting INTB LOW. 0: 1: Line far-end block error will not generate an interrupt. Line far-end block error will generate an interrupt. 38 PRELIMINARY REG − 37H BIT POSITION 7 6 5 4 3 2 1 0 PSL[7:0] PSL[7] PSL[6] PSL[5] PSL[4] PSL[3] PSL[2] PSL[1] PSL[0] CY7C955 Receive Path Signal Label Register NAME READ/WRITE R R R R R R R R DEFAULT This is the path signal label (C2) register byte. This register is either 13H or the first non-13H value detected in the received SONET data stream. REG − 38H BIT POSITION 7 6 5 4 3 2 1 0 PBE[15:0] Reg−38H and Reg−39H will be loaded with the number of path BIP−8 (B3) errors from an internal counter approximately 1 µs after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal BIP−8 (B3) error counter is reset to zero to begin another round of error accumulation. Reading Reg−38H and Reg−39H after the write yields the number of BIP−8 (B3) errors accumulated since the counter was last reset, if overflow has not occurred. PBE[7] PBE[6] PBE[5] PBE[4] PBE[3] PBE[2] PBE[1] PBE[0] Path BIP−8 (B3) Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT 39 PRELIMINARY REG − 39H BIT POSITION 7 6 5 4 3 2 1 0 PBE[15:0] PBE[15] PBE[14] PBE[13] PBE[12] PBE[11] PBE[10] PBE[9] PBE[8] Path BIP−8 (B3) Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 CY7C955 DEFAULT Reg−38H and Reg−39H will be loaded with the number of path BIP−8 (B3) errors from an internal counter approximately 1 µs after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal BIP−8 (B3) error counter is reset to zero to begin another round of error accumulation. Reading Reg−38H and Reg−39H after the write yields the number of BIP−8 (B3) errors accumulated since the counter was last reset, if overflow has not occurred. REG − 3AH BIT POSITION 7 6 5 4 3 2 1 0 PFE[15:0] Reg−3AH and Reg−3BH will be loaded with the number of path FEBE (G1) errors from an internal counter approximately 1 µs after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs after the write operation), these three registers are updated and the internal path FEBE error counter is reset to zero to begin another round of error accumulation. Reading Reg−3AH and Reg−3BH after the write yields the number of path FEBE (G1) errors accumulated since the counter was last reset, if overflow has not occurred. PFE[7] PFE[6] PFE[5] PFE[4] PFE[3] PFE[2] PFE[1] PFE[0] Path Far-End Block Error Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT 40 PRELIMINARY REG − 3BH BIT POSITION 7 6 5 4 3 2 1 0 PFE[15:0] PFE[15] PFE[14] PFE[13] PFE[12] PFE[11] PFE[10] PFE[9] PFE[8] CY7C955 Path Far End Block Error Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT Reg−3AH and Reg−3BH will be loaded with the number of path FEBE (G1) errors from an internal counter approximately 1 µs after a write operation is done to Reg−38H, Reg−39H, Reg−3AH, Reg−3BH, or Reg−00H. At that time (1 µs after the write operation), these three registers are update and the internal path FEBE error counter is reset to zero to begin another round of error accumulation. Reading Reg−3AH and Reg−3BH after the write yields the number of path FEBE (G1) errors accumulated since the counter was last reset, if overflow has not occurred. REG − 3DH BIT POSITION 7 6 5 4 3 2 1 0 BLKBIP This bit controls how path BIP−8 (B3) errors are accumulated. 0: 1: BIP−8 (B3) errors are accumulated and reported in a bit basis. BIP−8 (B3) errors are accumulated and reported in a block basis. Only one BIP−8 error is reported to the upstream path even if more than one path BIP−8 (B3) errors are detected. Unused Unused BLKBIP Unused Unused Unused Unused Unused R/W 0 Path Far-End Block Error Register NAME READ/WRITE DEFAULT 41 PRELIMINARY REG − 40H BIT POSITION 7 6 5 4 3 2 1 0 DB3 This bit generates a path BIP−8 error in the transmit data stream. 0: 1: PAIS This bit generates a path Alarm Indication Signal (AIS) in the transmit data stream. 0: 1: Normal operation. Normal operation. The path BIP −8 (B3) byte is inverted, eight BIP−8 (B3) errors are thus generated per frame PAIS. Unused Unused Unused Unused Unused Unused DB3 PAIS R/W R/W 0 0 CY7C955 Transmit Path Overhead Processor Error Insertion Register NAME READ/WRITE DEFAULT The whole synchronous payload envelope (SPE) together with the H1, H2, and H3 bytes are converted to 1 before scrambling. 42 PRELIMINARY REG − 41H BIT POSITION 7 6 5 4 3 2 1 0 FTPTR Unused FTPTR SOS PLD NDF NSE PSE Unused R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 CY7C955 Transmit Path Overhead Processor Pointer Control Register NAME READ/WRITE DEFAULT This bit enables the insertion of the arbitrary payload pointer value into the last 10 bits of H1, H2. The NDF flag is not automatically changed by this operation. 0: 1: SOS This is the stuff opportunity spacing bit which controls how often stuff events can occur. 0: 1: PLD This bit enables the insertion of the arbitrary payload pointer value into the last 10 bits of H1 and H2 bytes. The value in NDF[3:0] (Reg−46H, bit 7 − bit 4) will also be loaded into the new data flag (NDF) position of the H1 byte. PLD should be used instead of FTPTR for non-diagnostic payload pointer adjustments. 0: 1: Normal operation. The bits contained in Arbitrary Pointer Register (APTR[9:0]) are inserted into H1 and H2 of the transmit data stream. This operation will not affect the interpretation of the pointer in the received data stream, and will only be performed if the value stored in APTR[9:0] is >0 and < 782. Stuff event can occur in every other frame. Insertion of positive pointer movement or negative pointer movement can be done through writing to NSE and PSE (bit 2 and 1 of Reg−41H) Stuff event can occur only once in every four frames. Insertion of positive pointer movement or negative pointer movement can be done through writing to NSE and PSE (bit 2 and 1 of Reg−41H) Normal operation. The bits contained in Arbitrary Pointer Register (APTR[9:0]) are inserted into H1 and H2 of the transmitted data stream. This bit is provided for creating pointer byte errors to diagnose the downstream system. NDF This is the new data flag (NDF) insertion control bit. This bit is ignored if PLD is set to 1. 0: 1: NSE This bit can be used to generate a negative pointer movement. This bit has to be first enabled by setting FIXPTR (Reg−05H, bit 5) to 1. This bit resets to zero automatically after every write to it. 0: 1: PSE This bit can be used to generate a positive pointer movement. This bit has to be first enabled by setting FIXPTR (Reg−05H, bit 5) to 1. This bit resets to zero automatically after every write to it. 0: 1: Default state. A single positive pointer adjustment will be made on the outgoing data stream. This bit will be cleared to zero immediately. Default state. A single negative pointer adjustment will be made on the outgoing data stream. This bit will be cleared to zero immediately The normal NDF pattern (0110) is being transmitted in the first four bytes of H1. The value stored in NDF[3:0] (Reg−46H, bit 7−bit 4) are inserted into the first four bytes of H1. 43 PRELIMINARY REG − 45H BIT POSITION 7 6 5 4 3 2 1 0 APTR[9:0] APTR[7] APTR[6] APTR[5] APTR[4] APTR[3] APTR[2] APTR[1] APTR[0] CY7C955 Transmit Path Overhead Processor Arbitrary Payload Pointer Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DEFAULT Reg−45H and Reg −46H are the arbitrary payload pointer registers. This two registers are used to store the new payload pointer value to be loaded into H1and H2 of the transmitted data stream. The value loaded into these 10 bits has to be greater than or equal to zero and smaller than 782. A legal value stored in APTR[9:0] is not loaded into the data stream until PLD or FTPTR is toggled HIGH. REG − 46H BIT POSITION 7 6 5 4 3 2 1 0 NDF[3:0] These bits are used to store the arbitrary new data flag to be loaded into the transmit data stream. These bits are loaded when NDF is toggled HIGH or when PLD is toggled HIGH. S[1:0] These 2 bits are inserted into the 2 unused bits of H1 whenever PLD, NDF, or FTPTR are toggled HIGH. APTR[9:0] Reg−45H and Reg −46H are the arbitrary payload pointer registers. This two registers are used to store the new payload pointer value to be loaded into H1 and H2 of the transmitted data stream. The value loaded into these 10 bits has to be greater than or equal to zero and smaller than 782. A legal value stored in APTR[9:0] is not loaded into the data stream until PLD or FTPTR is toggled HIGH. NDF[3] NDF[2] NDF[1] NDF[0] S[1] S[2] APTR[9] APTR[8] Transmit Path Overhead Processor Arbitrary Payload Pointer Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 1 0 0 0 0 DEFAULT 44 PRELIMINARY REG − 48H BIT POSITION 7 6 5 4 3 2 1 0 C2[7:0] These bits are inserted in the C2 byte position in the transmit stream. REG − 49H BIT POSITION 7 6 5 4 3 2 1 0 FEBE[3:0] FEBE[3] FEBE[2] FEBE[1] FEBE[0] PRDI G1[2] G1[1] G1[0] C2[7] C2[6] C2[5] C2[4] C2[3] C2[2] C2[1] C2[0] Transmit Path Overhead Processor Signal Label Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 0 1 1 CY7C955 DEFAULT Transmit Path Overhead Processor Path Status Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DEFAULT These bits are used to hold the FEBE value to be inserted into the transmitted data stream. After insertion of these bits into the FEBE location of the next possible frame, FEBE[3:0] will be reset. If the value written to these register bits can still be read back, it just mean that the insertion has not taken place yet. PRDI This bit is used to insert remote defect indication (RDI) into the transmitted data stream. 0: 1: Normal operation. With the PRDI bit of G1 only affected by the setting of AUTOPRDI (Reg−01H, Bit 4) and the alarm conditions. The PRDI bit of G1 is set to 1. G1[2:0] These bits are inserted into the unused bit positions of G1 of every frame. 45 PRELIMINARY REG − 50H BIT POSITION 7 6 5 4 3 2 1 0 OOCDV This bit is the cell delineation status register. 0: 1: OOCDV RXPTYP PASS DISCOR HCSPASS HCSADD DDSCR FIFORST CY7C955 Receive ATM Cell Processor Control and Status Register NAME READ/WRITE R R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 0 DEFAULT This indicates that the cell delineation state machine is in the ‘SYNC’ state and ATM cells are passing though to the receive FIFO. This indicates that the cell delineation state machine is in the ‘PRESYNC’ or ‘HUNT’ state. RXPTYP This bit controls whether odd or even parity is used for RXPRTY. 0: 1: PASS This bit controls whether cells with VPI = 0 and VCI = 0 are dropped. 0: 1: All cells with VPI = 0, VCI = 0 and header matching all the unmasked bits of Reg−52H are dropped. No cell filtering is performed. Odd parity is generated for RDAT[7:0]. Even parity is generated for RDAT[7:0]. DISCOR This bit controls whether header error (HCS) correction is performed. 0: 1: Header error correction is performed. Single bit-errors detected in the header are corrected automatically. Header error correction is not performed. Any HCS error detected is considered uncorrectable. HCSPASS This bit controls whether cells with HCS error are dropped. 0: 1: All cells with an uncorrectable HCS error are dropped. No cells are dropped if the cell delineation state machine is in SYNC state. HCSADD This bit controls whether the coset polynomial x6+x4+x2+1 is added to the HCS byte before HCS comparison is performed. 0: 1: No coset polynomial is added. The coset polynomial x6+x4+x2+1 is added to the HCS byte. DDSCR This bit controls whether cell payload descrambling is performed. 0: 1: Cell payload descrambling is performed. Cell payload descrambling is not performed. FIFORST This bit is the receive FIFO reset bit. 0: 1: Normal receive FIFO operation. All receive FIFO locations are reset and the receive FIFO will ignore all writes. 46 PRELIMINARY REG − 51H BIT POSITION 7 6 5 4 3 2 1 0 OOCDE This bit controls whether a change in cell delineation state generates an interrupt by asserting INTB LOW. 0: 1: HCSE This bit controls whether an HCS error generates an interrupt by asserting INTB LOW. 0: 1: HCS errors will not generate an interrupt. A correctable or uncorrectable HCS error will both generate an interrupt. A change in the cell delineation state will not generate an interrupt. A change in the cell delineation state will generate an interrupt. OOCDE HCSE FIFOE OOCDI CHCSI UHCSI FOVRI Unused CY7C955 Receive ATM Cell Processor Interrupt Register NAME READ/WRITE R/W R/W R/W R R R R 0 0 0 DEFAULT FIFOE This bit controls whether receive FIFO overflow will generate an interrupt by asserting INTB LOW. 0: 1: Receive FIFO overflow will not generate an interrupt. Receive FIFO overflow will generate an interrupt. OOCDI This is the change of cell delineation interrupt bit. This bit resets as Reg−51H is being read. 0: 1: There is no change in the loss of cell delineation state. There is a change from the PRESYNC state to SYNC state or from the SYNC state to the HUNT state. CHCSI This is the correctable HCS error detection bit. This bit resets as Reg−51H is being read. 0: 1: No correctable HCS error has been detected since Reg−51H was last read. One or more than one correctable HCS errors have been detected since Reg−51H was last read. UHCSI This is the uncorrectable HCS error detection bit. This bit resets as Reg−51H is being read. 0: 1: No uncorrectable HCS error has been detected since Reg−51H was last read. One or more than one uncorrectable HCS errors have been detected since Reg−51H was last read. FOVRI This is the receive FIFO overflow interrupt bit. This bit resets as Reg−51H is being read. 0: 1: No receive FIFO overflow has occurred since Reg−51H was last read. Receive FIFO overflow has occurred since Reg−51H was last read. 47 PRELIMINARY REG − 52H BIT POSITION 7 6 5 4 3 2 1 0 GFC[3:0] GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP CY7C955 Receive ATM Cell Processor Match Header Pattern Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DEFAULT These are the Generic Flow Control (GFC) register bits. If the PASS bit (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0, and with other parts of their header matching all the unmasked bits of this register will be dropped. Each bit of this register can be masked by its corresponding bit in Reg−53H. Masked bits are not compared. PTI[2:0] These are the Payload Type Indicator (PTI) register bits. If the PASS bit (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0, and with other parts of their header matching all the unmasked bits of this register will be dropped. Each bit of this register can be masked by its corresponding bit in Reg−53H. Masked bits are not compared. CLP This is the Cell Loss Priority (CLP) register bit. If the PASS bit (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0,and with other parts of their header matching all the unmasked bits of this register will be dropped. Each bit of this register can be masked bits corresponding bit in Reg−53H. Masked bits are not compared. 48 PRELIMINARY REG − 53H BIT POSITION 7 6 5 4 3 2 1 0 MGFC[3:0] MGFC[3] MGFC[2] MGFC[1] MGFC[0] MPTI[2] MPTI[1] MPTI[0] MCLP CY7C955 Receive ATM Cell Processor Match Header Mask Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DEFAULT This is the mask for the Generic Flow Control register. A HIGH in any bit of this register unmasks the corresponding bit of Reg−52H and allows it to be compared with the current ATM cell. If PASS (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0, and other parts of their header matching all the unmasked bits of Reg−52H are dropped. MPTI[2:0] This is the mask for the Payload Type Indicator register. A HIGH in any bit of this register unmasks the corresponding bit of Reg−52H and allows it to be compared with the current ATM cell. If PASS (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0, and other parts of their header matching all the unmasked bits of Reg−52H are dropped. MCLP This is the mask for the Cell Loss Priority (CLP) register. A HIGH in any bit of this register unmasks the corresponding bit of Reg−52H and allows it to be compared with the current ATM cell. If PASS (Reg−50H, bit 5) is LOW, ATM cells with VPI = 0, VCI = 0, and other parts of their header matching all the unmasked bits of Reg−52H are dropped. REG − 54H BIT POSITION 7 6 5 4 3 2 1 0 CHCS[7:0] Reg−54H and Reg−55H will load the number of correctable HCS errors from an internal counter approximately 200 ns after a write operation is done to Reg−54H, Reg−55H, or Reg−00H. At that time (200 ns after the write operation), this register is updated and the internal correctable HCS error counter is reset to zero to begin another round of error accumulation. Reading Reg−54H and Reg–55H after the write yields the number of correctable HCS errors accumulated since the counter was last reset, if overflow has not occurred. CHCS[7] CHCS[6] CHCS[5] CHCS[4] CHCS[3] CHCS[2] CHCS[1] CHCS[0] Receive ATM Cell Processor Correctable HCS Error Count Register NAME READ/WRITE R R R R R R R R DEFAULT 49 PRELIMINARY REG − 55H BIT POSITION 7 6 5 4 3 2 1 0 UHCS[7:0] UHCS[7] UHCS[6] UHCS[5] UHCS[4] UHCS[3] UHCS[2] UHCS[1] UHCS[0] CY7C955 Receive ATM Cell Processor Uncorrectable HCS Error Count Register NAME READ/WRITE R R R R R R R R DEFAULT Reg−54H and Reg−55H will load the number of uncorrectable HCS errors from an internal counter approximately 200 ns after a write operation is done to Reg−54H, Reg−55H, or Reg−00H. At that time (200 ns after the write operation), this register is updated and the internal uncorrectable HCS error counter is reset to zero to begin another round of error accumulation. Reading Reg−54H and Reg.–55H after the write yields the number of uncorrectable HCS errors accumulated since the counter was last reset, if overflow has not occurred. REG − 56H BIT POSITION 7 6 5 4 3 2 1 0 RCELL[18:0] Reg−56H, Reg−57H, and Reg−58H will load the number of cells received from an internal counter approximately 200ns after a write operation is done to Reg−54H, Reg−55H, Reg−56H, Reg−57H, Reg−58H, or Reg−00H. At that time (200ns after the write operation), this register is updated and the internal receive cell counter is reset to zero to begin another round of accumulation. Reading Reg−56H, Reg−57H, and Reg−58H after the write yields the number of cells received since the counter was last reset, if overflow has not occurred. RCELL[7] RCELL[6] RCELL[5] RCELL[4] RCELL[3] RCELL[2] RCELL[1] RCELL[0] Receive ATM Cell Processor Receive Cell Counter Register NAME READ/WRITE R R R R R R R R DEFAULT 50 PRELIMINARY REG − 57H BIT POSITION 7 6 5 4 3 2 1 0 RCELL[18:0] RCELL[15] RCELL[14] RCELL[13] RCELL[12] RCELL[11] RCELL[10] RCELL[9] RCELL[8] CY7C955 Receive ATM Cell Processor Receive Cell Counter Register NAME READ/WRITE R R R R R R R R DEFAULT Reg−56H, Reg−57H, and Reg−58H will load the number of cells received from an internal counter approximately 200 ns after a write operation is done to Reg−54H, Reg−55H, Reg −56H, Reg−57H, Reg−58H, or Reg−00H. At that time (200 ns after the write operation), this register is updated and the internal receive cell counter is reset to zero to begin another round of accumulation. Reading Reg−56H, Reg−57H, and Reg−58H after the write yields the number of cells received since the counter was last reset, if overflow has not occurred. REG − 58H BIT POSITION 7 6 5 4 3 2 1 0 RCELL[18:0] Reg−56H, Reg−57H, and Reg−58H will load the number of cells received from an internal counter approximately 200 ns after a write operation is done to Reg−54H, Reg−55H, Reg −56H, Reg−57H, Reg−58H, or Reg−00H. At that time (200 ns after the write operation), this register is updated and the internal receive cell counter is reset to zero to begin another round of accumulation. Reading Reg−56H, Reg−57H, and Reg−58H after the write yields the number of cells received since the counter was last reset, if overflow has not occurred. Unused Unused Unused Unused Unused RCELL[18] RCELL[17] RCELL[16] R R R Receive ATM Cell Processor Receive Cell Counter Register NAME READ/WRITE DEFAULT 51 PRELIMINARY REG − 59H BIT POSITION 7 6 5 4 3 2 1 0 RGFCE[3:0] RGFCE[3] RGFCE[2] RGFCE[1] RGFCE[0] FSEN RCALEVEL0 HCSFTR[1] HCSFTR[0] CY7C955 Receive ATM Cell Processor Receive Configuration Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 0 0 DEFAULT This is the Receive Generic Flow Control Enable register. Each bit is logical ANDed with its corresponding bit in the ATM cell header. RGFCE[3] corresponds to the most significant bit of the GFC header. If RGFC[x] is set LOW, then bit x of the serial RGFC output (pin 59) will appear LOW. FSEN This is the fix stuff expectation bit. This command only affects STS−1 frames. 0: 1: No fix stuff bytes are expected in the STS−1 payload. Fix stuff bytes are expected in Column 30 and 59 of the received STS−1 frame. RCALEVEL0 This is the receive cell available (RCA) pin empty definition control register. 0: 1: RCA is an active LOW indication for the receive FIFO being 4 bytes from empty. RCA is an active LOW indication for the receive FIFO being empty. HCSFTR[1:0] This is the HCS cell acceptance threshold register. These bits control how many consecutive error-free cells are needed for the Receive ATM cell processor to convert from detection mode to correction mode. 11: 10: 01: 00: 7 cells with no HCS error is needed before the 8th cell is accepted. Correction mode is entered immediately after that. 3 cells with no HCS error is needed before the 4th cell is accepted. Correction mode is entered immediately after that. 1 cell with no HCS error is needed before the 2nd cell is accepted. Correction mode is entered immediately after that. All cell with no HCS error is accepted. Correction mode is entered immediately after that. 52 PRELIMINARY REG − 60H BIT POSITION 7 6 5 4 3 2 1 0 FIFOE FIFOE TSOCI FOVRI DHCS Unused HCSADD DDSCR FIFORST R/W R/W R/W 1 0 0 CY7C955 Transmit ATM Cell Processor Control and Status Register NAME READ/WRITE R/W R R R/W 0 0 DEFAULT This bit controls whether transmit FIFO overflow or misplaced transmit start of cell (TSOC) will generate an interrupt. 0: 1: Transmit FIFO overflow and misplaced TSOC will not generate an interrupt. Transmit FIFO overflow or misplaced TSOC (TSOC appearing not with the first byte of an ATM cell) will generate an interrupt. TSOCI This is the transmit start of cell interrupt bit. This bit resets as Reg−60H is being read. 0: 1: No TSOC error has occurred since Reg −60H was last read. TSOC has occurred at times other than at the beginning of an ATM cell. The internal 53-byte cell length counter is reset to zero immediately if such an error occurs and the incomplete ATM cell is discarded. FOVRI This is the transmit FIFO overflow interrupt bit. This bit resets as Reg−60H is being read. 0: 1: No transmit FIFO overflow has occurred since Reg−60H was last read. Transmit FIFO overflow has occurred since Reg−60H was last read. HCSADD This bit controls whether the coset polynomial x6+x4+x2+1 is added to the HCS byte before the ATM cell is inserted into the Synchronous Payload Envelope (before SONET scrambling if enabled). 0: 1: No coset polynomial is added. The coset polynomial x6+x4+x2+1 is added to the HCS byte. This is equivalent to substituting the HCS byte with (HCS byte XOR 01010101). DDSCR This bit controls whether cell payload scrambling is performed. 0: 1: Cell payload scrambling is performed. Cell payload scrambling is not performed. FIFORST This bit is the transmit FIFO reset bit. 0: 1: Normal transmit FIFO operation. All transmit FIFO locations are reset and the transmit FIFO will ignore all writes. 53 PRELIMINARY REG − 61H BIT POSITION 7 6 5 4 3 2 1 0 GFC[3:0] GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP CY7C955 Transmit ATM Cell Processor Unassigned Cell Header Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 DEFAULT These are the transmit Generic Flow Control (GFC) register bits. The bits in this register are appended to VPI = 0, and VCI = 0 before adding to the transmit data stream as idle cells. Idle cells are transmitted whenever there are no complete ATM cells in the transmit FIFO. PTI[2:0] These are the transmit Payload Type Indicator (PTI) register bits. The bits in this register are appended to VPI = 0, and VCI = 0 before adding to the transmit data stream as idle cells. Idle cells are transmitted whenever there are no complete ATM cells in the transmit FIFO. CLP This is the transmit Cell Loss Priority (CLP) register bit. The bits in this register are appended to VPI = 0, and VCI = 0 before adding to the transmit data stream as idle cells. Idle cells are transmitted whenever there are no complete ATM cells in the transmit FIFO. REG − 62H BIT POSITION 7 6 5 4 3 2 1 0 ICP[7:0] This register contains the octet to be placed in each byte of the transmitted idle cells. When there are no user ATM cells available for transmission, the Transmit ATM Cell Processor generates its own idle cells based on setting in Reg−61H and 62H. Idle cells allow CY7C955 to perform cell rate decoupling. ICP[7] ICP[6] ICP[5] ICP[4] ICP[3] ICP[2] ICP[1] ICP[0] Transmit ATM Cell Processor Unassigned Cell Payload Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 1 1 0 1 0 1 0 DEFAULT 54 PRELIMINARY REG − 63H BIT POSITION 7 6 5 4 3 2 1 0 TXPTYP This is the polarity control bit for the interpretation of TXPRTY. 0: 1: TXPRTY is the odd parity input for TDAT[7:0]. TXPRTY is the even parity input for TDAT[7:0]. TXPTYP TXPRTYE Unused TXPRTYI FIFODP[1] FIFODP[0] TCALEVEL0 Unused R R/W R/W R/W 0 0 0 0 CY7C955 Transmit ATM Cell Processor FIFO Control Register NAME READ/WRITE R/W R/W 0 0 DEFAULT TXPRTYE This is the transmit parity error interrupt enable register. 0: 1: Transmit parity error will not pull INTB (pin 108) LOW but will still be indicated on TXPRTYI. Transmit parity error will pull INTB (pin 108) LOW as well as setting TXPRTYI. TXPRTYI This is the transmit parity error interrupt register. This bit resets when Reg−63H is being read. 0: 1: No transmit parity error has been detected since Reg−63H was last read. Transmit parity error has been detected since Reg−63H was last read. FIFODP[1:0] This bit controls the transmit cell available (TCA) pin definition. Note that this register only determines when TCA (pin 86) is to be deasserted. The transmit FIFO is always 4 cells deep regardless of the setting of this register. This means that interrupt for FIFO overflow, if enabled by FIFOE (Reg−60H, bit 7), will only occur if a write is attempted on a FIFO that is already filled up with all 4 cells. 11: 10: 01: 00: TCA will go LOW when transmit FIFO is 1 cell full (if TCALEVEL = 1) or 4 bytes away from 1 cell full (if TCALEVEL = 0). TCA will go LOW when transmit FIFO is 2 cells full (if TCALEVEL = 1) or 4 bytes away from 2 cells full (if TCALEVEL = 0). TCA will go LOW when transmit FIFO is 3 cells full (if TCALEVEL = 1) or 4 bytes away from 3 cells full (if TCALEVEL = 0). TCA will go LOW when transmit FIFO is 4 cells full (if TCALEVEL = 1) or 4 bytes away from 4 cells full (if TCALEVEL = 0). TCALEVEL0 This is the transmit cell available (TCA) pin transition definition control register. 0: 1: TCA will go LOW when transmit FIFO is N cells full. N is determined by value in FIFODP[1:0] (Reg−63H, bit 2−3). TCA will stay LOW when transmit FIFO is within 4 bytes from N cells full. N is determined by value in FIFODP[1:0] (Reg−63H, bit 2−3). 55 PRELIMINARY REG − 64H BIT POSITION 7 6 5 4 3 2 1 0 TCELL[18:0] TCELL[7] TCELL[6] TCELL[5] TCELL[4] TCELL[3] TCELL[2] TCELL[1] TCELL[0] CY7C955 Transmit ATM Cell Processor Transmit Cell Counter Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT Reg−64H, Reg−65H, and Reg−66H will load the number of cells transmitted from an internal counter approximately 200 ns after a write operation is done to Reg−64H, Reg−65H, Reg−66H, or Reg−00H. At that time (200 ns after the write operation), this register is updated and the internal transmit cell counter is reset to zero or one (depending on whether a cell transmission has occurred while the write occurs) to begin another round of accumulation. Reading Reg−64H, Reg−65H, and Reg−66H after the write yields the number of cell transmitted since the counter was last reset, if overflow has not occurred. TCELL[18:0] should be polled once a second to prevent the register from being saturated. REG − 65H BIT POSITION 7 6 5 4 3 2 1 0 TCELL[18:0] Reg−64H, Reg−65H, and Reg−66H will load the number of cells transmitted from an internal counter approximately 200 ns after a write operation is done to Reg−64H, Reg−65H, Reg−66H, or Reg−00H. At that time (200 ns after the write operation), this register is updated and the internal transmit cell counter is reset to zero or one (depending on whether a cell transmission has occurred while the write occurs) to begin another round of accumulation. Reading Reg−64H, Reg−65H, and Reg−66H after the write yields the number of cell transmitted since the counter was last reset, if overflow has not occurred. TCELL[18:0] should be polled once a second to prevent the register from being saturated. TCELL[15] TCELL[14] TCELL[13] TCELL[12] TCELL[11] TCELL[10] TCELL[9] TCELL[8] Transmit ATM Cell Processor Transmit Cell Counter Register NAME READ/WRITE R R R R R R R R 0 0 0 0 0 0 0 0 DEFAULT 56 PRELIMINARY REG − 66H BIT POSITION 7 6 5 4 3 2 1 0 TCELL[18:0] Unused Unused Unused Unused Unused TCELL[18] TCELL[17] TCELL[16] R R R 0 0 0 CY7C955 Transmit ATM Cell Processor Transmit Cell Counter Register NAME READ/WRITE DEFAULT Reg−64H, Reg−65H, and Reg−66H will load the number of cells transmitted from an internal counter approximately 200 ns after a write operation is done to Reg−64H, Reg−65H, Reg−66H, or Reg−00H. At that time (200 ns after the write operation), this register is updated and the internal transmit cell counter is reset to zero or one (depending on whether a cell transmission has occurred while the write occurs) to begin another round of accumulation. Reading Reg−64H, Reg−65H, and Reg−66H after the write yields the number of cells transmitted since the counter was last reset, if overflow has not occurred. TCELL[18:0] should be polled once a second to prevent the register from being saturated. 57 PRELIMINARY REG − 67H BIT POSITION 7 6 5 4 3 2 1 0 TGFCE[3:0] TGFCE[3] TGFCE[2] TGFCE[1] TGFCE[0] FSEN H4INSB FIXBYTE[1] FIXBYTE[0] CY7C955 Transmit ATM Cell Processor Transmit Configuration Register NAME READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 0 0 DEFAULT This is the Transmit Generic Flow Control Enable register. Each bit of this register corresponds to a bit in the GFC field of the transmitted ATM cell headers. If TGFCE[x] is set HIGH, bit x of the GFC field in the transmitted ATM cell headers will be using the bit value collected from the TGFC (pin 52) pin (see description of Drop Side Transmit Interface). If TGFCE[x] is LOW, bit x will be derived from either TDAT (if transmit FIFO has at least one cell available) or from the Idle/Unassigned header register (if transmit FIFO has less than 1 cell available). FSEN This is the fix stuff enable bit. This bit will only affect the STS−1 frame. 0: 1: No stuffing is performed. Column 30 and 59 of the STS−1 frame contains fix stuff bytes. The contents for the fix stuff byte is controlled by FIXBYTE[1:0] (Reg−67H, bit 0 −1). H4INSB This bit controls the contents of H4 byte. 0: 1: H4 byte represents the cell indicator offset value. H4 byte is set to 00H. FIXBYTE[1:0] This register holds the number to be used in the fixed byte columns. 11: 10: 01: 00: FFH is inserted into the fixed byte columns. AAH is inserted into the fixed byte columns. 55H is inserted into the fixed byte columns. 00H is inserted into the fixed byte columns. 58 PRELIMINARY REG − 80H BIT POSITION 7 6 5 4 3 2 1 0 HIZDATA This is the data bus three-state control bit. 0: 1: HIZIO This is the input output three-state control bit. 0: 1: Normal operation. Normal operation. This data bus is held at HIGH impedance. Register reading is disabled but writing is still possible. Unused Unused Unused Unused Unused Unused HIZDATA HIZIO W R/W 0 CY7C955 Test Control Register NAME READ/WRITE CY7C955 DEFAULT All I/Os except the data bus are being held at the HIGH impedance state. The CY7C955 read/write is still possible. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. –40°C to +125°C Ambient Temperature under Bias ................ −40°C to +85°C Supply Voltage to Ground Potential ............... –0.5V to +6.0V DC Input Voltage............................................ –0.5V to +7.0V DC Input Current ..............................................................±20 mA Static Discharge Voltage ................................................± 2000V (per MIL-STD-883, Method 3015) Latch-Up Current ............................................................±100 mA Lead Temperature ........................................................300°C Maximum Junction Temperature ..................................155°C Maximum Power Dissipation ........................................ 1.5 W Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% 59 PRELIMINARY Electrical Characteristics Over the Operating Range Parameter VIHP VILP VIDIFF IIHP IILP VOHP VOLP VODIFF VSIHP VAILP Description Input HIGH Voltage Input LOW Voltage Input Differential Voltage PECL Input HIGH Current[3] PECL Input LOW Current[3] Output HIGH Voltage Output LOW Voltage Output Differential Voltage Input HIGH Voltage Input LOW Voltage 0.75VAVG VIN = VCC[2] VIN = 2.5 Terminated by 50Ω to VCC[2] –1.33V –200 VCC[2] –1.03 VCC[2] –1.92 0.6[6] VCC[2] –1.03 2.5 200 Test Conditions Min. CY7C955 Max. VCC[1] 2500 500 Unit V V mV µA µA PECL compatible Input Pins (RXD±, RRCLK±, ALOS± TRCLK±) PECL compatible Output Pins (RXDO±, TXD±, TXC±) VCC[2] –0.7 VCC[2] –1.62 V V V V VCC[2] –1.62 2.0 –0.3 –10 −200 20 –10 –10 –10 VIL = 0V VIH = VDD VIL = 0V VIH = VDD VIL = 0V VDD +0.3 0.8 10 −20 200 10 10 10 V PECL compatible Input Pin (ALOS–) When ALOS+ is grounded TTL compatible Input Pins VIHT VILT IIHPU IILPU IIHPD IILPD IIH IIL Input HIGH Voltage Input LOW Voltage Input HIGH Current for Internal Pull-Up Pins VIH = VDD Input LOW Current for Internal Pull-Up Pins[3] Input HIGH Current for Internal Pull-Down Pins[3] Input LOW Current for Internal Pull-Down Pins[3] Input HIGH Current for Pins Without Pull-Up or Pull-Down Resistors[3] Input LOW Current for Pins Without Pull-Up or Pull-Down Resistors[3] Output LOW Voltage Output HIGH Voltage[4] Three-state Leakage Output Short Circuit Current Operational Current Standby Current [4] V V µA µA µA µA µA µA TTL compatible Output Pins VOLT VOHT IOZ IOST IDD IDDS VDD = 4.75V, IOL = 12 mA for INTB and TCLK and 8 mA for all others VDD = 4.75V, IOH = 12 mA for TCLK and 8 mA for all others DATA[0:7] VOUT=0V [5] 0.4 2.4 –10 –15 10 –90 210[7] 75 V V µA mA mA mA Operating Current Rate 0 = 0 (51.84 Mbps, STS–1) Rate 0 = 1 (155.52 Mbps, STS–3c/ STM–1) RSTB = 0, or RESET (Reg–00H, bit 7) = 1 Notes: 2. RXVDD for RXD±, RRCLK±, and ALOS±, RXDO±; TXVDD for TRCLK±, TXD± and TXC±. 3. Current flowing out of the chip has a positive value, current flowing into the chip has a negative value. 4. Maximum leakage current of INTB output at VOHT = 900 µA. 5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 6. Typical is 0.75VAVG. 7. Conditions: Outputs unloaded; VDD = 5.5V; TXD ± = RXD ± = OPEN. 60 PRELIMINARY Capacitance Parameter CIN COUT CIO Description Input pin capacitance Output pin capacitance Input / Output pin capacitance Max. 7 7 7 CY7C955 Unit pF pF pF AC Test Loads and Waveforms 5V OUTPUT R1=910Ω R2=510Ω CL < 30 pF (Includes fixture and probe capacitance) R1 CL R2 CL RL VCC – 1.33 RL =50 Ω CL < 5 pF (Includes fixture and probe capacitance) 7C955-12 (a) TTL AC Test Load (b) PECL AC Test Load 3.0V 3.0V 2.0V GND ≤ 1 ns 1.0V 2.0V 1.0V ≤ 1 ns 7C955-13 VIHE 80% VILE 20% VIHE 80% 20% VILE ≤ 1 ns 7C955-14 ≤ 1 ns (c) TTL Input Test Waveform (d) PECL Input Test Waveform Switching Characteristics Over the Operating Range Parameter Microprocessor Interface Read Cycle tSAR tHRA tSAL tHLA tPL tSLR tHRL tSRD tHRD tSRI Valid Address to Read Set-Up Read to Address Invalid Hold Valid Address to Address Latch Enable Set-Up Address Latch Enable to Address Invalid Hold Address Latch Enable Pulse Width Address Latch Enable to Read Set-Up Read to Address Latch Enable Hold Read to Valid Data Set-Up Read to Data Invalid Hold Read to Interrupt Inactive 25 5 20 10 20 0 5 80 20 50 ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit Microprocessor Interface Write Cycle tSAW tSDW tSAL tHLA tPL tSLW Valid Address to Write Set-Up Valid Data to Write Set-Up Valid Address to Address Latch Enable Set-Up Address Latch Enable to Address Invalid Hold Address Latch Enable Pulse Width Address Latch Enable to Write Set-Up 25 20 20 10 20 0 ns ns ns ns ns ns 61 PRELIMINARY Switching Characteristics Over the Operating Range (continued) Parameter tHWL tHWD tHWA tPW Write to Data Invalid Hold Write to Address Invalid Hold Write Pulse Width Description Write to Address Latch Enable Hold Min. 5 5 5 40 Max. CY7C955 Unit ns ns ns ns Line Interface (Receive Side) Timing tR fR tSDC tHCD RRCLK± Duty Cycle RRCLK± Frequency Tolerance[8, 9] RXD± Stable to RRCLK± Rising Edge Setup Time. RBYP = 1 RRCLK± State Change to RXD Unstable Hold Time. RBYP = 1 19.44 MHz or 6.48 MHz (RBYP = 0) 30 −250 2 1 70 250 % ppm ns ns Receive Side Alarm Timing tDCR RCLK HIGH to RALM or RFP Valid Delay 2 20 ns Line Interface (Transmit Side) Timing tT fT tDTO tDTD TRCLK± Duty Cycle TRCLK± Frequency Tolerance TCLK HIGH to TFPO Valid Delay TXC± LOW to TXD± Valid Delay 19.44 MHz or 6.48 MHz (TBYP = 0) 30 –250 3 –2 70 250 20 2 % ppm ns ns UTOPIA Interface (Receive Side) Timing [TSEN = 0] fRF tRF tSRC tHCR tDCD RFCLK Frequency RFCLK Duty Cycle RRDENB Stable to RFCLK HIGH Set-Up RFCLK HIGH to RRDENB Unstable Hold RFCLK HIGH to RSOC / RCA / RXPRTY / RDAT [7:0] Valid Delay 40 10 1 2 20 33 60 MHz % ns ns ns UTOPIA Interface (Receive Side) Timing [TSEN = 1] fRF tRF tSRC tHCR tDCA tDCD tDCT RFCLK Frequency RFCLK Duty Cycle RRDENB Stable to RFCLK HIGH Set-Up RFCLK HIGH to RRDENB Unstable Hold RFCLK HIGH to RCA Valid Delay RFCLK HIGH to RSOC / RXPRTY / RDAT [7:0] Valid Delay RFCLK HIGH to RSOC / RXPRTY / RDAT [7:0] Three-state Delay 40 10 1 2 2 2 −1 20 20 20 33 60 MHz % ns ns ns ns ns GFC (RECEIVE SIDE) TIMING tDCG RCLK HIGH to RGFC / RCP Valid Delay 10 ns UTOPIA INTERFACE (TRANSMIT SIDE) TIMING fTF tTF tSTC TFCLK Frequency TFCLK Duty Cycle TWRENB / TDAT[7:0] / TXPRTY / TSOC Stable to TFCLK HIGH Set-Up 40 10 33 60 MHz % ns Notes: 8. Not Tested. 9. See description on Receive Clock Recovery (RCR) page 10 62 PRELIMINARY Switching Characteristics Over the Operating Range (continued) Parameter tHCT tDTT Description TFCLK HIGH to TWRENB / TDAT[7:0] / TXPRTY / TSOC Unstable Hold TFCLK HIGH to TCA Valid Delay Min. 1 2 20 Max. CY7C955 Unit ns ns GFC (Transmit Side) Timing tSGT tHTG tDTP TGFC Stable to TCLK High Set-Up TCLK High to TGFC Unstable Hold TCLK High to TCP Valid Delay 10 1 –1 10 ns ns ns Switching Waveforms Microprocessor Interface Read Cycle A[7:0] VALID ADDRESS tSAL tPL ALE tHLA tHRA tSLR tSAR (RDB + CSB) tSRD tHRL tHRD D[7:0] VALID DATA tSRI INTB 7C955–15 63 PRELIMINARY Switching Waveforms (continued) Microprocessor Interface Write Cycle CY7C955 A[7:0] VALID ADDRESS tSAL tPL ALE tHLA tHWA tSLW tSAW tPW tHWL (WRB + CSB) tSDW tHWD D[7:0] VALID DATA 7C955–16 Receive Side Line Interface Timing RXD± tSDC tHCD RRCLK± 7C955–17 64 PRELIMINARY Switching Waveforms (continued) Receiver Alarm Interface Timing CY7C955 RCLK tDCR RALM / RFP 7C955–18 Transmit Side Line Interface Timing TCLK tDCT TFPO TXC± tDCD TXD± 7C955–19 65 PRELIMINARY Switching Waveforms (continued) Utopia Interface (Receive Side) Timing [TSEN = 0] CY7C955 RFCLK tSRC tHCR RRDENB tDCD RDAT[7:0] / RCA / RSOC / RXPRTY 7C955–20 66 PRELIMINARY Switching Waveforms (continued) Utopia Interface (Receive Side) Timing [TSEN=1] CY7C955 RFCLK tSRC tHCR RRDENB tDCA RCA tDCT RDAT[7:0] / RSOC / RXPRTY tDCD VALID RDAT[7:0] / RSOC / RXPRTY 7C955–21 GFC Interface (Receive Side) Timing RCLK tDCG RGFC / RCP 7C955–22 67 PRELIMINARY Switching Waveforms (continued) Utopia Interface (Transmit Side) Timing CY7C955 RCLK tSTC RRDENB tHCT tDTT RCA 7C955–23 GFC Interface (TransmitSide)Timing TCLK tSGT TGFC tHTG tDTP TCP 7C955–24 68 PRELIMINARY Functional Timing Diagram Utopia Interface (Transmit Side) Functional Timing Figure 8 shows, in a nutshell, all the functional timing requirements of the Transmit Side Utopia Interface. The Transmit Side Utopia Interface consists of TDAT[7:0], TXPRTY, TSOC, TWRENB, TCA, and TFCLK. TDAT[7:0] ATM cells are expected to be clocked into the Utopia FIFO interface through TDAT[7:0] with the 1st header byte first followed by the remaining 52 bytes of headers and payload. The fifth header byte (HEC) is required but is being ignored and replaced by the HCS octet generated by the Transmit ATM Cell Processor. TXPRTY The TXPTYP (Reg−63, bit 7) and TXPRTYE (Reg−63H, bit 6) can be set to make the Transmit Side Utopia Interface accept odd, even, or no parity TXPRTY inputs. TSOC A HIGH TSOC input is expected along with the first header byte of an ATM cell. If TSOC is absent, the Transmit ATM Cell Processor will automatically generate a TSOC based on previous TSOC positions, no interrupt will be sent. However, if TSOC is misplaced, the previously stored incomplete ATM cell will be discarded and the transmit FIFO pointer will be set back to the beginning of the same cell. A misplaced event will cause CY7C955 TSOCI (Reg−60H, bit 6) to go HIGH, and causes an interrupt also if FIFOE (Reg−60H, bit 7) is enabled. TWRENB This transmit FIFO write enable bit (TWRENB) should be pulled LOW whenever there is an ATM byte to send. It can be deactivated at any time to pause the writing process—not necessarily at cell boundaries. TCA The transmit cell available (TCA) is affected by TCAINV (Reg−01H, bit 3) and TCALEVEL0 (Reg−63H, bit 94). TCAINV determines the active polarity of the TCA signal, and TCALEVEL0 controls the meaning of TCA going active. If TCALEVEL0 = 0, TCA will be deasserted when the transmit FIFO is 4 writes from full. If TCALEVEL0 = 1, TCA will be deasserted when the FIFO is full and can accept no more writes. TFCLK TFCLK has to be a clock of 33 MHz or less. Although it can be stopped if necessary, it is not recommended because some registers and pins synchronized by this clock will not be updated. If this clock is stopped, the line side interface will still be able to transmit the cells already stored into the FIFO. After that, idle cells will be transmitted. TFCLK TDAT[7:0] X H1 H2 H3 P44 P45 P46 P47 P48 X H1 TSOC TXPRTY X X TCA LEVEL 0 = 1 TCA TWNRENB Figure 8. Transmit FIFO 69 PRELIMINARY Functional Timing Diagram (continued) Utopia Interface (Receive Side) Functional Timing Figure 9 shows, in a nutshell, all the functional timing requirements of the Receive Side Utopia Interface. The Receive Side Utopia Interface consists of TSEN, RDAT[7:0], RXPRTY, RSOC, RRDENB, RCA, and RFCLK. TSEN This three-state enable pin can be used to implement shared Utopia bus architecture for Multi-PHY operation. If TSEN is tied HIGH, RDAT[7:0], RXPRTY, and RSOC will be three-stated if RRDENB is HIGH. If TSEN is pulled LOW, RDAT[7:0], RXPRTY, and RSOC will always assume a logic 1 or logic 0. TSEN has an integrated pull down resistor. RDAT[7:0] CY7C955 ATM cells are clocked out of the Utopia FIFO interface through RDAT[7:0] with the 1st header byte first followed by the remaining 52 bytes of headers and payload. The cell stream can be stopped at anytime by pulling RRDENB HIGH. RXPRTY The RXPTYP (Reg–50, bit 6) can be set to make the receive side Utopia interface produce odd or even parity RXPRTY outputs. RSOC RSOC will go HIGH when RDAT[7:0] contains the first header byte of an ATM cell. RFCLK RDAT[7:0] H1 H2 P43 P44 P45 P46 P47 P48 H1 RSOC RRDENB READ IGNORED RCALEVEL0= 1 RCA RXPRTY Figure 9. Receive FIFO 70 PRELIMINARY Functional Timing Diagram (continued) GFC Interface (Transmit Side) Functional Timing Figure 10 shows the functional timing for the TGFC input with respect to TCLK and TCP. TCP Transmit Cell Pulse toggles HIGH for one clock cycle 6 TCLK periods before the first octet of the next ATM cell is read from the transmit FIFO. TGFC If enabled by TGFCE (Reg-67, bit 4−7), a stable TGFC[3] is expected on the next rising edge of the TCLK after TCP goes HIGH (see Figure 10). All enabled TGFC bits will replace the CY7C955 corresponding GFC bit of the next transmitted assigned ATM cell. Unassigned/ Idle cells will maintain its default content and will not be affected by the TGFC input. GFC Interface (Receive Side) Functional Timing Figure 11 shows the functional timing for the RGFC input with respect to RCLK and RCP. RCP Receive Cell Pulse toggles HIGH whenever the most significant GFC bit (GFC[3]) of an assigned ATM cell header is presented on the RGFC pin. GFC[3] can be present for as long as 1 to 14 RCLK cycles on the RGFC pin, and so RCP can also be HIGH for anywhere between 1 to 14 RCLK cycles. TCLK TCP TGFC X GFC[3] GFC[2] GFC[1] GFC[0] X Figure 10. Transmit GFC Serial Link RCLK RGFCE[3:0]=1111B RCP RGFC GFC[3] CELL N GFC[2] CELL N GFC[1] CELL N GFC[0] CELL N RGFCE[3:0]=1001B RCP RGFC GFC[3] CELL N GFC[0] CELL N Figure 11. Receive GFC Serial Link 71 PRELIMINARY Functional Timing Diagram (continued) Timing Modes Figure 12, 13, and 14 shows how to connect the clock reference for different applications. In the presence of a 155.52 MHz/51.84 MHz primary reference source (PRS). The configuration described in Figure 12 should be used. TBYP is HIGH and RBYP is LOW. The primary reference clock source provides the accurate bit synchronization needed for the transmit data stream. CY7C955 If the application is a LAN termination equipment, the configuration described in Figure 13 should be used. LOOPT (Reg–5H, bit 0) is HIGH to enable loop timing mode. In loop timing mode, The clock recovered from the received data stream is being used to synchronize the transmit datastream. If that clock is lost, RRCLK x 8 will be used as the clock reference. The clocking architecture of the CY7C955 is shown in Figure 14. 19.44 MHz Stratum or free-run reference 19.44 MHz Stratum or free-run reference TRCLK± Input Data RXD± CY7C955 TCLK Input Data RXD± RRCLK± TRCLK± CY7C955 TCLK RRCLK± Figure 12. Clock Synthesis Figure 13. Loop Timing TRCLK± Internal Tx Clock Source A B Clock Synthesizer /8 Internal Rx Clock Source TCLK RXD± Clock Recovery RRCLK± Figure 14. Conceptual Clocking Structure 72 PRELIMINARY Interface Termination and Biasing Schemes PECL Input Termination and Biasing Recommendations Figures 15−19 show how to connect different output types to the CY7C955 PECL inputs. Differential termination and biasing (Figure 15) is required for RXD, and is highly recommended for RRCLK, and TRCLK. Nevertheless it is also possible for the input to accept single-ended signals. If the positive end of a PECL input pair is tied to GND (with or without a pull-down resistor), the negative input will become a single-ended input. This input is self-biased to its threshold at VCC/2. Notice that because the negative input is used, the signal entering the chip through the input are inverted. Figure 15 shows a differential PECL connection. Whenever possible, this differential PECL connection scheme should be used. Differential signals are less susceptible to common-mode noise. CY7C955 Figure 16 shows another possible type of a differential PECL connection. Although this connection is allowed, the method suggested in Figure 15 will give better switching characteristics. Figure 17 shows a CMOS connection; no termination is needed if the trace is kept short. If the trace is long, follow common transmission line termination practices. Figure 18 shows a TTL connection. The 0.01 µF AC-coupling capacitor allows the CY7C955 inputs to self-bias itself to VCC/2. This connection scheme is not suitable for the ALOS input because the signal is close to static. Figure 19 shows how to connect a single-ended PECL connection to the ALOS − input. ALOS is almost a static signal, so the connection must be DC-coupled. A 330Ω resistor to GND is needed, as a current sink is needed for the PECL output to operate correctly. VCC +ve– PECL Output 80Ω TRCLK+ / RRCLK+ / RXD+ 130Ω CY7C955 Vcc 80Ω –ve – PECL Output TRCLK– / RRCLK– / RXD– 130Ω Figure 15. Differential PECL Termination (High Performance) 73 PRELIMINARY CY7C955 +ve– PECL Output 330Ω 100Ω ALOS+ / TRCLK+ / RRCLK+ / RXD+ CY7C955 –ve – PECL Output 330Ω ALOS– / TRCLK– / RRCLK– / RXD– Figure 16. Differential PECL Termination (Low Power) ALOS+ / TRCLK+ / RRCLK+ / RXD+ CY7C955 ALOS– / TRCLK– / RRCLK– / RXD– CMOS Output Figure 17. CMOS Connection 74 PRELIMINARY CY7C955 TRCLK+ / RRCLK+ CY7C955 .01µF TTL Output TRCLK– / RRCLK– Figure 18. TTL Connection ALOS+ CY7C955 Singleended– PECL Output ALOS– 330Ω Figure 19. Single-ended PECL Connection for ALOS Filter Pin Configuration The CY7C955 Phase-locked Loop is designed to meet the Bellcore specifications on jitter generation, jitter transfer, and jitter tolerance. The highly integrated charge pump design drastically reduces the complexity of external filter components. Only a single 0.47-µF non-polar capacitor is needed to provide the damping factor needed to meet the jitter ceiling defined in GR-253. Figure 14 describes how to connect the capacitor across the LF− and LFO pins of the CY7C955. The LF+ pin is to be left unconnected. The 1.0-µF capacitor should have the following characteristics: Breakdown Voltage: Tolerance: Dielectric: Polarity: Size: Example Part Number: Size: 1206 Breakdown: 16V Capacitance: 0.47µF Part Number: 1206YC474JAT1A AVX Corporation Tel: 360 699 8746 16V or higher ±10% or better X7R or better Non-polar or Bipolar 1206 or 1210 (0805 is not available commercially yet) 75 PRELIMINARY The 1.0-µF capacitor should have the following characteristics: Breakdown Voltage: Tolerance: Dielectric: Polarity: Size: Dielectric: X7R Tolerance: ± 5% Size: 1206 Breakdown: 16V Capacitance: 0.47µF Dielectric: X7R Tolerance: ±10% Part Number: EMK316BJ474K 16V or higher ±10% or better X7R or better Non-polar or Bipolar CY7C955 1206 or 1210 (0805 is not available commercially yet) Anderson Electronics Component Distribution Tel: 408 577 1323 FLIP FLOP Data CORE LOGIC Phase Detector Charge Pump VCO Clock LF- LFO 0.47 uF Figure 20. Phase-Locked Loop Capacitor Placement Ordering Information Ordering Code CY7C955-NC CY7C955-NI Document #: 38-00417-D Package Name N128 N128 Package Type 128-Lead Plastic Quad Flat Package 128-Lead Plastic Quad Flat Package Operating Range Commercial Industrial 76 PRELIMINARY CY7C955 Package Diagram 128-Lead Plastic Quad Flatpack 77 PRELIMINARY ADDENDUM - Design Considerations for the CY7C955 This memo outlines current design considerations for the CY7C955 - ATM PHY in reference to the ATM Forum UTOPIA Level 1 specification. Receive FIFO Reset The Receive four-cell FIFO is reset by programming register 0x50(RACP)[0] to a logic '1'. Under this condition the CY7C955 RCA output is not deasserted immediately and the RDATA[7:0] output is not 0x00. The CY7C955 RCA output is held asserted until the end of the current transmission of the cell on the RxUTOPIA bus. The RDATA is hold immediately after the RxFIFO Reset is recognized, while the RCA output is still asserted (indicating a valid cell). 54-Byte Cell on RxUTOPIA Bus CY7C955 Received ATM cells in the RXFIFO can be read out from the RxUTOPIA bus at various throughput. The throughput can be throttled by two ways; one way is by changing the RFCLK frequency; another way is using the RRDENB input and a fixed RFCLK (for more information on the Rx UTOPIA bus operation, refer to the pin description, “Receive UTOPIA Interface” section of the data sheet and the UTOPIA spec Level 1). When the throughput writing into the RxFIFO is greater than the throughput reading out, then, intermittently, the CY7C955 outputs a cell with 54bytes FIFO RST RCA RDATA Figure 21. CY7C955 Receive FIFO Reset Behavior © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.