CY7S1049G
CY7S1049GE
4-Mbit (512K words × 8-bit) Static RAM
with PowerSnooze™
and Error Correcting Code (ECC)
4-Mbit (512K words × 8-bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
ultra-low power Deep-Sleep mode[3]. With Deep-Sleep mode
currents as low as 15 µA, the CY7S1049G/CY7S1049GE
devices combine the best features of fast and low- power SRAMs
in industry-standard package options. The device also features
embedded ECC. logic which can detect and correct single-bit
errors in the accessed location.
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
Features
■
High speed
❐ Access time (tAA) = 10 ns / 15 ns
■
Ultra-low power Deep-Sleep (DS) current
❐ IDS = 15 µA
■
Low active and standby currents
❐ Active Current ICC = 38-mA typical
❐ Standby Current ISB2 = 6-mA typical
■
■
Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
Embedded ECC for single-bit error correction[1, 2]
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
■
1.0-V data retention
■
TTL- compatible inputs and outputs
■
Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil)
molded SOJ
Functional Description
The CY7S1049G/CY7S1049GE[1] is a high-performance
PowerSnooze™ static RAM organized as 512K words × 8 bits.
This device features fast access times (10 ns) and a unique
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O0 through I/O7) and address pins (A0
through A18) respectively.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O0
through I/O7).
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1049G is available in 44-pin TSOP II, and 36-pin
Molded SOJ (400 Mils).
Product Portfolio
Power Dissipation
Product[4]
CY7S1049G(E)18
Range
Industrial
CY7S1049G(E)30
VCC Range (V)
Speed
(ns)
Operating ICC,
(mA)
f = fmax
Deep-Sleep
current (µA)
Typ [5]
Max
Typ [5]
Max
Typ [5]
Max
6
8
–
15
1.65 V–2.2 V
15
–
40
2.2 V–3.6 V
10
38
45
4.5–5.5 V
10
38
45
CY7S1049G(E)
Standby, ISB2
(mA)
Notes
1. This device does not support automatic write back on error detection.
2. SER FIT Rate 2001 V
Storage temperature ................................ –65 C to +150 C
Latch-up current .................................................... > 140 mA
Ambient temperature
with power applied ................................... –55 C to +125 C
Operating Range
Supply voltage
on VCC relative to GND [10] ................. –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z State [10] .................................. –0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range of –40 C to +85 C
Parameter
VOH
VOL
VIH[10, 13]
VIL [10, 13]
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage
Test Conditions
10 ns/ 15 ns
Min
Typ [11]
Max
1.65 V to 2.2 V
VCC = Min, IOH = –0.1 mA
1.4
–
–
2.2 V to 2.7 V
VCC = Min, IOH = –1.0 mA
2
–
–
2.7 V to 3.6 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
[12]
4.5 V to 5.5 V
VCC = Min, IOH = –0.1 mA
–
–
1.65 V to 2.2 V
VCC = Min, IOL = 0.1 mA
–
–
0.2
2.2 V to 2.7 V
VCC = Min, IOL = 2 mA
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 8 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 8 mA
–
–
0.4
1.65 V to 2.2 V
–
1.4
–
VCC + 0.2
2.2 V to 2.7 V
–
2
–
VCC + 0.3
2.7 V to 3.6 V
–
2
–
VCC + 0.3
VCC – 0.5
4.5 V to 5.5 V
–
2
–
VCC + 0.5
1.65 V to 2.2 V
–
–0.2
–
0.4
2.2 V to 2.7 V
–
–0.3
–
0.6
2.7 V to 3.6 V
–
–0.3
–
0.8
4.5 V to 5.5 V
–
–0.5
–
0.8
GND < VIN < VCC
–1
–
+1
Unit
V
V
V
V
A
IIX
Input leakage current
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
–
+1
A
VCC operating supply current
VCC = Max,
IOUT = 0 mA,
CMOS levels
f = 100 MHz
–
38
45
mA
f = 66.7 MHz
–
–
40
Standby current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–
–
15
ICC
ISB1
mA
Notes
10. VIL (min) = –2.0 V and VIH (max) = VCC + 2 V for pulse durations of less than 20 ns.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
12. Guaranteed by design and not tested.
13. For the DS pin, VIH (min) is VCC – 0.2 V and VIL (max) is 0.2 V.
Document Number: 001-95414 Rev. *F
Page 6 of 21
CY7S1049G
CY7S1049GE
DC Electrical Characteristics (continued)
Over the Operating Range of –40 C to +85 C
Parameter
Description
Test Conditions
10 ns/ 15 ns
Min
Typ [11]
Max
Unit
ISB2
Standby current – CMOS inputs Max VCC, CE > VCC – 0.2 V,
DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
6
8
mA
IDS
Deep-Sleep current
–
–
15
µA
Max VCC, CE > VCC – 0.2 V, DS < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
Capacitance
Parameter [14]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC(typ)
All packages
Unit
10
pF
10
pF
Thermal Resistance
Parameter [14]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
44-pin TSOP II Unit
Package
Test Conditions
36-pin SOJ
Package
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52
68.85
C/W
31.48
15.97
C/W
Note
14. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-95414 Rev. *F
Page 7 of 21
CY7S1049G
CY7S1049GE
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms [15]
HI-Z Characteristics:
VCC
50
Output
VTH
Z0 = 50
R1
Output
30 pF*
* Including
JIG and
Scope
(a)
* Capacitive Load Consists
of all Components of the
Test Environment
(b)
All Input Pulses
VHIGH
GND
R2
5 pF*
90%
90%
10%
Rise Time:
> 1 V/ns
10%
(c)
Fall Time:
> 1 V/ns
Parameters
1.8 V
3.0 V
5.0 V
Unit
R1
1667
317
317
R2
1538
351
351
VTH
VCC/2
1.5
1.5
V
VHIGH
1.8
3.0
3.0
V
Note
15. Full-device AC operation assumes a 100-s ramp time from 0 to VCC(min) or 100-s wait time after VCC stabilization.
Document Number: 001-95414 Rev. *F
Page 8 of 21
CY7S1049G
CY7S1049GE
Data Retention Characteristics
Over the Operating Range of –40C to +85 C
Parameter
Conditions [16]
Description
Min
Max
Unit
1.0
–
V
VDR
VCC for data retention
–
ICCDR
Data retention current
VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–
8
mA
tCDR [17]
Chip deselect to data retention
time
–
0
–
ns
tR[17, 18]
Operation recovery time
2.2 V < VCC < 5.5 V
10
–
ns
VCC < 2.2 V
15
–
ns
Data Retention Waveform
Figure 6. Data Retention Waveform [18]
VCC
VCC(min)
DATA RETENTION MODE
VDR = 1.0 V
tCDR
VCC(min)
tR
CE
Notes
16. DS signal must be HIGH during Data Retention Mode.
17. These parameters are guaranteed by design.
18. Full-device operation requires linear VCC ramp from VDR to VCC(min.) 100 s or stable at VCC(min.) 100 s.
Document Number: 001-95414 Rev. *F
Page 9 of 21
CY7S1049G
CY7S1049GE
Deep-Sleep Mode Characteristics
Over the Operating Range of –40 C to +85 C
Parameter
Description
Conditions
Max
Unit
–
15
µA
IDS
Deep-Sleep mode current
tPDS[19]
Minimum time for DS to be LOW –
for part to successfully exit
Deep-Sleep mode
100
–
ns
tDS[20]
DS assertion to Deep-Sleep –
mode transition time
–
1
ms
tDSCD[19]
DS deassertion to chip disable
If tPDS > tPDS(min)
–
100
s
If tPDS < tPDS(min)
–
0
s
300
–
s
tDSCA
VCC = VCC (max), DS < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Min
DS deassertion to chip access If tPDS > tPDS(min)
(Active/Standby)
If tPDS < tPDS(min)
Figure 7. Active, Standby, and Deep-Sleep Operation Modes
Chip
Access
Allowed
Not Allowed
CE
ENABLE/
DISABLE
DON’T CARE
Allowed
DISABLE
ENABLE/
DISABLE
tPDS
DS
tDSCD
tDS
Mode
Active/Standby
Mode
Standby
Mode
Deep Sleep Mode
tDSCA
Standby Active/Standby
Mode
Mode
Notes
19. CE must be pulled HIGH within tDSCD time of DS de-assertion to avoid SRAM data loss.
20. After assertion of DS signal, device will take a maximum of tDS time to stabilize to Deep-Sleep current IDS. During this period, DS signal must continue to be asserted
to logic level LOW to keep the device in Deep-Sleep mode.
Document Number: 001-95414 Rev. *F
Page 10 of 21
CY7S1049G
CY7S1049GE
AC Switching Characteristics
Over the Operating Range of –40 C to +85 C
Parameter [21]
Description
10 ns
15 ns
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
10
–
15
–
ns
tAA
Address to data valid
–
10
–
15
ns
tOHA
Data hold from address change
3
–
3
–
ns
tACE
CE LOW to data valid
–
10
–
15
ns
tDOE
OE LOW to data valid
–
4.5
–
8
ns
0
–
0
–
ns
–
5
–
8
ns
3
–
3
–
ns
–
5
–
8
ns
0
–
0
–
ns
–
10
–
15
ns
tLZOE
OE LOW to low impedance
tHZOE
[22, 23, 24]
OE HIGH to HI-Z
tLZCE
CE LOW to low impedance
tHZCE
CE HIGH to HI-Z [22, 23, 24]
tPU
tPD
Write Cycle
CE LOW to power-up
[22, 23, 24]
[22, 23, 24]
[24]
CE HIGH to power-down
[24]
[25, 26]
tWC
Write cycle time
10
–
15
–
ns
tSCE
CE LOW to write end
7
–
12
–
ns
tAW
Address setup to write end
7
–
12
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
7
–
12
–
ns
tSD
Data setup to write end
5
–
8
–
ns
tHD
Data hold from write end
0
–
0
–
ns
tLZWE
WE HIGH to low impedance [22, 23, 24]
3
–
3
–
ns
–
5
–
8
ns
tHZWE
WE LOW to HI-Z
[22, 23, 24]
Notes
21. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 5 on page 8, unless specified otherwise.
22. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 8. Transition is measured 200 mV from steady state voltage.
23. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
24. These parameters are guaranteed by design.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and WE, CE, signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
26. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be the sum of tHZWE and tSD.
Document Number: 001-95414 Rev. *F
Page 11 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms
Figure 8. Read Cycle No. 1 of CY7S1049G (Address Transition Controlled) [27, 28, 29]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATA I/O
DATAOUT VALID
Figure 9. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [27, 28, 29]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
27. The device is continuously selected. OE = VIL, CE = VIL.
28. WE is HIGH for read cycle.
29. DS is HIGH for chip access.
Document Number: 001-95414 Rev. *F
Page 12 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms (continued)
Figure 10. Read Cycle No. 3 (OE Controlled) [30, 31, 32]
ADDRESS
tRC
CE
tPD
t HZCE
t ACE
OE
t HZOE
t DOE
t LZOE
DATA I /O
HIGH IMPEDANCE
DATA OUT VALID
HIGH
IMPEDANCE
t LZCE
tPU
VCC
SUPPLY
CURRENT
ISB
Notes
30. WE is HIGH for read cycle.
31. Address valid prior to or coincident with CE LOW transition.
32. DS must be HIGH for chip access.
Document Number: 001-95414 Rev. *F
Page 13 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms (continued)
Figure 11. Write Cycle No. 1 (CE Controlled) [33, 34, 35]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
OE
tHZOE
tHD
tSD
DATA I/O
DATAIN VALID
Figure 12. Write Cycle No. 2 (WE Controlled, OE LOW) [33, 34, 35, 36]
tW C
AD D R ES S
t S CE
CE
tS A
tA W
tH A
tP W E
WE
t H ZW E
D ATA I/O
tS D
t LZW E
tH D
D A TA IN VA LID
Notes
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
34. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
35. DS must be HIGH for chip access.
36. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95414 Rev. *F
Page 14 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms (continued)
Figure 13. Write Cycle No. 3 (WE Controlled) [37, 38, 39]
tW C
ADDRESS
tS C E
CE
tA W
tS A
tH A
tP W E
WE
OE
tH Z O E
D A T A I/O
Note 40
tH D
tS D
D A T A IN V A L ID
Notes
37. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE, signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
38. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or DS = VIL.
39. DS must be HIGH for chip access.
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-95414 Rev. *F
Page 15 of 21
CY7S1049G
CY7S1049GE
Truth Table
DS
CE
OE
[41]
X
WE
I/O0–I/O7
Mode
Power
[41]
HIGH-Z
Standby
Standby (ISB)
H
H
X
H
L
L
H
Data out
Read all bits
Active (ICC)
H
L
X
L
Data in
Write all bits
Active (ICC)
H
L
H
H
HI-Z
Selected, outputs disabled
Active (ICC)
L[42]
X
X
X
HI-Z
Deep-Sleep
Deep-Sleep Ultra Low Power (IDS)
ERR Output – CY7S1049GE
Output [43]
0
1
High-Z
Mode
Read operation, no single-bit error in the stored data.
Read operation, single-bit error detected and corrected.
Device deselected / outputs disabled / Write operation
Notes
41. The input voltage levels on these pins should be either at VIH or VIL.
42. VIL on DS must be < 0.2 V.
43. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-95414 Rev. *F
Page 16 of 21
CY7S1049G
CY7S1049GE
Ordering Information
Speed
(ns)
10
Voltage
Range
2.2 V–3.6 V
Ordering Code
Package
Diagram
Package Type (All Pb-free)
CY7S1049G30-10VXI
51-85090 36-pin SOJ
CY7S1049G30-10VXIT
51-85090 36-pin SOJ, Tape and Reel
CY7S1049GE30-10VXI
51-85090 36-pin SOJ, ERR Output
CY7S1049GE30-10VXIT
51-85090 36-pin SOJ, ERR Output, Tape and Reel
Operating
Range
Industrial
Ordering Code Definitions
CY 7 S 1 04 9
G X
XX - XX XX X X X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: X = I
I = Industrial
Pb-free
Package Type: XX = V
V = 36-pin SOJ
Speed: XX = 10
10 = 10 ns
Voltage Range: XX = 30
30 = 2.2 V to 3.6 V
X = blank or E
blank = without ERR output; E = with ERR Output
Process Technology: Revision Code “G” = 65 nm Technology
Data Width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
S = Deep-Sleep feature
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-95414 Rev. *F
Page 17 of 21
CY7S1049G
CY7S1049GE
Package Diagrams
Figure 14. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
51-85090 *G
Figure 15. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-95414 Rev. *F
Page 18 of 21
CY7S1049G
CY7S1049GE
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degrees Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
A
microampere
SOJ
Small-Outline J-lead
s
microsecond
SRAM
Static Random Access Memory
mA
milliampere
TSOP
Thin Small Outline Package
mm
millimeter
TTL
Transistor-Transistor Logic
ns
nanosecond
WE
Write Enable
ohm
ECC
Write Enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-95414 Rev. *F
Symbol
Unit of Measure
Page 19 of 21
CY7S1049G
CY7S1049GE
Document History Page
Document Title: CY7S1049G/CY7S1049GE, 4-Mbit (512K words × 8-bit) Static RAM with PowerSnooze™ and Error Correcting
Code (ECC)
Document Number: 001-95414
Rev.
ECN No.
Orig. of
Change
Submission
Date
*B
5025315
VINI
11/24/2015
Changed status from Preliminary to Final.
*C
5090263
NILE
01/18/2016
Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
*D
5428860
NILE
09/07/2016
Updated Functional Description:
Added Note 1 and referred the same note in “CY7S1049G/CY7S1049GE”.
Updated Maximum Ratings:
Updated Note 10 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding
to Operating Range “2.7 V to 3.6 V” and Test Condition
“VCC = Min, IOH = –4.0 mA”.
Changed minimum value of VIH parameter from 2.2 V to 2 V corresponding to
Operating Range “4.5 V to 5.5 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E
5981584
AESATMP8
12/01/2017
Updated logo and Copyright.
*F
6120487
NILE
04/03/2018
Updated Features:
Referred Note 1 in “Embedded ECC for single-bit error correction”.
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Updated Functional Description:
Added Note 3 and referred the same note at the end of sentence “This device
features fast access times (10 ns) and a unique ultra-low power Deep-Sleep
mode”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-95414 Rev. *F
Description of Change
Page 20 of 21
CY7S1049G
CY7S1049GE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95414 Rev. *F
Revised April 3, 2018
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